Re: [PATCH v13 4/4] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

[Takahiro Kuwano <tkuw584924@gmail.com>]

On 4/21/2022 7:45 PM, Tudor.Ambarus@microchip.com wrote:
> On 4/21/22 12:40, tkuw584924@gmail.com wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>
>> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.
>>
>> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
>> uniform sector sizes are supported. This is due to missing or incorrect
>> entries in SMPT. Fixup for other sector sizes configurations will be
>> followed up as needed.
>>
>> Tested on Xilinx Zynq-7000 FPGA board.
>>
>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>> ---
>> Changes in v13:
>>   - Remove part specific set_4byte_addr_mode()
>>   - Revert SNOR_F_4B_OPCODES
>>   - Add post_sfdp to fix 3 byte erase opcode in 4BAIT
>>
>> Changes in v12:
>>   - Cleanup fixups based on other patches in this series
>>   - Add part specific set_4byte_addr_mode()
>>   - Unset SNOR_F_4B_OPCODES flag to let core to call set_4byte_addr_mode
>>
>> Changes in v11:
>>   - Cleanup fixups based on other patches in this series
>>
>> Changes in v10:
>>   - Cleanup fixups and ID table based on other patches in this series
>>
>> Changes in v9:
>>   - Use late_init() hook to fix mode clocks and writesize
>>   - Use PARSE_SFDP instead of NO_SFDP_FLAGS
>>   - Use MFR_FLAGS for USE_CLSR
>>   - Add comment block to explain about addr mode in post_bfpt_fixups()
>>
>> Changes in v8:
>>   - Call write_disable in error case only
>>   - Use spi_nor_read_reg() helper
>>   - Use nor->bouncebuf instead of variable on stack
>>   - Update ID table to use FLAGS macro
>>
>> Changes in v7:
>>   - Add missing device info table in v6
>>
>> Changes in v6:
>>   - Remove 2Gb multi die pacakge support
>>
>> Changes in v5:
>>   - Add NO_CHIP_ERASE flag to S25HL02GT and S25HS02GT
>>
>> Changes in v4:
>>   - Merge block comments about SMPT in s25hx_t_post_sfdp_fixups()
>>   - Remove USE_CLSR flags from S25HL02GT and S25HS02GT
>>
>> Changes in v3:
>>   - Remove S25HL256T and S25HS256T
>>   - Add S25HL02GT and S25HS02GT
>>   - Add support for multi-die package parts support
>>   - Remove erase_map fix for top/split sector layout
>>   - Set ECC data unit size (16B) to writesize
>>
>>  drivers/mtd/spi-nor/spansion.c | 66 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 66 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
>> index 952d4383f9da..e56c48c3280b 100644
>> --- a/drivers/mtd/spi-nor/spansion.c
>> +++ b/drivers/mtd/spi-nor/spansion.c
>> @@ -203,6 +203,56 @@ static int cypress_nor_set_page_size(struct spi_nor *nor)
>>         return 0;
>>  }
>>
>> +static int
>> +s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
>> +                       const struct sfdp_parameter_header *bfpt_header,
>> +                       const struct sfdp_bfpt *bfpt)
>> +{
>> +       /* Replace Quad Enable with volatile version */
>> +       nor->params->quad_enable = cypress_nor_quad_enable_volatile;
>> +
>> +       return cypress_nor_set_page_size(nor);
>> +}
>> +
>> +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
>> +{
>> +       struct spi_nor_erase_type *erase_type =
>> +                                       nor->params->erase_map.erase_type;
>> +       int i;
>> +
>> +       /*
>> +        * In some parts, 3byte erase opcodes are advertised by 4BAIT.
>> +        * Convert them to 4byte erase opcodes.
> 
> this is a fix, those opcodes don't work with 4 byte addresses, right?
Right. If we want to use 3byte opcodes with 4byte address, need to call
set_4byte_addr_mode().

> Looks good!
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> 
Thank you!


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