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From: <Tudor.Ambarus@microchip.com>
To: <tkuw584924@gmail.com>, <linux-mtd@lists.infradead.org>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
	<p.yadav@ti.com>, <Bacem.Daassi@infineon.com>,
	<Takahiro.Kuwano@infineon.com>
Subject: Re: [PATCH v4 6/6] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups
Date: Fri, 9 Apr 2021 02:37:45 +0000	[thread overview]
Message-ID: <e9d997a1-6d81-bccb-9e40-8030022cb7aa@microchip.com> (raw)
In-Reply-To: <a5ecdaac-3375-a898-59a1-646da26b5afb@gmail.com>

Hi,

On 4/9/21 5:05 AM, Takahiro Kuwano wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 4/8/2021 7:03 PM, Tudor.Ambarus@microchip.com wrote:
>> On 4/8/21 11:21 AM, Takahiro Kuwano wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Hi Tudor,
>>>
>>> On 4/8/2021 2:06 PM, Tudor.Ambarus@microchip.com wrote:
>>>> Hi,
>>>>
>>>> On 3/19/21 8:58 AM, tkuw584924@gmail.com wrote:
>>>>> +static int
>>>>> +s25hx_t_post_bfpt_fixups(struct spi_nor *nor,
>>>>> +                        const struct sfdp_parameter_header *bfpt_header,
>>>>> +                        const struct sfdp_bfpt *bfpt,
>>>>> +                        struct spi_nor_flash_parameter *params)
>>>>> +{
>>>>> +       int ret;
>>>>> +       u32 addr;
>>>>> +       u8 cfr3v;
>>>>> +
>>>>> +       ret = spi_nor_set_4byte_addr_mode(nor, true);
>>>>> +       if (ret)
>>>>> +               return ret;
>>>>> +       nor->addr_width = 4;
>>>>
>>>> Takahiro, you are bypassing the core functions. spansion_set_4byte_addr_mode()
>>>> will be called at set_4byte_addr_mode() time, resulting in an illegal op?
>>>>
>>> Since the spansion_post_sfdp_fixups() adds the SNOR_F_4B_OPCODES flag,
>>> spansion_set_4byte_addr_mode() is not called actually.
>>
>> right. Do we have to undo this somewhere, i.e, call
>> spi_nor_set_4byte_addr_mode(nor, false); ?
>>
> No. The Read/Write Any Register commands take 3 or 4 byte address depending
> on the Flash's current addr mode. Since the spansion_read/write_any_reg()
> use nor->addr_width which is always 4, the Flash's addr mode must always be
> in 4 byte mode.

If you reboot your board via cmdline, and the flash doesn't have a reset opcode,
the flash will remain in 4 byte mode when the driver loads again. Wouldn't that
affect the read sfdp command, since it is sent in 3 byte mode? Can you try a
"reboot" cmd and check what happens?

Cheers,
ta
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  reply	other threads:[~2021-04-09  2:38 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-19  6:51 [PATCH v4 0/6] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t tkuw584924
2021-03-19  6:53 ` [PATCH v4 1/6] mtd: spi-nor: core: Add the ->ready() hook tkuw584924
2021-03-19  6:54 ` [PATCH v4 2/6] mtd: spi-nor: core: Expose spi_nor_clear_sr() to manufacturer drivers tkuw584924
2021-03-19  6:56 ` [PATCH v4 3/6] mtd: spi-nor: spansion: Add support for Read/Write Any Register tkuw584924
2021-03-22  9:36   ` Pratyush Yadav
2021-04-20  5:48   ` Takahiro Kuwano
2021-03-19  6:57 ` [PATCH v4 4/6] mtd: spi-nor: spansion: Add support for volatile QE bit tkuw584924
2021-03-19  6:58 ` [PATCH v4 5/6] mtd: spi-nor: spansion: Add status check for multi-die parts tkuw584924
2021-03-19  6:58 ` [PATCH v4 6/6] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups tkuw584924
2021-04-08  5:06   ` Tudor.Ambarus
2021-04-08  8:21     ` Takahiro Kuwano
2021-04-08 10:03       ` Tudor.Ambarus
2021-04-09  2:05         ` Takahiro Kuwano
2021-04-09  2:37           ` Tudor.Ambarus [this message]
2021-04-09  3:24             ` Takahiro Kuwano
2021-04-01  6:09 ` [PATCH v4 0/6] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t Tudor.Ambarus
2021-04-02  7:13   ` Takahiro Kuwano
2021-04-08  5:35     ` Tudor.Ambarus
2021-04-09  8:50       ` Takahiro Kuwano

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