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[111.98.84.235]) by smtp.gmail.com with ESMTPSA id o27sm13638064pgb.70.2021.06.01.01.09.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jun 2021 01:09:48 -0700 (PDT) Subject: Re: [PATCH v5 6/6] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups To: Vignesh Raghavendra , linux-mtd@lists.infradead.org Cc: tudor.ambarus@microchip.com, miquel.raynal@bootlin.com, richard@nod.at, p.yadav@ti.com, Bacem.Daassi@infineon.com, Takahiro Kuwano References: <28d1a4015f37156a8bebe88959ea643e64b030f8.1619504535.git.Takahiro.Kuwano@infineon.com> <6b329250-93f4-bbbe-048f-696de9436342@ti.com> From: Takahiro Kuwano Message-ID: Date: Tue, 1 Jun 2021 17:09:37 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <6b329250-93f4-bbbe-048f-696de9436342@ti.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210601_010950_470547_92D63873 X-CRM114-Status: GOOD ( 28.26 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi Vignesh, On 5/27/2021 10:20 PM, Vignesh Raghavendra wrote: > > > On 4/27/21 12:39 PM, tkuw584924@gmail.com wrote: >> From: Takahiro Kuwano >> >> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. >> >> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and >> uniform sector sizes are supported. For the multi-die package parts (2Gb), >> only uniform sector sizes is supprted. This is due to missing or incorrect >> entries in SMPT. Fixup for other sector sizes configurations will be >> followed up as needed. >> >> Tested on Xilinx Zynq-7000 FPGA board. >> >> Signed-off-by: Takahiro Kuwano >> Reviewed-by: Pratyush Yadav >> --- >> Changes in v5: >> - Add NO_CHIP_ERASE flag to S25HL02GT and S25HS02GT >> >> Changes in v4: >> - Merge block comments about SMPT in s25hx_t_post_sfdp_fixups() >> - Remove USE_CLSR flags from S25HL02GT and S25HS02GT >> >> Changes in v3: >> - Remove S25HL256T and S25HS256T >> - Add S25HL02GT and S25HS02GT >> - Add support for multi-die package parts support >> - Remove erase_map fix for top/split sector layout >> - Set ECC data unit size (16B) to writesize >> >> drivers/mtd/spi-nor/spansion.c | 117 +++++++++++++++++++++++++++++++++ >> 1 file changed, 117 insertions(+) >> >> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c >> index 79d3249ed0aa..b3b006874b4f 100644 >> --- a/drivers/mtd/spi-nor/spansion.c >> +++ b/drivers/mtd/spi-nor/spansion.c >> @@ -229,6 +229,103 @@ static int spansion_mdp_ready(struct spi_nor *nor, u8 reg_dummy, u32 die_size) >> return 1; >> } >> >> +static int s25hx_t_quad_enable(struct spi_nor *nor) >> +{ >> + return spansion_quad_enable_volatile(nor, 0, SZ_128M); > > Number of dies should be part of struct flash_info > Die size can then be derived from total_size / die_num > > >> +} >> + >> +static int s25hx_t_mdp_ready(struct spi_nor *nor) >> +{ >> + return spansion_mdp_ready(nor, 0, SZ_128M); > > Hmm, is it necessary to poll second die if writes/erases were targeted > to first die only? > > Please split multi die support into a separate series. SPI NOR core > should be aware of multiple dies and thus call poll on each of the dies > separately. > > This will also allow base S25hx support to be accepted faster. > OK, I will do it. >> +} >> + >> +static int >> +s25hx_t_post_bfpt_fixups(struct spi_nor *nor, >> + const struct sfdp_parameter_header *bfpt_header, >> + const struct sfdp_bfpt *bfpt, >> + struct spi_nor_flash_parameter *params) >> +{ >> + int ret; >> + u32 addr; >> + u8 cfr3v; >> + >> + ret = spi_nor_set_4byte_addr_mode(nor, true); >> + if (ret) >> + return ret; >> + nor->addr_width = 4; > > Don't we need to check if flash size is actual >16M before enabling 4 > byte addressing? > S25HL/HS-T family has >16M devices only so we don't have to check it. >> + >> + /* Replace Quad Enable with volatile version */ >> + params->quad_enable = s25hx_t_quad_enable; >> + >> + /* >> + * The page_size is set to 512B from BFPT, but it actually depends on >> + * the configuration register. Look up the CFR3V and determine the >> + * page_size. For multi-die package parts, use 512B only when the all >> + * dies are configured to 512B buffer. >> + */ >> + for (addr = 0; addr < params->size; addr += SZ_128M) { >> + ret = spansion_read_any_reg(nor, >> + addr + SPINOR_REG_CYPRESS_CFR3V, 0, >> + &cfr3v); >> + if (ret) >> + return ret; >> + >> + if (!(cfr3v & SPINOR_REG_CYPRESS_CFR3V_PGSZ)) { >> + params->page_size = 256; >> + return 0; >> + } >> + } >> + params->page_size = 512; >> + >> + return 0; >> +} >> + > Regards > Vignesh > ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/