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Thu, 12 Nov 2026 03:25:18 +0100 Received: from MUCSE815.infineon.com ([fe80::b54c:c0bd:546c:c9be]) by MUCSE815.infineon.com ([fe80::b54c:c0bd:546c:c9be%12]) with mapi id 15.02.2562.056; Thu, 12 Nov 2026 03:25:18 +0100 From: To: , , CC: , , , , Subject: RE: [PATCH v4] mtd: spi-nor: micron-st: Add support for is25wx01g Thread-Topic: [PATCH v4] mtd: spi-nor: micron-st: Add support for is25wx01g Thread-Index: AQHdbgxT16z/LCoqo0ucH5OFl4R/+7cpmcow Date: Thu, 12 Nov 2026 02:25:18 +0000 Message-ID: References: <20261106-mtd-spi-nor-new-issi-chip-v4-1-7e2b6a361fe0@analog.com> In-Reply-To: <20261106-mtd-spi-nor-new-issi-chip-v4-1-7e2b6a361fe0@analog.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: X-Archived-By: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261111_182622_131560_38B1D116 X-CRM114-Status: GOOD ( 16.09 ) X-Spam-Score: -4.4 (----) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" X-Spam-Status: No, score=-3.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi, > Add support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal NOR flash. > The part is fully described by SFDP, so only the flash ID and small > post_bfpt and post_sfdp fixups are needed. > > WRITE STATUS REGISTER (01h) takes a single data byte and only affects > status register bits 7:2, so the default 16-bit Write Status assumption > does not hold. Clear write_sr1_and_sr2 so that the single byte write_sr1 > path is taken; write_sr1 is already set to 01h by the BFPT parsing. > > The flash also has no Status Register 2. Configuration registers are read > with B5h/85h and written with B1h/81h, and the 35h Read Configuration > Register command does not exist, so clear read_sr2 as well. > > Software write protection is done through the block protect bits in the > status register: BP0-BP2 at bits 4:2, BP3 at bit 6 and a Top/Bottom bit at > bit 5, which is exactly what SPI_NOR_HAS_LOCK, SPI_NOR_4BIT_BP, > SPI_NOR_BP3_SR_BIT6 and SPI_NOR_HAS_TB describe, so set those flags to get > the generic locking support. > > The flash also supports 8D-8D-8D, but this could not be tested. Since the > SFDP has no SCCR map, the core would select 8D-8D-8D on a capable > controller but never switch the flash into it. Hence, drop the 8D-8D-8D > capabilities in a post_sfdp fixup for now. > To fix missing SCCR map, .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE is needed. Could you check if it works? Thanks, Takahiro ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/