From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADB66C433EF for ; Mon, 21 Mar 2022 23:13:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:Cc:To:From :Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZwNBkrPVt0x1ulxmVd78PFERgnU8xV00faZJdMKnR8w=; b=u+xW6G2RzaxAahaWlCEY5NhWEc pZF2BBYpQxjEOeNUG1HhzKXz/zHQOdRIypUF0228wJqb3wGmOFdYTcT6IKXrxqdeGsh6xsssyjr85 2mZKtx0DL/GQYLbrGnYCw16SuDU21DNk0ZomdBjFUppGktk0ooqSp9wZlErxv7gdt5jyg5CViSLxx HH99BgL7RpdJg8cTro+Czoq0Lri9keDYEmH5hovBMk6vn4HxmOGbgrYgieXPFYBh8kCSkAqgvBVlH Lq6chtQ++mDc1AMcuiTQknC55xZ9FH6KrDRgh/ijImGvJDRc8dEGPjFKSse0bPReJGEZgyOEOOBj5 LEzrYYYA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nWRDA-009NQm-62; Mon, 21 Mar 2022 23:13:16 +0000 Received: from ssl.serverraum.org ([176.9.125.105]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nWRD7-009NPq-2m for linux-mtd@lists.infradead.org; Mon, 21 Mar 2022 23:13:14 +0000 Received: from ssl.serverraum.org (web.serverraum.org [172.16.0.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id E8E4C22175; Tue, 22 Mar 2022 00:13:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647904391; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d0xza72s8F6FNg0Fbb13ObxsvTsGPI8FF+13zzU0Pw8=; b=nfMtUOaRQPS1Ku1VXu9uHdN9PTrsF1hUFzWgRmsANEgXjQid3k3utpd0swizN13G1V6PGS 2oaq9WN2xDhCspOwbkBP6KRpL8kSeOtFfR5FXByNiJl7Hy5QKzWsjbEErEA47eo8TqCO5Z v2Sw+iH/lL/i3hO4Q5HhVfAq/VXWo0U= MIME-Version: 1.0 Date: Tue, 22 Mar 2022 00:13:10 +0100 From: Michael Walle To: Tudor Ambarus Cc: p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, nicolas.ferre@microchip.com, Takahiro Kuwano Subject: Re: [PATCH v2 6/8] mtd: spi-nor: core: Add helpers to read/write any register In-Reply-To: <20220228111712.111737-7-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> <20220228111712.111737-7-tudor.ambarus@microchip.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: X-Sender: michael@walle.cc X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220321_161313_311738_7494C3BA X-CRM114-Status: GOOD ( 21.47 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Am 2022-02-28 12:17, schrieb Tudor Ambarus: > There are manufacturers that use registers indexed by address. Some of > them support "read/write any register" opcodes. Provide core methods > that > can be used by all manufacturers. SPI NOR controller ops are > intentionally > not supported as we intend to move all the SPI NOR controller drivers > under the SPI subsystem. > > Signed-off-by: Tudor Ambarus > Tested-by: Takahiro Kuwano > Reviewed-by: Pratyush Yadav > --- > drivers/mtd/spi-nor/core.c | 41 ++++++++++++++++++++++++++++++++++++++ > drivers/mtd/spi-nor/core.h | 4 ++++ > 2 files changed, 45 insertions(+) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 281e3d25f74c..f1aa1e2ea7c9 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -307,6 +307,47 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, > loff_t to, size_t len, > return nor->controller_ops->write(nor, to, len, buf); > } > > +/** > + * spi_nor_read_reg() - read register to flash memory > + * @nor: pointer to 'struct spi_nor'. > + * @op: SPI memory operation. op->data.buf must be DMA-able. > + * @proto: SPI protocol to use for the register operation. > + * > + * Return: zero on success, -errno otherwise > + */ > +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto) > +{ > + if (!nor->spimem) > + return -EOPNOTSUPP; > + > + spi_nor_spimem_setup_op(nor, op, proto); > + return spi_nor_spimem_exec_op(nor, op); > +} > + > +/** > + * spi_nor_write_reg() - write register to flash memory > + * @nor: pointer to 'struct spi_nor' > + * @op: SPI memory operation. op->data.buf must be DMA-able. > + * @proto: SPI protocol to use for the register operation. > + * > + * Return: zero on success, -errno otherwise > + */ > +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto) > +{ > + int ret; > + > + if (!nor->spimem) > + return -EOPNOTSUPP; > + > + ret = spi_nor_write_enable(nor); > + if (ret) > + return ret; > + spi_nor_spimem_setup_op(nor, op, proto); > + return spi_nor_spimem_exec_op(nor, op); > +} > + > /** > * spi_nor_write_enable() - Set write enable latch with Write Enable > command. > * @nor: pointer to 'struct spi_nor'. > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index f952061d5c24..7c704475946d 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -554,6 +554,10 @@ ssize_t spi_nor_read_data(struct spi_nor *nor, > loff_t from, size_t len, > u8 *buf); > ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, > const u8 *buf); > +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto); > +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, > + enum spi_nor_protocol proto); These look rather odd. I'd expect to see an address and such for such a "random register read/write". Looks like these functions don't do much except calling spi_nor_spimem_setup_op() and exec_op() and don't have anything to do with register access (except maybe for the write enable). Can't we have a bit more sophisticated interface in the core? Something that calls into the flash driver to assemble the spi_mem_op automatically? Assuming that this will be used more often to access registers in a flash. -michael > int spi_nor_erase_sector(struct spi_nor *nor, u32 addr); > > int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t > len, u8 *buf); ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/