From: Michael Walle <michael@walle.cc>
To: Pratyush Yadav <pratyush@kernel.org>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>,
Jaime Liao <jaimeliao.tw@gmail.com>,
linux-mtd@lists.infradead.org, pratyush@kernel.org,
miquel.raynal@bootlin.com, leoyu@mxic.com.tw,
jaimeliao@mxic.com.tw
Subject: Re: [PATCH v4 1/6] mtd: spi-nor: Add manufacturer read id function
Date: Thu, 05 Oct 2023 13:43:05 +0200 [thread overview]
Message-ID: <f60995d3d02d7639204c2c16abf9bfd7@walle.cc> (raw)
In-Reply-To: <mafs034yppc28.fsf@kernel.org>
Hi,
>> I see this flash supports 1-1-1, 8-8-8, and 8d-8d-8d, there are no
>> mixed
>> modes supported, thus a 8d-8d-8s mode seems just like a hardware bug
>> to
>> me. So my proposal is to leave the core away and to handle the read id
>> hack just in the macronix driver.
>
> +1
I've looked at the xspi spec. There is no RDID specified. So I'd argue,
the only pseudo standard is that RDID was only ever used with 1s1s1s.
But
we added spi_nor_read_id() with parameters suited for the "unusual"
8d8d8d
case with additional address and dummy cycles. Just for checking whether
the
octal-dtr switch was successful. Therefore, we've already added
parameters to
spi_nor_read_id() which are not standard. Then we can just add one more.
It's
just how macronix is doing it. Again there is no standard.
If we'd only put standard (or for the 9F pseudo standard) things in the
core,
then spi_nor_read_id() would need to check whether the flash is in
1s1s1s
mode. And no I wouldn't prefer that ;)
-michael
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next prev parent reply other threads:[~2023-10-05 11:43 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 6:42 [PATCH v4 0/6] Add octal DTR support for Macronix flash Jaime Liao
2023-09-08 6:42 ` [PATCH v4 1/6] mtd: spi-nor: Add manufacturer read id function Jaime Liao
2023-09-20 12:28 ` Tudor Ambarus
2023-10-05 11:02 ` Pratyush Yadav
2023-10-05 11:43 ` Michael Walle [this message]
[not found] ` <54e5662f-baf4-4660-9fc4-7959d2405120@linaro.org>
[not found] ` <29bb3d952b9f49961da5e01cf86f9c4f@walle.cc>
2023-10-05 14:11 ` Tudor Ambarus
2023-10-06 8:22 ` Michael Walle
2023-10-12 8:59 ` liao jaime
2023-10-12 9:09 ` Michael Walle
2023-10-12 9:50 ` liao jaime
2023-10-13 8:06 ` Michael Walle
2023-10-13 8:23 ` liao jaime
2023-10-13 9:04 ` Michael Walle
2023-10-13 9:14 ` liao jaime
2023-10-13 9:32 ` Michael Walle
2023-10-17 10:12 ` Pratyush Yadav
2023-09-08 6:43 ` [PATCH v4 2/6] mtd: spi-nor: add Octal DTR support for Macronix flash Jaime Liao
2023-09-20 12:37 ` Tudor Ambarus
2023-10-05 10:18 ` Pratyush Yadav
2023-09-08 6:43 ` [PATCH v4 3/6] mtd: spi-nor: add support for Macronix Octal flash Jaime Liao
2023-09-20 12:41 ` Tudor Ambarus
2023-10-12 9:10 ` liao jaime
2023-09-08 6:43 ` [PATCH v4 4/6] spi: spi-mem: Allow specifying the byte order in DTR mode Jaime Liao
2023-09-20 12:47 ` Tudor Ambarus
2023-09-08 6:43 ` [PATCH v4 5/6] mtd: spi-nor: core: " Jaime Liao
2023-09-20 12:51 ` Tudor Ambarus
2023-09-08 6:43 ` [PATCH v4 6/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Jaime Liao
2023-09-20 12:52 ` Tudor Ambarus
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