From: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
To: linux-mtd@lists.infradead.org,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] mtd: spi-nor: macronix: Add support for mx66l2g45g
Date: Mon, 23 May 2022 22:33:31 +0800 [thread overview]
Message-ID: <fde9bd5a-7161-9222-4719-4279b2416163@linux.intel.com> (raw)
In-Reply-To: <20220523143002.1754922-1-jiaqing.zhao@linux.intel.com>
Use PARSE_SFDP for now as the SNOR_ID3() patch is not merged yet, will
switch to it after it is merged.
On 2022-05-23 22:30, Jiaqing Zhao wrote:
> Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
> x1, x2, and x4 operation modes.
>
> Tested read/write/erase with Aspeed AST2600 BMC SoC operating in x2
> mode at 50MHz, using Aspeed spi-mem driver.
>
> Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
> ---
> drivers/mtd/spi-nor/macronix.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index d81a4cb2812b..fd24ce9f02e2 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -95,6 +95,8 @@ static const struct flash_info macronix_nor_parts[] = {
> { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048)
> NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ) },
> + { "mx66l2g45g", INFO(0xc2201c, 0, 64 * 1024, 4096)
> + PARSE_SFDP },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048)
> NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
> { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096)
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next prev parent reply other threads:[~2022-05-23 14:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 14:30 [PATCH v2] mtd: spi-nor: macronix: Add support for mx66l2g45g Jiaqing Zhao
2022-05-23 14:33 ` Jiaqing Zhao [this message]
2022-05-23 14:59 ` Michael Walle
2022-05-23 15:03 ` Jiaqing Zhao
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