Re: [PATCH v2 3/3] riscv: dts: sophgo: Add SPI NOR node for SG2042

Chen Wang
2025-05-26T02:15:41Z

On 2025/5/25 22:58, Zixian Zeng wrote:
> Add SPI-NOR controller and flash nodes to device tree for SG2042.
>
> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
> .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 18 ++++++++++++++++
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 ++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> index 34645a5f6038389cd00d4940947c6bb71d39ec6f..c59a819e35d3201c484bf98392aec14392a7eb04 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> @@ -68,6 +68,24 @@ &sd {
> status = "okay";
> };
>
> +&spifmc0 {
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + };
> +};
> +
> +&spifmc1 {
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + };
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 212a3edc73fd654de59e10fab2094af2fec7f88f..06b433d5949bcc2374ea90223ff2d81434fad2b5 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -83,6 +83,30 @@ soc: soc {
> interrupt-parent = <&intc>;
> ranges;
>
> + spifmc0: spi@7000180000 {
> + compatible = "sophgo,sg2042-spifmc-nor", "sophgo,sg2044-spifmc-nor";
> + reg = <0x70 0x00180000 0x0 0x1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&clkgen GATE_CLK_AHB_SF>;
> + interrupt-parent = <&intc>;
"interrupt-parent" is not needed, because it has been defined in soc level.
> + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rstgen RST_SF0>;
> + status = "disabled";
> + };
> +
> + spifmc1: spi@7002180000 {
> + compatible = "sophgo,sg2042-spifmc-nor", "sophgo,sg2044-spifmc-nor";
> + reg = <0x70 0x02180000 0x0 0x1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&clkgen GATE_CLK_AHB_SF>;
> + interrupt-parent = <&intc>;
The same question listed upon.
> + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rstgen RST_SF1>;
> + status = "disabled";
> + };
> +
> i2c0: i2c@7030005000 {
> compatible = "snps,designware-i2c";
> reg = <0x70 0x30005000 0x0 0x1000>;

Othres LGTM.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>