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From: "Gerhard TAEUBL" <Gerhard.TAEUBL@frequentis.com>
To: <linux-mtd@lists.infradead.org>
Subject: Intel 28F320 Flash
Date: Fri, 11 Apr 2003 13:39:06 +0200	[thread overview]
Message-ID: <se96c581.053@mail.frequentis.com> (raw)

Hi to all!

In our company we use the 28F320 3V3 flashes. The WP ist connected to low, RP is high. So it isn't possible to lock or unlock any block. Also after production we test the wholeflash (only word write, not buffer write).

So far so good.

On some hardware (1 -3%) it isn't possible to use the jffs2 filesystem. If we copy files the copy comand will be aborted. After searching in the code and do some additional output, I see, that one flash (we have two in parallel manner for 32 bit access) has set SR.1 bit after the buffer write command. 

Hum, only one of both... and all pins a right connected.
So I write an own test program for flash and buffer write => everything seems to be OK! The only difference is, that I check the whole status word if it is correct not like in the cfi_cmdset program to mask only the OK bit.

If I comment this & code (if ((status /*& status_OK*/) == status_OK)) then everything works fine.

Is this a sw bug or the 28F320 chip has a defect?

Thanks for any hint

best regards
Gerhard

P.S. I'm not member of this mailing list, so address me direct!

                 reply	other threads:[~2003-04-11 11:39 UTC|newest]

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