From: Peter Zijlstra <peterz@infradead.org>
To: Stafford Horne <shorne@gmail.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>,
Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
"H. Peter Anvin" <hpa@zytor.com>,
linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
Frederic Weisbecker <fweisbec@gmail.com>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Subject: Re: linux-next: manual merge of the tip tree with the openrisc tree
Date: Mon, 20 Feb 2017 12:28:44 +0100 [thread overview]
Message-ID: <20170220112844.GN6536@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20170220111805.GP6500@twins.programming.kicks-ass.net>
On Mon, Feb 20, 2017 at 12:18:05PM +0100, Peter Zijlstra wrote:
> On Sun, Feb 19, 2017 at 04:26:54PM +0900, Stafford Horne wrote:
> > On Fri, Feb 17, 2017 at 12:43:21PM +1100, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > Today's linux-next merge of the tip tree got a conflict in:
> > >
> > > arch/openrisc/include/asm/Kbuild
> > >
> > > between commit:
> > >
> > > 157e82f58007 ("openrisc: add cmpxchg and xchg implementations")
>
> *groan* branch delay slots...
>
>
> It it typically recommended to implement 1 and 2 byte versions as well.
> If the architecture doesn't support these natively, you can easily
> implement them with the 4 byte ll/sc and simply retain the other bits.
While there; I spotted commit 8ffa662370f0 ("openrisc: add optimized
atomic operations") which doesn't make any kind of sense to me.
Have you actually read the asm-generic/atomic.h file you're including?
next prev parent reply other threads:[~2017-02-20 11:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-17 1:43 linux-next: manual merge of the tip tree with the openrisc tree Stephen Rothwell
2017-02-19 7:26 ` Stafford Horne
2017-02-20 11:18 ` Peter Zijlstra
2017-02-20 11:28 ` Peter Zijlstra [this message]
2017-02-20 14:53 ` Stafford Horne
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