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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id q1sm12151983pgr.92.2019.11.04.09.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 09:40:39 -0800 (PST) From: coverity-bot X-Google-Original-From: coverity-bot Date: Mon, 4 Nov 2019 09:40:38 -0800 To: Jun Lei Cc: Leo Li , Alex Deucher , Tony Cheng , "Gustavo A. R. Silva" , linux-next@vger.kernel.org Subject: Coverity: dcn20_update_bounding_box(): UNINTENDED_INTEGER_DIVISION Message-ID: <201911040940.91FAE4C@keescook> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Sender: linux-next-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-next@vger.kernel.org Hello! This is an experimental automated report about issues detected by Coverity from a scan of next-20191031 as part of the linux-next weekly scan project: https://scan.coverity.com/projects/linux-next-weekly-scan You're getting this email because you were associated with the identified lines of code (noted below) that were touched by recent commits: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Coverity reported the following: *** CID 1487397: (UNINTENDED_INTEGER_DIVISION) /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3142 in dcn20_update_bounding_box() 3136 // FCLK:UCLK ratio is 1.08 3137 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); 3138 3139 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3140 min_dcfclk : min_fclk_required_by_uclk; 3141 vvv CID 1487397: (UNINTENDED_INTEGER_DIVISION) vvv Dividing integer expressions "max_clocks->socClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored. 3142 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3143 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3144 3145 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3146 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3147 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3145 in dcn20_update_bounding_box() 3139 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? 3140 min_dcfclk : min_fclk_required_by_uclk; 3141 3142 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? 3143 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3144 vvv CID 1487397: (UNINTENDED_INTEGER_DIVISION) vvv Dividing integer expressions "max_clocks->dcfClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored. 3145 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? 3146 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; 3147 3148 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; 3149 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; 3150 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); If this is a false positive, please let us know so we can mark it as such, or teach the Coverity rules to be smarter. If not, please make sure fixes get into linux-next. :) For patches fixing this, please include these lines (but double-check the "Fixes" first): Reported-by: coverity-bot Addresses-Coverity-ID: 1487397 ("UNINTENDED_INTEGER_DIVISION") Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Thanks for your attention! -- Coverity-bot