linux-next: manual merge of the tip tree with the perf tree

linux-next: manual merge of the tip tree with the perf tree

[Stephen Rothwell]

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Hi all,

Today's linux-next merge of the tip tree got conflicts in:

  tools/perf/arch/x86/include/arch-tests.h
  tools/perf/arch/x86/tests/arch-tests.c

between commit:

  ae4aa00a1a93 ("perf test: Move x86 hybrid tests to arch/x86")

from the perf tree and commit:

  78075d947534 ("perf test: Add selftest to test IBS invocation via core pmu events")

from the tip tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc tools/perf/arch/x86/include/arch-tests.h
index 33d39c1d3e64,93d3b8877baa..000000000000
--- a/tools/perf/arch/x86/include/arch-tests.h
+++ b/tools/perf/arch/x86/include/arch-tests.h
@@@ -11,7 -11,7 +11,8 @@@ int test__intel_pt_pkt_decoder(struct t
  int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest);
  int test__bp_modify(struct test_suite *test, int subtest);
  int test__x86_sample_parsing(struct test_suite *test, int subtest);
 +int test__hybrid(struct test_suite *test, int subtest);
+ int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest);
  
  extern struct test_suite *arch_tests[];
  
diff --cc tools/perf/arch/x86/tests/arch-tests.c
index 147ad0638bbb,b5c85ab8d92e..000000000000
--- a/tools/perf/arch/x86/tests/arch-tests.c
+++ b/tools/perf/arch/x86/tests/arch-tests.c
@@@ -22,15 -22,7 +22,16 @@@ struct test_suite suite__intel_pt = 
  DEFINE_SUITE("x86 bp modify", bp_modify);
  #endif
  DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing);
 +static struct test_case hybrid_tests[] = {
 +	TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"),
 +	{ .name = NULL, }
 +};
 +
 +struct test_suite suite__hybrid = {
 +	.desc = "x86 hybrid",
 +	.test_cases = hybrid_tests,
 +};
+ DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu);
  
  struct test_suite *arch_tests[] = {
  #ifdef HAVE_DWARF_UNWIND_SUPPORT
@@@ -44,6 -36,6 +45,7 @@@
  	&suite__bp_modify,
  #endif
  	&suite__x86_sample_parsing,
 +	&suite__hybrid,
+ 	&suite__amd_ibs_via_core_pmu,
  	NULL,
  };

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Re: linux-next: manual merge of the tip tree with the perf tree

[Stephen Rothwell]

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Hi all,

On Tue, 16 May 2023 10:34:13 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> 
> Today's linux-next merge of the tip tree got conflicts in:
> 
>   tools/perf/arch/x86/include/arch-tests.h
>   tools/perf/arch/x86/tests/arch-tests.c
> 
> between commit:
> 
>   ae4aa00a1a93 ("perf test: Move x86 hybrid tests to arch/x86")
> 
> from the perf tree and commit:
> 
>   78075d947534 ("perf test: Add selftest to test IBS invocation via core pmu events")
> 
> from the tip tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> -- 
> Cheers,
> Stephen Rothwell
> 
> diff --cc tools/perf/arch/x86/include/arch-tests.h
> index 33d39c1d3e64,93d3b8877baa..000000000000
> --- a/tools/perf/arch/x86/include/arch-tests.h
> +++ b/tools/perf/arch/x86/include/arch-tests.h
> @@@ -11,7 -11,7 +11,8 @@@ int test__intel_pt_pkt_decoder(struct t
>   int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest);
>   int test__bp_modify(struct test_suite *test, int subtest);
>   int test__x86_sample_parsing(struct test_suite *test, int subtest);
>  +int test__hybrid(struct test_suite *test, int subtest);
> + int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest);
>   
>   extern struct test_suite *arch_tests[];
>   
> diff --cc tools/perf/arch/x86/tests/arch-tests.c
> index 147ad0638bbb,b5c85ab8d92e..000000000000
> --- a/tools/perf/arch/x86/tests/arch-tests.c
> +++ b/tools/perf/arch/x86/tests/arch-tests.c
> @@@ -22,15 -22,7 +22,16 @@@ struct test_suite suite__intel_pt = 
>   DEFINE_SUITE("x86 bp modify", bp_modify);
>   #endif
>   DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing);
>  +static struct test_case hybrid_tests[] = {
>  +	TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"),
>  +	{ .name = NULL, }
>  +};
>  +
>  +struct test_suite suite__hybrid = {
>  +	.desc = "x86 hybrid",
>  +	.test_cases = hybrid_tests,
>  +};
> + DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu);
>   
>   struct test_suite *arch_tests[] = {
>   #ifdef HAVE_DWARF_UNWIND_SUPPORT
> @@@ -44,6 -36,6 +45,7 @@@
>   	&suite__bp_modify,
>   #endif
>   	&suite__x86_sample_parsing,
>  +	&suite__hybrid,
> + 	&suite__amd_ibs_via_core_pmu,
>   	NULL,
>   };

This is now a conflict between the perf tree and Linus' tree.

-- 
Cheers,
Stephen Rothwell

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Re: linux-next: manual merge of the tip tree with the perf tree

[Namhyung Kim]

Hello,

On Tue, Jun 27, 2023 at 6:37 PM Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> Hi all,
>
> On Tue, 16 May 2023 10:34:13 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> >
> > Today's linux-next merge of the tip tree got conflicts in:
> >
> >   tools/perf/arch/x86/include/arch-tests.h
> >   tools/perf/arch/x86/tests/arch-tests.c
> >
> > between commit:
> >
> >   ae4aa00a1a93 ("perf test: Move x86 hybrid tests to arch/x86")
> >
> > from the perf tree and commit:
> >
> >   78075d947534 ("perf test: Add selftest to test IBS invocation via core pmu events")
> >
> > from the tip tree.
> >
> > I fixed it up (see below) and can carry the fix as necessary. This
> > is now fixed as far as linux-next is concerned, but any non trivial
> > conflicts should be mentioned to your upstream maintainer when your tree
> > is submitted for merging.  You may also want to consider cooperating
> > with the maintainer of the conflicting tree to minimise any particularly
> > complex conflicts.

Thanks for the email and the resolution.  Looks ok to me.
I'll note this in my pull request.


> >
> > --
> > Cheers,
> > Stephen Rothwell
> >
> > diff --cc tools/perf/arch/x86/include/arch-tests.h
> > index 33d39c1d3e64,93d3b8877baa..000000000000
> > --- a/tools/perf/arch/x86/include/arch-tests.h
> > +++ b/tools/perf/arch/x86/include/arch-tests.h
> > @@@ -11,7 -11,7 +11,8 @@@ int test__intel_pt_pkt_decoder(struct t
> >   int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest);
> >   int test__bp_modify(struct test_suite *test, int subtest);
> >   int test__x86_sample_parsing(struct test_suite *test, int subtest);
> >  +int test__hybrid(struct test_suite *test, int subtest);
> > + int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest);
> >
> >   extern struct test_suite *arch_tests[];
> >
> > diff --cc tools/perf/arch/x86/tests/arch-tests.c
> > index 147ad0638bbb,b5c85ab8d92e..000000000000
> > --- a/tools/perf/arch/x86/tests/arch-tests.c
> > +++ b/tools/perf/arch/x86/tests/arch-tests.c
> > @@@ -22,15 -22,7 +22,16 @@@ struct test_suite suite__intel_pt =
> >   DEFINE_SUITE("x86 bp modify", bp_modify);
> >   #endif
> >   DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing);
> >  +static struct test_case hybrid_tests[] = {
> >  +    TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"),
> >  +    { .name = NULL, }
> >  +};
> >  +
> >  +struct test_suite suite__hybrid = {
> >  +    .desc = "x86 hybrid",
> >  +    .test_cases = hybrid_tests,
> >  +};
> > + DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu);
> >
> >   struct test_suite *arch_tests[] = {
> >   #ifdef HAVE_DWARF_UNWIND_SUPPORT
> > @@@ -44,6 -36,6 +45,7 @@@
> >       &suite__bp_modify,
> >   #endif
> >       &suite__x86_sample_parsing,
> >  +    &suite__hybrid,
> > +     &suite__amd_ibs_via_core_pmu,
> >       NULL,
> >   };
>
> This is now a conflict between the perf tree and Linus' tree.

Yep, thanks!

Namhyung

linux-next: manual merge of the tip tree with the perf tree

[Stephen Rothwell]

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Hi all,

Today's linux-next merge of the tip tree got a conflict in:

  tools/arch/x86/include/asm/cpufeatures.h

between commit:

  444f03645f14 ("tools headers x86 cpufeatures: Sync with the kernel sources to pick ZEN6 and Indirect Target Selection (ITS) bits")

from the perf tree and commits:

  282cc5b67623 ("x86/cpufeatures: Clean up formatting")
  13327fada7ff ("x86/cpufeatures: Shorten X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT")
  3aba0b40cacd ("x86/cpufeatures: Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES")

from the tip tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc tools/arch/x86/include/asm/cpufeatures.h
index 30144ef9ef02,bc81b9d1aeca..000000000000
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@@ -476,12 -476,11 +476,12 @@@
  #define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* Clear branch history at syscall entry using SW loop */
  #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
  #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
- #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
- #define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
- #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
- #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
- #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
- #define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32 + 9) /* Use thunk for indirect branches in lower half of cacheline */
+ #define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */
+ #define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
+ #define X86_FEATURE_AMD_HTR_CORES	(21*32+ 6) /* Heterogeneous Core Topology */
+ #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
+ #define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
++#define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32+ 9) /* Use thunk for indirect branches in lower half of cacheline */
  
  /*
   * BUG word(s)
@@@ -528,12 -527,10 +528,12 @@@
  #define X86_BUG_TDX_PW_MCE		X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does partial write to TDX private memory */
  
  /* BUG word 2 */
- #define X86_BUG_SRSO			X86_BUG(1*32 + 0) /* "srso" AMD SRSO bug */
- #define X86_BUG_DIV0			X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */
- #define X86_BUG_RFDS			X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
- #define X86_BUG_BHI			X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
- #define X86_BUG_IBPB_NO_RET	   	X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
- #define X86_BUG_SPECTRE_V2_USER		X86_BUG(1*32 + 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
- #define X86_BUG_ITS			X86_BUG(1*32 + 6) /* "its" CPU is affected by Indirect Target Selection */
- #define X86_BUG_ITS_NATIVE_ONLY		X86_BUG(1*32 + 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
+ #define X86_BUG_SRSO			X86_BUG( 1*32+ 0) /* "srso" AMD SRSO bug */
+ #define X86_BUG_DIV0			X86_BUG( 1*32+ 1) /* "div0" AMD DIV0 speculation bug */
+ #define X86_BUG_RFDS			X86_BUG( 1*32+ 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
+ #define X86_BUG_BHI			X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */
+ #define X86_BUG_IBPB_NO_RET		X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target predictions */
+ #define X86_BUG_SPECTRE_V2_USER		X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
++#define X86_BUG_ITS			X86_BUG( 1*32+ 6) /* "its" CPU is affected by Indirect Target Selection */
++#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
  #endif /* _ASM_X86_CPUFEATURES_H */

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Re: linux-next: manual merge of the tip tree with the perf tree

[Stephen Rothwell]

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Hi all,

On Mon, 26 May 2025 14:50:15 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> 
> Today's linux-next merge of the tip tree got a conflict in:
> 
>   tools/arch/x86/include/asm/cpufeatures.h
> 
> between commit:
> 
>   444f03645f14 ("tools headers x86 cpufeatures: Sync with the kernel sources to pick ZEN6 and Indirect Target Selection (ITS) bits")
> 
> from the perf tree and commits:
> 
>   282cc5b67623 ("x86/cpufeatures: Clean up formatting")
>   13327fada7ff ("x86/cpufeatures: Shorten X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT")
>   3aba0b40cacd ("x86/cpufeatures: Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES")
> 
> from the tip tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> 
> diff --cc tools/arch/x86/include/asm/cpufeatures.h
> index 30144ef9ef02,bc81b9d1aeca..000000000000
> --- a/tools/arch/x86/include/asm/cpufeatures.h
> +++ b/tools/arch/x86/include/asm/cpufeatures.h
> @@@ -476,12 -476,11 +476,12 @@@
>   #define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* Clear branch history at syscall entry using SW loop */
>   #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
>   #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
> - #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> - #define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
> - #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
> - #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
> - #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> - #define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32 + 9) /* Use thunk for indirect branches in lower half of cacheline */
> + #define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */
> + #define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
> + #define X86_FEATURE_AMD_HTR_CORES	(21*32+ 6) /* Heterogeneous Core Topology */
> + #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
> + #define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
> ++#define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32+ 9) /* Use thunk for indirect branches in lower half of cacheline */
>   
>   /*
>    * BUG word(s)
> @@@ -528,12 -527,10 +528,12 @@@
>   #define X86_BUG_TDX_PW_MCE		X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does partial write to TDX private memory */
>   
>   /* BUG word 2 */
> - #define X86_BUG_SRSO			X86_BUG(1*32 + 0) /* "srso" AMD SRSO bug */
> - #define X86_BUG_DIV0			X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */
> - #define X86_BUG_RFDS			X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
> - #define X86_BUG_BHI			X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
> - #define X86_BUG_IBPB_NO_RET	   	X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
> - #define X86_BUG_SPECTRE_V2_USER		X86_BUG(1*32 + 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
> - #define X86_BUG_ITS			X86_BUG(1*32 + 6) /* "its" CPU is affected by Indirect Target Selection */
> - #define X86_BUG_ITS_NATIVE_ONLY		X86_BUG(1*32 + 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
> + #define X86_BUG_SRSO			X86_BUG( 1*32+ 0) /* "srso" AMD SRSO bug */
> + #define X86_BUG_DIV0			X86_BUG( 1*32+ 1) /* "div0" AMD DIV0 speculation bug */
> + #define X86_BUG_RFDS			X86_BUG( 1*32+ 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
> + #define X86_BUG_BHI			X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */
> + #define X86_BUG_IBPB_NO_RET		X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target predictions */
> + #define X86_BUG_SPECTRE_V2_USER		X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
> ++#define X86_BUG_ITS			X86_BUG( 1*32+ 6) /* "its" CPU is affected by Indirect Target Selection */
> ++#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
>   #endif /* _ASM_X86_CPUFEATURES_H */

This is now a conflict between the perf tree and Linus' tree.

-- 
Cheers,
Stephen Rothwell

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Re: linux-next: manual merge of the tip tree with the perf tree

[Stephen Rothwell]

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Hi all,

On Wed, 28 May 2025 10:34:18 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> 
> On Mon, 26 May 2025 14:50:15 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> > 
> > Today's linux-next merge of the tip tree got a conflict in:
> > 
> >   tools/arch/x86/include/asm/cpufeatures.h
> > 
> > between commit:
> > 
> >   444f03645f14 ("tools headers x86 cpufeatures: Sync with the kernel sources to pick ZEN6 and Indirect Target Selection (ITS) bits")
> > 
> > from the perf tree and commits:
> > 
> >   282cc5b67623 ("x86/cpufeatures: Clean up formatting")
> >   13327fada7ff ("x86/cpufeatures: Shorten X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT")
> >   3aba0b40cacd ("x86/cpufeatures: Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES")
> > 
> > from the tip tree.
> > 
> > I fixed it up (see below) and can carry the fix as necessary. This
> > is now fixed as far as linux-next is concerned, but any non trivial
> > conflicts should be mentioned to your upstream maintainer when your tree
> > is submitted for merging.  You may also want to consider cooperating
> > with the maintainer of the conflicting tree to minimise any particularly
> > complex conflicts.
> > 
> > 
> > diff --cc tools/arch/x86/include/asm/cpufeatures.h
> > index 30144ef9ef02,bc81b9d1aeca..000000000000
> > --- a/tools/arch/x86/include/asm/cpufeatures.h
> > +++ b/tools/arch/x86/include/asm/cpufeatures.h
> > @@@ -476,12 -476,11 +476,12 @@@
> >   #define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* Clear branch history at syscall entry using SW loop */
> >   #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
> >   #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
> > - #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> > - #define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
> > - #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
> > - #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
> > - #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> > - #define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32 + 9) /* Use thunk for indirect branches in lower half of cacheline */
> > + #define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */
> > + #define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
> > + #define X86_FEATURE_AMD_HTR_CORES	(21*32+ 6) /* Heterogeneous Core Topology */
> > + #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
> > + #define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
> > ++#define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32+ 9) /* Use thunk for indirect branches in lower half of cacheline */
> >   
> >   /*
> >    * BUG word(s)
> > @@@ -528,12 -527,10 +528,12 @@@
> >   #define X86_BUG_TDX_PW_MCE		X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does partial write to TDX private memory */
> >   
> >   /* BUG word 2 */
> > - #define X86_BUG_SRSO			X86_BUG(1*32 + 0) /* "srso" AMD SRSO bug */
> > - #define X86_BUG_DIV0			X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */
> > - #define X86_BUG_RFDS			X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
> > - #define X86_BUG_BHI			X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
> > - #define X86_BUG_IBPB_NO_RET	   	X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
> > - #define X86_BUG_SPECTRE_V2_USER		X86_BUG(1*32 + 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
> > - #define X86_BUG_ITS			X86_BUG(1*32 + 6) /* "its" CPU is affected by Indirect Target Selection */
> > - #define X86_BUG_ITS_NATIVE_ONLY		X86_BUG(1*32 + 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
> > + #define X86_BUG_SRSO			X86_BUG( 1*32+ 0) /* "srso" AMD SRSO bug */
> > + #define X86_BUG_DIV0			X86_BUG( 1*32+ 1) /* "div0" AMD DIV0 speculation bug */
> > + #define X86_BUG_RFDS			X86_BUG( 1*32+ 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
> > + #define X86_BUG_BHI			X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */
> > + #define X86_BUG_IBPB_NO_RET		X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target predictions */
> > + #define X86_BUG_SPECTRE_V2_USER		X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
> > ++#define X86_BUG_ITS			X86_BUG( 1*32+ 6) /* "its" CPU is affected by Indirect Target Selection */
> > ++#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
> >   #endif /* _ASM_X86_CPUFEATURES_H */  
> 
> This is now a conflict between the perf tree and Linus' tree.

This is now a conflict between the perf-current tree and Linus' tree.

-- 
Cheers,
Stephen Rothwell

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