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Date: Mon, 19 Feb 2024 12:14:18 +0000
From: Catalin Marinas <catalin.marinas@arm.com>
To: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Christoffer Dall <cdall@cs.columbia.edu>, Marc Zyngier <maz@kernel.org>,
	Will Deacon <will@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux Next Mailing List <linux-next@vger.kernel.org>,
	Oliver Upton <oliver.upton@linux.dev>
Subject: Re: linux-next: manual merge of the kvm-arm tree with the arm64 tree
Message-ID: <ZdNGGrUDWfvqCudV@arm.com>
References: <20240219135805.1c4138a3@canb.auug.org.au>
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On Mon, Feb 19, 2024 at 01:58:05PM +1100, Stephen Rothwell wrote:
> diff --cc arch/arm64/kernel/cpufeature.c
> index 0be9296e9253,f309fd542c20..000000000000
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@@ -721,13 -754,12 +756,14 @@@ static const struct __ftr_reg_entry 
>   			       &id_aa64isar2_override),
>   
>   	/* Op1 = 0, CRn = 0, CRm = 7 */
>  -	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
>  +	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0,
>  +			       &id_aa64mmfr0_override),
>   	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
>   			       &id_aa64mmfr1_override),
>  -	ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
>  +	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2,
>  +			       &id_aa64mmfr2_override),
>   	ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
> + 	ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4),
>   
>   	/* Op1 = 1, CRn = 0, CRm = 0 */
>   	ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
> @@@ -2701,33 -2817,13 +2779,40 @@@ static const struct arm64_cpu_capabilit
>   		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
>   		.matches = has_lpa2,
>   	},
>  +#ifdef CONFIG_ARM64_VA_BITS_52
>  +	{
>  +		.capability = ARM64_HAS_VA52,
>  +		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
>  +		.matches = has_cpuid_feature,
>  +		.field_width = 4,
>  +#ifdef CONFIG_ARM64_64K_PAGES
>  +		.desc = "52-bit Virtual Addressing (LVA)",
>  +		.sign = FTR_SIGNED,
>  +		.sys_reg = SYS_ID_AA64MMFR2_EL1,
>  +		.field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT,
>  +		.min_field_value = ID_AA64MMFR2_EL1_VARange_52,
>  +#else
>  +		.desc = "52-bit Virtual Addressing (LPA2)",
>  +		.sys_reg = SYS_ID_AA64MMFR0_EL1,
>  +#ifdef CONFIG_ARM64_4K_PAGES
>  +		.sign = FTR_SIGNED,
>  +		.field_pos = ID_AA64MMFR0_EL1_TGRAN4_SHIFT,
>  +		.min_field_value = ID_AA64MMFR0_EL1_TGRAN4_52_BIT,
>  +#else
>  +		.sign = FTR_UNSIGNED,
>  +		.field_pos = ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
>  +		.min_field_value = ID_AA64MMFR0_EL1_TGRAN16_52_BIT,
>  +#endif
>  +#endif
>  +	},
>  +#endif
> + 	{
> + 		.desc = "NV1",
> + 		.capability = ARM64_HAS_HCR_NV1,
> + 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + 		.matches = has_nv1,
> + 		ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1)
> + 	},
>   	{},
>   };

Thanks Stephen. It looks fine.

-- 
Catalin