From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52D7821C9F1; Thu, 15 May 2025 16:01:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747324877; cv=none; b=BGnZQgeNRWaPjIIJ4Ir4JxxxWn0qJ4PF7TsyHGe+GFelcpd8FNzETE2nqG5Evz6KCxq8UkS+EGNXrT+Qnz4dA0EFSnX71m3+d/NwNlHpqYaSxFKPyBwNT6uKwC7a4fnMOZyXl7TwcANl0u6+HzazxTFVt7dfepKXY5fIRv5BxcU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747324877; c=relaxed/simple; bh=ATrywjxspmQpMwG9e61oi4DTZo/y4M+lVUmbwwGtxrU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jutnd5Y41iUtoMC9N/39ZUnQK+aew3dPEx/wPnFgFcbFN97VKsdptZq7ocLbjs6sCeVUy0J6PJ12KeZJDWrVY2Vqdu6mGuOb24JXhuVgjN/nyjks0cqnb5ha69BIuMjdbc3I//hMvtPBcrgTqSH6yLPTxaWFcLXmzEgz+panPtU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W8O7/rwf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W8O7/rwf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B919DC4CEEB; Thu, 15 May 2025 16:01:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747324876; bh=ATrywjxspmQpMwG9e61oi4DTZo/y4M+lVUmbwwGtxrU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=W8O7/rwfGZSlLBwQUFmu0Mt98qc7VIN9nNH+yhpEIjlsMMFqomqyMw4usn+NHVSY5 lbcXGC1aS49c9FCZnMLVK3wXvicXJB+y6KVPkrCdU30jWcNM+3QACPg7Cqqi0Yb1ax Lk0TvBst4Hda3I91XCLee35+MOlWJRyguICPMYoa8MxYMs9KbbKPYm7sLMmugld3+D uXPp6h1tAVmyfOLabExqN1T7zqx1hHrTpk02OJicVpqVh4N8XTJljejRsDT8LV/WwE 7kw00hgnC56cFFxN4Ki2T2xhviAzpAIVO1mCroMUCbTbkpHcgyJgB5Bqn/W31ZiH8o /EE2w35RilGqA== Date: Thu, 15 May 2025 18:01:12 +0200 From: Ingo Molnar To: Mario Limonciello Cc: Stephen Rothwell , Thomas Gleixner , "H. Peter Anvin" , Peter Zijlstra , "Rafael J. Wysocki" , Dhananjay Ugwekar , Linux Kernel Mailing List , Linux Next Mailing List Subject: [PATCH] x86/msr: Add rdmsrl_on_cpu() compatibility wrapper Message-ID: References: <20250512145517.6e0666e3@canb.auug.org.au> <20250512152326.3f2f0226@canb.auug.org.au> <8c4ab851-1853-442e-90a9-225be16c804c@amd.com> <46e04d1c-dbc8-4a45-95d4-fecfdd943065@amd.com> Precedence: bulk X-Mailing-List: linux-next@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <46e04d1c-dbc8-4a45-95d4-fecfdd943065@amd.com> * Mario Limonciello wrote: > > If it's only about rdmsrl_on_cpu(), how about the simple > > compatibility wrapper below instead, applied to the x86 tree? > > > > Can merge it into -tip and tomorrow's -next would resolve this > > without any changes or merges done to the PM tree. > > Sounds good to me. Great - I've added the patch below to the x86 tree, tomorrow's -next should have this resolved in theory. Thanks, Ingo =======================> From: Ingo Molnar Date: Thu, 15 May 2025 17:49:16 +0200 Subject: [PATCH] x86/msr: Add rdmsrl_on_cpu() compatibility wrapper Add a simple rdmsrl_on_cpu() compatibility wrapper for rdmsrq_on_cpu(), to make life in -next easier, where the PM tree recently grew more uses of the old API. Reported-by: Stephen Rothwell Signed-off-by: Ingo Molnar Acked-by: Mario Limonciello Cc: "H. Peter Anvin" Cc: Juergen Gross Cc: Dave Hansen Cc: Xin Li Link: https://lore.kernel.org/r/20250512145517.6e0666e3@canb.auug.org.au --- arch/x86/include/asm/msr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index a9ce56fc8785..4096b8af4ba7 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -329,6 +329,7 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) /* Compatibility wrappers: */ #define rdmsrl(msr, val) rdmsrq(msr, val) #define wrmsrl(msr, val) wrmsrq(msr, val) +#define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q) #endif /* __ASSEMBLER__ */ #endif /* _ASM_X86_MSR_H */