linux-next: manual merge of the drm tree with the drm-fixes tree

[Mark Brown <broonie@kernel.org>]

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Hi all,

Today's linux-next merge of the drm tree got a conflict in:

  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

between commit:

  cdbc3b62cfc278 ("drm/amd/pm: Skip redundant UCLK restore in smu_v13_0_6")

from the drm-fixes tree and commits:

  17f11bbbc76c8e ("drm/amd/pm: Skip redundant UCLK restore in smu_v13_0_6")
  5da89a8afca14a ("drm/amd/pm: Add custom fclk setting support")

from the drm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --combined drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 870bcc86fd7948,47554118978298..00000000000000
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@@ -373,6 -373,9 +373,9 @@@ static void smu_v13_0_12_init_caps(stru
  	} else {
  		smu_v13_0_12_tables_fini(smu);
  	}
+ 
+ 	if (fw_ver >= 0x04561000)
+ 		smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_AID_XCD_HBM));
  }
  
  static void smu_v13_0_6_init_caps(struct smu_context *smu)
@@@ -458,6 -461,7 +461,7 @@@
  		smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
  
  	if ((pgm == 0 && fw_ver >= 0x00558200) ||
+ 	    (pgm == 4 && fw_ver >= 0x04557100) ||
  	    (pgm == 7 && fw_ver >= 0x07551400))
  		smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
  }
@@@ -478,7 -482,7 +482,7 @@@ static int smu_v13_0_6_check_fw_version
  {
  	int r;
  
- 	r = smu_v13_0_check_fw_version(smu);
+ 	r = smu_cmn_check_fw_version(smu);
  	/* Initialize caps flags once fw version is fetched */
  	if (!r)
  		smu_v13_0_x_init_caps(smu);
@@@ -1196,6 -1200,7 +1200,7 @@@ static int smu_v13_0_6_populate_umd_sta
  	struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
  	struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
  	struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
+ 	struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
  	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
  
  	pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
@@@ -1213,6 -1218,12 +1218,12 @@@
  	pstate_table->socclk_pstate.curr.min = SMU_DPM_TABLE_MIN(soc_table);
  	pstate_table->socclk_pstate.curr.max = SMU_DPM_TABLE_MAX(soc_table);
  
+ 	pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table);
+ 	pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table);
+ 	pstate_table->fclk_pstate.curr.min = SMU_DPM_TABLE_MIN(fclk_table);
+ 	pstate_table->fclk_pstate.curr.max = SMU_DPM_TABLE_MAX(fclk_table);
+ 	pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table);
+ 
  	if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
  	    mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
  	    soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
@@@ -1398,7 -1409,15 +1409,15 @@@ static int smu_v13_0_6_emit_clk_levels(
  				      pstate_table->uclk_pstate.curr.min,
  				      pstate_table->uclk_pstate.curr.max);
  		break;
+ 	case SMU_OD_FCLK:
+ 		if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT))
+ 			return -EOPNOTSUPP;
  
+ 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_FCLK");
+ 		size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
+ 				      pstate_table->fclk_pstate.curr.min,
+ 				      pstate_table->fclk_pstate.curr.max);
+ 		break;
  	case SMU_SCLK:
  	case SMU_GFXCLK:
  		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
@@@ -2040,7 -2059,7 +2059,7 @@@ static int smu_v13_0_6_set_soft_freq_li
  	int ret = 0;
  
  	if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
- 	    clk_type != SMU_UCLK)
+ 	    clk_type != SMU_UCLK && clk_type != SMU_FCLK)
  		return -EINVAL;
  
  	if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
@@@ -2081,6 -2100,15 +2100,15 @@@
  				pstate_table->uclk_pstate.curr.max = max;
  		}
  
+ 		if (clk_type == SMU_FCLK) {
+ 			if (max == pstate_table->fclk_pstate.curr.max)
+ 				return 0;
+ 
+ 			ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_FCLK, 0, max, false);
+ 			if (!ret)
+ 				pstate_table->fclk_pstate.curr.max = max;
+ 		}
+ 
  		return ret;
  	}
  
@@@ -2123,6 -2151,7 +2151,7 @@@ static int smu_v13_0_6_usr_edit_dpm_tab
  	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
  	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
  	struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table;
+ 	struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
  	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
  	uint32_t min_clk;
  	uint32_t max_clk;
@@@ -2203,6 -2232,40 +2232,40 @@@
  			pstate_table->uclk_pstate.custom.max = input[1];
  		}
  		break;
+ 	case PP_OD_EDIT_FCLK_TABLE:
+ 		if (size != 2) {
+ 			dev_err(smu->adev->dev,
+ 				"Input parameter number not correct\n");
+ 			return -EINVAL;
+ 		}
+ 
+ 		if (!smu_cmn_feature_is_enabled(smu,
+ 						SMU_FEATURE_DPM_FCLK_BIT)) {
+ 			dev_warn(smu->adev->dev,
+ 				 "FCLK limits setting not supported!\n");
+ 			return -EOPNOTSUPP;
+ 		}
+ 
+ 		max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table);
+ 		if (input[0] == 0) {
+ 			dev_info(smu->adev->dev,
+ 				 "Setting min FCLK level is not supported\n");
+ 			return -EOPNOTSUPP;
+ 		} else if (input[0] == 1) {
+ 			if (input[1] > max_clk) {
+ 				dev_warn(smu->adev->dev,
+ 					 "Maximum FCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
+ 					 input[1], max_clk);
+ 				pstate_table->fclk_pstate.custom.max =
+ 					pstate_table->fclk_pstate.curr.max;
+ 				return -EINVAL;
+ 			}
+ 
+ 			pstate_table->fclk_pstate.custom.max = input[1];
+ 		} else {
+ 			return -EINVAL;
+ 		}
+ 		break;
  
  	case PP_OD_RESTORE_DEFAULT_TABLE:
  		if (size != 0) {
@@@ -2232,6 -2295,17 +2295,17 @@@
  				if (ret)
  					return ret;
  			}
+ 
+ 			if (SMU_DPM_TABLE_MAX(fclk_table) !=
+ 			    pstate_table->fclk_pstate.curr.max) {
+ 				max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table);
+ 				min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.fclk_table);
+ 				ret = smu_v13_0_6_set_soft_freq_limited_range(smu,
+ 									      SMU_FCLK, min_clk,
+ 									      max_clk, false);
+ 				if (ret)
+ 					return ret;
+ 			}
  			smu_v13_0_reset_custom_level(smu);
  		}
  		break;
@@@ -2258,6 -2332,16 +2332,16 @@@
  			if (ret)
  				return ret;
  
+ 			if (pstate_table->fclk_pstate.custom.max) {
+ 				min_clk = pstate_table->fclk_pstate.curr.min;
+ 				max_clk = pstate_table->fclk_pstate.custom.max;
+ 				ret = smu_v13_0_6_set_soft_freq_limited_range(smu,
+ 									      SMU_FCLK, min_clk,
+ 									      max_clk, false);
+ 				if (ret)
+ 					return ret;
+ 			}
+ 
  			if (!pstate_table->uclk_pstate.custom.max)
  				return 0;
  
@@@ -3163,14 -3247,25 +3247,25 @@@ static int smu_v13_0_6_reset_vcn(struc
  
  static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg)
  {
+ 	struct amdgpu_device *adev = smu->adev;
  	int ret;
  
+ 	if (amdgpu_sriov_vf(adev))
+ 		return -EOPNOTSUPP;
+ 
  	switch (msg) {
  	case SMU_MSG_QueryValidMcaCount:
  	case SMU_MSG_QueryValidMcaCeCount:
  	case SMU_MSG_McaBankDumpDW:
  	case SMU_MSG_McaBankCeDumpDW:
  	case SMU_MSG_ClearMcaOnRead:
+ 	case SMU_MSG_GetRASTableVersion:
+ 	case SMU_MSG_GetBadPageCount:
+ 	case SMU_MSG_GetBadPageMcaAddr:
+ 	case SMU_MSG_SetTimestamp:
+ 	case SMU_MSG_GetTimestamp:
+ 	case SMU_MSG_GetBadPageIpid:
+ 	case SMU_MSG_EraseRasTable:
  		ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg);
  		break;
  	default:

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