linux-next: manual merge of the pci tree with the arm64 tree

[Mark Brown <broonie@kernel.org>]

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Hi all,

Today's linux-next merge of the pci tree got a conflict in:

  arch/arm64/Kconfig

between commit:

  12aab25ca56ee ("arm64: errata: work around NVIDIA Olympus device store/load ordering")

from the arm64 tree and commit:

  a8818827486cd ("irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround")

from the pci tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc arch/arm64/Kconfig
index fe807d72a3e7b,b9e17ce475e61..0000000000000
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@@ -1405,28 -1382,15 +1405,37 @@@ config NVIDIA_CARMEL_CNP_ERRATU
  
  	  If unsure, say Y.
  
 +config NVIDIA_OLYMPUS_1027_ERRATUM
 +	bool "NVIDIA Olympus: device store/load ordering erratum"
 +	default y
 +	help
 +	  This option adds an alternative code sequence to work around an
 +	  NVIDIA Olympus core erratum where a Device-nGnR* store can be
 +	  observed by a peripheral after a younger Device-nGnR* load to the
 +	  same peripheral. This breaks the program order that drivers rely
 +	  on for MMIO and can leave a device in an incorrect state.
 +
 +	  The workaround inserts a DMB OSH immediately before raw MMIO loads.
 +	  The erratum cannot occur when a DMB that orders loads appears
 +	  between the store and load, preventing the younger load from being
 +	  observed before the older store.
 +
 +	  The alternatives framework patches in DMB OSH only when an affected
 +	  CPU is detected. Other CPUs execute a NOP in its place. Disabling
 +	  this option leaves the original MMIO read instruction stream
 +	  unchanged.
 +
 +	  If unsure, say Y.
 +
+ config RENESAS_ERRATUM_GEN4GICITS1
+ 	bool "Renesas R-Car Gen4: GIC600 can not access physical addresses above 4 GiB"
+ 	default y
+ 	help
+ 	  The Renesas R-Car Gen4 S4/V4H/V4M GIC600 SoC integrations have AXI
+ 	  addressing limited to the first 32-bit of physical address space.
+ 
+ 	  If unsure, say Y.
+ 
  config ROCKCHIP_ERRATUM_3568002
  	bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
  	default y

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