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* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2025-09-22  9:50 Mark Brown
  2025-09-22 11:27 ` Aithal, Srikanth
  2025-09-30 18:13 ` Paolo Bonzini
  0 siblings, 2 replies; 15+ messages in thread
From: Mark Brown @ 2025-09-22  9:50 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Linux Kernel Mailing List, Linux Next Mailing List,
	Peter Zijlstra

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/kvm/emulate.c

between commit:

  6204aea36b74c ("KVM: x86: Introduce EM_ASM_1")

from the tip tree and commit:

  f8457615b71c6 ("KVM: x86: Don't emulate instructions affected by CET features")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc arch/x86/kvm/emulate.c
index 796d0c64f9baf,5c5fb6a6f7f92..0000000000000
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@@ -4001,11 -4153,11 +4088,11 @@@ static const struct opcode group4[] = 
  };
  
  static const struct opcode group5[] = {
 -	F(DstMem | SrcNone | Lock,		em_inc),
 -	F(DstMem | SrcNone | Lock,		em_dec),
 +	I(DstMem | SrcNone | Lock,		em_inc),
 +	I(DstMem | SrcNone | Lock,		em_dec),
- 	I(SrcMem | NearBranch | IsBranch,       em_call_near_abs),
- 	I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far),
+ 	I(SrcMem | NearBranch | IsBranch | ShadowStack, em_call_near_abs),
+ 	I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack, em_call_far),
 -	I(SrcMem | NearBranch | IsBranch, em_jmp_abs),
 +	I(SrcMem | NearBranch | IsBranch,       em_jmp_abs),
  	I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far),
  	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
  };
diff --cc arch/x86/include/asm/cpufeatures.h
index b2a562217d3ff,8738bd783de22..0000000000000
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -495,8 -496,7 +496,9 @@@
  #define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
  #define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
  #define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */
 -#define X86_FEATURE_MSR_IMM		(21*32+14) /* MSR immediate form instructions */
 +#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
 +#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */
++#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */
  
  /*
   * BUG word(s)
diff --cc arch/x86/include/asm/msr-index.h
index 718a55d82fe45,717baeba6db3c..0000000000000
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@@ -315,14 -315,15 +315,16 @@@
  #define PERF_CAP_PT_IDX			16
  
  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
 -
+ #define PERF_CAP_LBR_FMT		0x3f
  #define PERF_CAP_PEBS_TRAP		BIT_ULL(6)
  #define PERF_CAP_ARCH_REG		BIT_ULL(7)
  #define PERF_CAP_PEBS_FORMAT		0xf00
+ #define PERF_CAP_FW_WRITES		BIT_ULL(13)
  #define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)
 +#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)
  #define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
 -					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
 +					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
 +					 PERF_CAP_PEBS_TIMING_INFO)
  
  #define MSR_IA32_RTIT_CTL		0x00000570
  #define RTIT_CTL_TRACEEN		BIT(0)
diff --cc arch/x86/kvm/emulate.c
index 796d0c64f9baf,5c5fb6a6f7f92..0000000000000
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@@ -4001,11 -4153,11 +4088,11 @@@ static const struct opcode group4[] = 
  };
  
  static const struct opcode group5[] = {
  	F(DstMem | SrcNone | Lock,		em_inc),
  	F(DstMem | SrcNone | Lock,		em_dec),
- 	I(SrcMem | NearBranch | IsBranch,       em_call_near_abs),
- 	I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far),
+ 	I(SrcMem | NearBranch | IsBranch | ShadowStack, em_call_near_abs),
+ 	I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack, em_call_far),
 -	I(SrcMem | NearBranch | IsBranch, em_jmp_abs),
 +	I(SrcMem | NearBranch | IsBranch,       em_jmp_abs),
  	I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far),
  	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
  };

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2025-11-20  4:52 Stephen Rothwell
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Rothwell @ 2025-11-20  4:52 UTC (permalink / raw)
  To: Sean Christopherson, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Peter Zijlstra
  Cc: Dave Hansen, Elena Reshetova, Linux Kernel Mailing List,
	Linux Next Mailing List, Naveen N Rao

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/include/asm/cpufeatures.h

between commit:

  6ffdb49101f0 ("x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag")

from the tip tree and commits:

  5d0316e25def ("x86/cpufeatures: Add X86_FEATURE_X2AVIC_EXT")
  f6106d41ec84 ("x86/bugs: Use an x86 feature to track the MMIO Stale Data mitigation")
  9c6bbdaab7e6 ("Merge branch 'svm'")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2025-11-20  4:46 Stephen Rothwell
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Rothwell @ 2025-11-20  4:46 UTC (permalink / raw)
  To: Sean Christopherson, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Peter Zijlstra
  Cc: Dave Hansen, Elena Reshetova, Linux Kernel Mailing List,
	Linux Next Mailing List, Naveen N Rao

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/include/asm/cpufeatures.h

between commit:

  6ffdb49101f0 ("x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag")

from the tip tree and commits:

  5d0316e25def ("x86/cpufeatures: Add X86_FEATURE_X2AVIC_EXT")
  f6106d41ec84 ("x86/bugs: Use an x86 feature to track the MMIO Stale Data mitigation")
  9c6bbdaab7e6 ("Merge branch 'svm'")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/include/asm/cpufeatures.h
index b6472e252491,646d2a77a2e2..000000000000
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -503,7 -500,12 +504,13 @@@
  #define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
  #define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */
  #define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */
 -#define X86_FEATURE_X2AVIC_EXT		(21*32+17) /* AMD SVM x2AVIC support for 4k vCPUs */
 -#define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+18) /*
 +#define X86_FEATURE_SGX_EUPDATESVN	(21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */
++#define X86_FEATURE_X2AVIC_EXT		(21*32+18) /* AMD SVM x2AVIC support for 4k vCPUs */
++#define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+19) /*
+ 						      * Clear CPU buffers before VM-Enter if the vCPU
+ 						      * can access host MMIO (ignored for all intents
+ 						      * and purposes if CLEAR_CPU_BUF_VM is set).
+ 						      */
  
  /*
   * BUG word(s)

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2025-10-20  0:07 Stephen Rothwell
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Rothwell @ 2025-10-20  0:07 UTC (permalink / raw)
  To: Sean Christopherson, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Peter Zijlstra
  Cc: Dave Hansen, Elena Reshetova, Naveen N Rao (AMD),
	Linux Kernel Mailing List, Linux Next Mailing List

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/include/asm/cpufeatures.h

between commit:

  6ffdb49101f0 ("x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag")

from the tip tree and commit:

  5d0316e25def ("x86/cpufeatures: Add X86_FEATURE_X2AVIC_EXT")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/include/asm/cpufeatures.h
index 592909dbe0a8,7129eb44adad..000000000000
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -502,7 -500,7 +503,8 @@@
  #define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
  #define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */
  #define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */
 -#define X86_FEATURE_X2AVIC_EXT		(21*32+17) /* AMD SVM x2AVIC support for 4k vCPUs */
 +#define X86_FEATURE_SGX_EUPDATESVN	(21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */
++#define X86_FEATURE_X2AVIC_EXT		(21*32+18) /* AMD SVM x2AVIC support for 4k vCPUs */
  
  /*
   * BUG word(s)

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2025-09-19 13:50 Mark Brown
  0 siblings, 0 replies; 15+ messages in thread
From: Mark Brown @ 2025-09-19 13:50 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Dapeng Mi, Linux Kernel Mailing List, Linux Next Mailing List,
	Mingwei Zhang, Peter Zijlstra

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/include/asm/msr-index.h

between commit:

  0c5caea762de3 ("perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag")

from the tip tree and commit:

  cdfed9370b96a ("KVM: x86/pmu: Move PMU_CAP_{FW_WRITES,LBR_FMT} into msr-index.h header")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc arch/x86/include/asm/msr-index.h
index 718a55d82fe45,717baeba6db3c..0000000000000
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@@ -315,14 -315,15 +315,16 @@@
  #define PERF_CAP_PT_IDX			16
  
  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
 -
+ #define PERF_CAP_LBR_FMT		0x3f
  #define PERF_CAP_PEBS_TRAP		BIT_ULL(6)
  #define PERF_CAP_ARCH_REG		BIT_ULL(7)
  #define PERF_CAP_PEBS_FORMAT		0xf00
+ #define PERF_CAP_FW_WRITES		BIT_ULL(13)
  #define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)
 +#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)
  #define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
 -					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
 +					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
 +					 PERF_CAP_PEBS_TIMING_INFO)
  
  #define MSR_IA32_RTIT_CTL		0x00000570
  #define RTIT_CTL_TRACEEN		BIT(0)

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2025-01-06  4:05 Stephen Rothwell
  2025-01-09 19:18 ` Sean Christopherson
  2025-01-23  3:25 ` Stephen Rothwell
  0 siblings, 2 replies; 15+ messages in thread
From: Stephen Rothwell @ 2025-01-06  4:05 UTC (permalink / raw)
  To: Sean Christopherson, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Peter Zijlstra
  Cc: Borislav Petkov (AMD), Linux Kernel Mailing List,
	Linux Next Mailing List

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/kvm/cpuid.c

between commit:

  716f86b523d8 ("KVM: x86: Advertise SRSO_USER_KERNEL_NO to userspace")

from the tip tree and commits:

  ccf93de484a3 ("KVM: x86: Unpack F() CPUID feature flag macros to one flag per line of code")
  3cc359ca29ad ("KVM: x86: Rename kvm_cpu_cap_mask() to kvm_cpu_cap_init()")
  75c489e12d4b ("KVM: x86: Add a macro for features that are synthesized into boot_cpu_data")
  871ac338ef55 ("KVM: x86: Use only local variables (no bitmask) to init kvm_cpu_caps")

from the kvm-x86 tree.

I fixed it up (I think - see below) and can carry the fix as
necessary. This is now fixed as far as linux-next is concerned, but any
non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging.  You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/kvm/cpuid.c
index f7e222953cab,edef30359c19..000000000000
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@@ -808,50 -1134,72 +1134,73 @@@ void kvm_set_cpu_caps(void
  	    !boot_cpu_has(X86_FEATURE_AMD_SSBD))
  		kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
  
- 	/*
- 	 * Hide all SVM features by default, SVM will set the cap bits for
- 	 * features it emulates and/or exposes for L1.
- 	 */
- 	kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
- 
- 	kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
- 		0 /* SME */ | 0 /* SEV */ | 0 /* VM_PAGE_FLUSH */ | 0 /* SEV_ES */ |
- 		F(SME_COHERENT));
- 
- 	kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
- 		F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
- 		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
- 		F(WRMSR_XX_BASE_NS) | F(SRSO_USER_KERNEL_NO)
+ 	/* All SVM features required additional vendor module enabling. */
+ 	kvm_cpu_cap_init(CPUID_8000_000A_EDX,
+ 		VENDOR_F(NPT),
+ 		VENDOR_F(VMCBCLEAN),
+ 		VENDOR_F(FLUSHBYASID),
+ 		VENDOR_F(NRIPS),
+ 		VENDOR_F(TSCRATEMSR),
+ 		VENDOR_F(V_VMSAVE_VMLOAD),
+ 		VENDOR_F(LBRV),
+ 		VENDOR_F(PAUSEFILTER),
+ 		VENDOR_F(PFTHRESHOLD),
+ 		VENDOR_F(VGIF),
+ 		VENDOR_F(VNMI),
+ 		VENDOR_F(SVME_ADDR_CHK),
  	);
  
- 	kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB);
- 	kvm_cpu_cap_check_and_set(X86_FEATURE_IBPB_BRTYPE);
- 	kvm_cpu_cap_check_and_set(X86_FEATURE_SRSO_NO);
- 
- 	kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX,
- 		F(PERFMON_V2)
+ 	kvm_cpu_cap_init(CPUID_8000_001F_EAX,
+ 		VENDOR_F(SME),
+ 		VENDOR_F(SEV),
+ 		/* VM_PAGE_FLUSH */
+ 		VENDOR_F(SEV_ES),
+ 		F(SME_COHERENT),
+ 	);
+ 
+ 	kvm_cpu_cap_init(CPUID_8000_0021_EAX,
+ 		F(NO_NESTED_DATA_BP),
+ 		/*
+ 		 * Synthesize "LFENCE is serializing" into the AMD-defined entry
+ 		 * in KVM's supported CPUID, i.e. if the feature is reported as
+ 		 * supported by the kernel.  LFENCE_RDTSC was a Linux-defined
+ 		 * synthetic feature long before AMD joined the bandwagon, e.g.
+ 		 * LFENCE is serializing on most CPUs that support SSE2.  On
+ 		 * CPUs that don't support AMD's leaf, ANDing with the raw host
+ 		 * CPUID will drop the flags, and reporting support in AMD's
+ 		 * leaf can make it easier for userspace to detect the feature.
+ 		 */
+ 		SYNTHESIZED_F(LFENCE_RDTSC),
+ 		/* SmmPgCfgLock */
+ 		F(NULL_SEL_CLR_BASE),
+ 		F(AUTOIBRS),
+ 		EMULATED_F(NO_SMM_CTL_MSR),
+ 		/* PrefetchCtlMsr */
+ 		F(WRMSR_XX_BASE_NS),
++		F(SRSO_USER_KERNEL_NO),
+ 		SYNTHESIZED_F(SBPB),
+ 		SYNTHESIZED_F(IBPB_BRTYPE),
+ 		SYNTHESIZED_F(SRSO_NO),
+ 	);
+ 
+ 	kvm_cpu_cap_init(CPUID_8000_0022_EAX,
+ 		F(PERFMON_V2),
  	);
  
- 	/*
- 	 * Synthesize "LFENCE is serializing" into the AMD-defined entry in
- 	 * KVM's supported CPUID if the feature is reported as supported by the
- 	 * kernel.  LFENCE_RDTSC was a Linux-defined synthetic feature long
- 	 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most
- 	 * CPUs that support SSE2.  On CPUs that don't support AMD's leaf,
- 	 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing
- 	 * the mask with the raw host CPUID, and reporting support in AMD's
- 	 * leaf can make it easier for userspace to detect the feature.
- 	 */
- 	if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
- 		kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC);
  	if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
  		kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE);
- 	kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR);
  
- 	kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
- 		F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
- 		F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
- 		F(PMM) | F(PMM_EN)
+ 	kvm_cpu_cap_init(CPUID_C000_0001_EDX,
+ 		F(XSTORE),
+ 		F(XSTORE_EN),
+ 		F(XCRYPT),
+ 		F(XCRYPT_EN),
+ 		F(ACE2),
+ 		F(ACE2_EN),
+ 		F(PHE),
+ 		F(PHE_EN),
+ 		F(PMM),
+ 		F(PMM_EN),
  	);
  
  	/*

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2024-02-07  4:35 Stephen Rothwell
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Rothwell @ 2024-02-07  4:35 UTC (permalink / raw)
  To: Sean Christopherson, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Peter Zijlstra
  Cc: Ashish Kalra, Borislav Petkov (AMD), Brijesh Singh,
	Jarkko Sakkinen, Linux Kernel Mailing List,
	Linux Next Mailing List, Michael Roth, Tom Lendacky

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Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/kvm/svm/sev.c

between commit:

  1ca5614b84ee ("crypto: ccp: Add support to initialize the AMD-SP for SEV-SNP")

from the tip tree and commit:

  cc4ce37bed85 ("KVM: SVM: Set sev->asid in sev_asid_new() instead of overloading the return")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/kvm/svm/sev.c
index f99435b6648f,f06f9e51ad9d..000000000000
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@@ -246,8 -254,7 +254,8 @@@ static void sev_unbind_asid(struct kvm 
  static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
  {
  	struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 +	struct sev_platform_init_args init_args = {0};
- 	int asid, ret;
+ 	int ret;
  
  	if (kvm->created_vcpus)
  		return -EINVAL;
@@@ -258,13 -264,11 +265,12 @@@
  
  	sev->active = true;
  	sev->es_active = argp->id == KVM_SEV_ES_INIT;
- 	asid = sev_asid_new(sev);
- 	if (asid < 0)
+ 	ret = sev_asid_new(sev);
+ 	if (ret)
  		goto e_no_asid;
- 	sev->asid = asid;
  
 -	ret = sev_platform_init(&argp->error);
 +	init_args.probe = false;
 +	ret = sev_platform_init(&init_args);
  	if (ret)
  		goto e_free;
  

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^ permalink raw reply	[flat|nested] 15+ messages in thread
* linux-next: manual merge of the kvm-x86 tree with the tip tree
@ 2023-01-19 23:54 Stephen Rothwell
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Rothwell @ 2023-01-19 23:54 UTC (permalink / raw)
  To: Sean Christopherson, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Peter Zijlstra
  Cc: Ingo Molnar, Jim Mattson, Kan Liang, Linux Kernel Mailing List,
	Linux Next Mailing List, Xin Li

[-- Attachment #1: Type: text/plain, Size: 1860 bytes --]

Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/include/asm/cpufeatures.h

between commits:

  a018d2e3d4b1 ("x86/cpufeatures: Add Architectural PerfMon Extension bit")
  660569472dd7 ("x86/cpufeature: Add the CPU feature bit for LKGS")

from the tip tree and commit:

  751b1e1ee8e9 ("x86/cpufeatures: Add macros for Intel's new fast rep string features")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/include/asm/cpufeatures.h
index 7b319acda31a,cdb7e1492311..000000000000
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -312,8 -312,9 +312,11 @@@
  #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
  #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
  #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
 +#define X86_FEATURE_ARCH_PERFMON_EXT	(12*32+ 8) /* "" Intel Architectural PerfMon Extension */
+ #define X86_FEATURE_FZRM		(12*32+10) /* "" Fast zero-length REP MOVSB */
+ #define X86_FEATURE_FSRS		(12*32+11) /* "" Fast short REP STOSB */
+ #define X86_FEATURE_FSRC		(12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
 +#define X86_FEATURE_LKGS		(12*32+18) /* "" Load "kernel" (userspace) GS */
  #define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */
  #define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
  

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^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2025-11-20  4:52 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-22  9:50 linux-next: manual merge of the kvm-x86 tree with the tip tree Mark Brown
2025-09-22 11:27 ` Aithal, Srikanth
2025-09-22 11:40   ` Mark Brown
2025-09-22 13:23     ` Mark Brown
2025-09-22 14:04     ` Sean Christopherson
2025-09-30 18:13 ` Paolo Bonzini
  -- strict thread matches above, loose matches on Subject: below --
2025-11-20  4:52 Stephen Rothwell
2025-11-20  4:46 Stephen Rothwell
2025-10-20  0:07 Stephen Rothwell
2025-09-19 13:50 Mark Brown
2025-01-06  4:05 Stephen Rothwell
2025-01-09 19:18 ` Sean Christopherson
2025-01-23  3:25 ` Stephen Rothwell
2024-02-07  4:35 Stephen Rothwell
2023-01-19 23:54 Stephen Rothwell

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