From: Prike Liang <Prike.Liang@amd.com>
To: linux-nvme@lists.infradead.org, Chaitanya.Kulkarni@wdc.com,
kbusch@kernel.org, axboe@fb.com, hch@lst.de, sagi@grimberg.me
Cc: Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com,
Prike Liang <Prike.Liang@amd.com>
Subject: [PATCH v2] nvme: put some AMD PCIE downstream NVME device to simple suspend/resume path
Date: Wed, 31 Mar 2021 20:48:05 +0800 [thread overview]
Message-ID: <1617194885-459-1-git-send-email-Prike.Liang@amd.com> (raw)
The NVME device pluged in some AMD PCIE root port will resume timeout
from s2idle which caused by NVME power CFG lost in the SMU FW restore.
This issue can be workaround by using PCIe power set with simple
suspend/resume process path instead of APST. In the onwards ASIC will
try do the NVME shutdown save and restore in the BIOS and still need PCIe
power seting to resume from RTD3 for s2idle.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
Changes in v2:
Fix the patch format and check chip root complex DID instead of PCIe RP
to avoid the storage device plugged in internal PCIe RP by USB adaptor.
---
drivers/nvme/host/pci.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 6bad4d4..1952da1 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -42,6 +42,9 @@
#define NVME_MAX_KB_SZ 4096
#define NVME_MAX_SEGS 127
+#define AMD_PCIE_ID_CZN 0x1630
+#define AMD_PCIE_ID_RN AMD_PCIE_ID_CZN
+
static int use_threaded_interrupts;
module_param(use_threaded_interrupts, int, 0);
@@ -70,6 +73,12 @@ static unsigned int io_queue_depth = 1024;
module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
+static const struct pci_device_id pcie_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_RN) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_CZN) },
+ { }
+};
+
static int io_queue_count_set(const char *val, const struct kernel_param *kp)
{
unsigned int n;
@@ -2832,6 +2841,7 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
{
struct acpi_device *adev;
struct pci_dev *root;
+ struct pci_dev *rdev;
acpi_handle handle;
acpi_status status;
u8 val;
@@ -2845,6 +2855,15 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
if (!root)
return false;
+ rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
+ if (rdev && pci_match_id(pcie_ids, rdev)) {
+ /* Detect NVME device which pluged in the Renoir PCIE root port
+ * then force use quick suspend/resume path for handling the NVME
+ * timeout during s2idle resume.
+ */
+ return NVME_QUIRK_SIMPLE_SUSPEND;
+ }
+
adev = ACPI_COMPANION(&root->dev);
if (!adev)
return false;
--
2.7.4
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next reply other threads:[~2021-03-31 12:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 12:48 Prike Liang [this message]
2021-03-31 20:47 ` [PATCH v2] nvme: put some AMD PCIE downstream NVME device to simple suspend/resume path Chaitanya Kulkarni
2021-04-01 1:04 ` Liang, Prike
2021-04-01 1:51 ` Keith Busch
2021-04-01 2:05 ` Chaitanya Kulkarni
2021-04-06 7:17 ` Liang, Prike
2021-04-01 9:16 ` Christoph Hellwig
2021-04-11 3:32 ` Liang, Prike
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