From: keith.busch@intel.com (Keith Busch)
Subject: [PATCH V3] nvme-pci: add sgl support
Date: Tue, 1 Aug 2017 04:48:04 -0400 [thread overview]
Message-ID: <20170801084803.GB7837@localhost.localdomain> (raw)
In-Reply-To: <MWHPR04MB1008D3259D1E7EDB5BAC0FDD86B30@MWHPR04MB1008.namprd04.prod.outlook.com>
On Tue, Aug 01, 2017@08:29:00AM +0000, Chaitanya Kulkarni wrote:
> [CK] Yes, I've observed approximately %5 better
> performance for IO sizes larger than 32k (for sgl_threshold = 32k).
Is that a physically contiguous 32k, or does each 4k require a different
SG element? Could you try to force both conditions and see how each
scenario compares with PRP?
next prev parent reply other threads:[~2017-08-01 8:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-26 18:19 [PATCH V3] nvme-pci: add sgl support Chaitanya Kulkarni
2017-07-26 18:19 ` Chaitanya Kulkarni
2017-07-31 6:30 ` Sagi Grimberg
2017-07-31 6:45 ` Sagi Grimberg
2017-07-31 7:13 ` Keith Busch
2017-07-31 11:18 ` Sagi Grimberg
2017-08-01 8:29 ` Chaitanya Kulkarni
2017-08-01 8:48 ` Keith Busch [this message]
2017-08-10 8:59 ` Christoph Hellwig
2017-08-10 16:47 ` Keith Busch
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