From: helgaas@kernel.org (Bjorn Helgaas)
Subject: [PATCH] PCI: Add Intel remapped NVMe device support
Date: Wed, 19 Jun 2019 08:52:12 -0500 [thread overview]
Message-ID: <20190619135212.GB143205@google.com> (raw)
In-Reply-To: <1f56c881-9005-f8ad-1557-5efd6e0ef535@suse.de>
On Tue, Jun 18, 2019@05:15:52PM +0200, Hannes Reinecke wrote:
> On 6/18/19 10:06 AM, Daniel Drake wrote:
> > We can probably also use these registers for MSI support. I
> > started to experiment, doesn't quite work but I'll keep poking.
> > The doc suggests there is a single MSI-X vector for the AHCI SATA
> > device, and AHCI MSI-X Starting Vector (AMXV) has value 0x140 on
> > this platform. No idea how to interpret that value. From
> > experimentation, the AHCI SATA disk generates interrupts on vector
> > 0.
> >
> The 0x140 is probably the offset into the PCI config space where the
> AHCI MSI-X vector table can be found ...
An MSI-X vector table is in memory space, not config space. You'd
have to look at PCI_MSIX_TABLE_BIR to find which BAR maps it, and then
add PCI_MSIX_TABLE_OFFSET to the BAR value.
Bjorn
next prev parent reply other threads:[~2019-06-19 13:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 7:44 [PATCH] PCI: Add Intel remapped NVMe device support Daniel Drake
2019-06-10 16:00 ` Keith Busch
2019-06-11 2:46 ` Daniel Drake
2019-06-12 14:32 ` Keith Busch
2019-06-13 8:54 ` Christoph Hellwig
2019-06-14 2:26 ` Daniel Drake
2019-06-14 19:36 ` Keith Busch
2019-06-14 20:05 ` Bjorn Helgaas
2019-06-14 21:05 ` Keith Busch
2019-06-18 7:48 ` Hannes Reinecke
2019-06-18 7:46 ` Hannes Reinecke
2019-06-18 8:06 ` Daniel Drake
2019-06-18 15:15 ` Hannes Reinecke
2019-06-19 13:52 ` Bjorn Helgaas [this message]
2019-06-10 21:16 ` Bjorn Helgaas
2019-06-11 3:25 ` Daniel Drake
2019-06-11 19:52 ` Bjorn Helgaas
2019-06-12 3:16 ` Daniel Drake
2019-06-12 13:49 ` Bjorn Helgaas
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