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From: Christoph Hellwig <hch@lst.de>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: sagi@grimberg.me, ilias.apalodimas@linaro.org,
	linux-nvme@lists.infradead.org, axboe@fb.com, kbusch@kernel.org,
	hch@lst.de
Subject: Re: [PATCH v3] nvme: retain split access workaround for capability reads
Date: Mon, 7 Oct 2019 14:07:21 +0200	[thread overview]
Message-ID: <20191007120721.GA21060@lst.de> (raw)
In-Reply-To: <20191007114253.30735-1-ard.biesheuvel@linaro.org>

On Mon, Oct 07, 2019 at 01:42:53PM +0200, Ard Biesheuvel wrote:
> This fixes a boot issue on some ARM boxes with NVMe behind a Synopsys
> DesignWare PCIe host controller.

>  static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
>  {
> -	*val = readq(to_nvme_dev(ctrl)->bar + off);
> +	/* use a split read to work around buggy interconnects */
> +	*val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);

I though this was to fix back up the broken Apple controllers?

If you interconnect doesn't support 8-byte MMIO read/write TLPs you
have a much deeper problem, as this will break all drivers using
readq/writeq.  And we currently only have compile time detection for
readq/writeq, not runtime so you'll have to invent a scheme if this
works at all or not.

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  reply	other threads:[~2019-10-07 12:07 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-07 11:42 [PATCH v3] nvme: retain split access workaround for capability reads Ard Biesheuvel
2019-10-07 12:07 ` Christoph Hellwig [this message]
2019-10-07 12:24   ` Ard Biesheuvel
2019-10-07 12:27     ` Christoph Hellwig
2019-10-07 12:32       ` Ard Biesheuvel
2019-10-07 12:47         ` Christoph Hellwig
2019-10-07 12:48         ` Keith Busch
2019-10-07 13:20           ` Ard Biesheuvel
2019-10-07 13:32             ` Keith Busch
2019-10-07 13:33               ` Ard Biesheuvel

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