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Wed, 27 Nov 2019 22:59:07 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B2A9ADB20; Thu, 28 Nov 2019 03:59:05 +0000 (UTC) Received: from ming.t460p (ovpn-8-21.pek2.redhat.com [10.72.8.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9CF6E608B9; Thu, 28 Nov 2019 03:58:58 +0000 (UTC) Date: Thu, 28 Nov 2019 11:58:53 +0800 From: Ming Lei To: Keith Busch Subject: Re: [PATCH 2/4] nvme/pci: Mask legacy and MSI in threaded handler Message-ID: <20191128035853.GF3277@ming.t460p> References: <20191127175824.1929-1-kbusch@kernel.org> <20191127175824.1929-3-kbusch@kernel.org> <20191128033956.GD3277@ming.t460p> <20191128034817.GC1738@redsun51.ssa.fujisawa.hgst.com> MIME-Version: 1.0 In-Reply-To: <20191128034817.GC1738@redsun51.ssa.fujisawa.hgst.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: sUuB7DpSNJ2ISCG5euzLOQ-1 X-Mimecast-Spam-Score: 0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191127_195913_147063_F1697FDD X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-nvme@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagi@grimberg.me, bigeasy@linutronix.de, linux-nvme@lists.infradead.org, helgaas@kernel.org, Thomas Gleixner , hch@lst.de Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-nvme" Errors-To: linux-nvme-bounces+linux-nvme=archiver.kernel.org@lists.infradead.org On Thu, Nov 28, 2019 at 12:48:17PM +0900, Keith Busch wrote: > On Thu, Nov 28, 2019 at 11:39:56AM +0800, Ming Lei wrote: > > On Thu, Nov 28, 2019 at 02:58:22AM +0900, Keith Busch wrote: > > > @@ -1502,6 +1524,11 @@ static int queue_request_irq(struct nvme_queue *nvmeq) > > > int nr = nvmeq->dev->ctrl.instance; > > > > > > if (use_threaded_interrupts) { > > > + /* MSI and Legacy use the same NVMe IRQ masking */ > > > + if (!pdev->msix_enabled) > > > + return pci_request_irq(pdev, nvmeq->cq_vector, > > > + nvme_irq_check_msi, nvme_irq_thread_msi, > > > + nvmeq, "nvme%dq%d", nr, nvmeq->qid); > > > return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, > > > nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); > > > > Just wondering why don't do that for misx_enabled, and according to > > document of request_threaded_irq(), the handler is supposed to > > disable the device's interrupt: > > MSI-x is handled in patch 3/4. I just split the two since the mechanisms > they use to mask interrupts are very different from each other. Fine. > > > 923aa4c378f9("PCI/MSI: Set IRQCHIP_ONESHOT_SAFE for PCI-MSI irqchips"), > > then the question is that if interrupt mask is needed. > > We don't want to use IRQF_ONESHOT for our MSI interrupts because that > will write to the MSI mask config register, which is a costly non-posted > transaction. The NVMe specific way uses much faster posted writes. What I meant is that IRQF_ONESHOT isn't needed in case of IRQCHIP_ONESHOT_SAFE. So it is reasonable to understand that interrupt mask isn't needed in the hard interrupt handler in case of IRQCHIP_ONESHOT_SAFE. That is basically what commit dc9b229a58dc("genirq: Allow irq chips to mark themself oneshot safe") does. Thanks, Ming _______________________________________________ linux-nvme mailing list linux-nvme@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-nvme