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Thu, 28 Nov 2019 03:41:41 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9CC0E12CAC32; Thu, 28 Nov 2019 08:41:39 +0000 (UTC) Received: from ming.t460p (ovpn-8-17.pek2.redhat.com [10.72.8.17]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 10F4B5D9E2; Thu, 28 Nov 2019 08:41:31 +0000 (UTC) Date: Thu, 28 Nov 2019 16:41:26 +0800 From: Ming Lei To: Keith Busch Subject: Re: [PATCH 2/4] nvme/pci: Mask legacy and MSI in threaded handler Message-ID: <20191128084126.GB15549@ming.t460p> References: <20191127175824.1929-1-kbusch@kernel.org> <20191127175824.1929-3-kbusch@kernel.org> <20191128033956.GD3277@ming.t460p> <20191128034817.GC1738@redsun51.ssa.fujisawa.hgst.com> <20191128035853.GF3277@ming.t460p> <20191128041404.GB1947@redsun51.ssa.fujisawa.hgst.com> MIME-Version: 1.0 In-Reply-To: <20191128041404.GB1947@redsun51.ssa.fujisawa.hgst.com> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: lCl_NUQSPSOd5SmSq_3QYw-1 X-Mimecast-Spam-Score: 0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191128_004144_804821_0DFA936C X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-nvme@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagi@grimberg.me, bigeasy@linutronix.de, linux-nvme@lists.infradead.org, helgaas@kernel.org, Thomas Gleixner , hch@lst.de Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-nvme" Errors-To: linux-nvme-bounces+linux-nvme=archiver.kernel.org@lists.infradead.org On Thu, Nov 28, 2019 at 01:14:04PM +0900, Keith Busch wrote: > On Thu, Nov 28, 2019 at 11:58:53AM +0800, Ming Lei wrote: > > On Thu, Nov 28, 2019 at 12:48:17PM +0900, Keith Busch wrote: > > > On Thu, Nov 28, 2019 at 11:39:56AM +0800, Ming Lei wrote: > > > > 923aa4c378f9("PCI/MSI: Set IRQCHIP_ONESHOT_SAFE for PCI-MSI irqchips"), > > > > then the question is that if interrupt mask is needed. > > > > > > We don't want to use IRQF_ONESHOT for our MSI interrupts because that > > > will write to the MSI mask config register, which is a costly non-posted > > > transaction. The NVMe specific way uses much faster posted writes. > > > > What I meant is that IRQF_ONESHOT isn't needed in case of IRQCHIP_ONESHOT_SAFE. > > > > So it is reasonable to understand that interrupt mask isn't needed in the > > hard interrupt handler in case of IRQCHIP_ONESHOT_SAFE. That is > > basically what commit dc9b229a58dc("genirq: Allow irq chips to mark themself > > oneshot safe") does. > > Hmm, it doesn't look like it's always safe. We have to stop the device > from generating MSIs for new completions somehow while the threaded > handler is running, otherwise those MSIs will be considered spurious > when the thread never gets a chance to increment desc->threads_handled. > I just observe hard interrupts triggered between start of nvme_irq_check() and end of nvme_irq(). Yeah, there could be at most 36 interrupts comes during the period on one machine, and most are <= 5. So looks this patchset make sense, and also means that IRQCHIP_ONESHOT_SAFE might be broken. @interrupts_during_threaded: [0, 1) 2074375 |@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | [1, 2) 3668018 |@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@| [2, 3) 1508944 |@@@@@@@@@@@@@@@@@@@@@ | [3, 4) 554496 |@@@@@@@ | [4, 5) 225761 |@@@ | [5, 6) 99354 |@ | [6, 7) 45127 | | [7, 8) 20912 | | [8, 9) 9940 | | [9, 10) 4765 | | [10, 11) 2458 | | [11, 12) 1365 | | [12, 13) 719 | | [13, 14) 451 | | [14, 15) 265 | | [15, 16) 168 | | [16, 17) 103 | | [17, 18) 67 | | [18, 19) 60 | | [19, 20) 41 | | [20, 21) 27 | | [21, 22) 18 | | [22, 23) 17 | | [23, 24) 8 | | [24, 25) 2 | | [25, 26) 9 | | [26, 27) 6 | | [27, 28) 3 | | [28, 29) 1 | | [29, 30) 0 | | [30, 31) 0 | | [31, 32) 0 | | [32, 33) 0 | | [33, 34) 0 | | [34, 35) 0 | | [35, 36) 0 | | [36, 37) 1 | | Thanks, Ming _______________________________________________ linux-nvme mailing list linux-nvme@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-nvme