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Wed, 04 Dec 2019 05:22:08 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id F036E18A6EC0; Wed, 4 Dec 2019 10:22:06 +0000 (UTC) Received: from ming.t460p (ovpn-8-17.pek2.redhat.com [10.72.8.17]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A11CF5D6AE; Wed, 4 Dec 2019 10:22:00 +0000 (UTC) Date: Wed, 4 Dec 2019 18:21:55 +0800 From: Ming Lei To: Keith Busch Subject: Re: [RFC PATCH 1/3] nvme/pci: Poll the cq in the primary irq handler Message-ID: <20191204102155.GC5958@ming.t460p> References: <20191202222206.2225-1-kbusch@kernel.org> <20191202222206.2225-2-kbusch@kernel.org> <20191203100930.r76fiu3s5hlbrlxu@linutronix.de> <20191203111626.GA86476@C02WT3WMHTD6.lpcnextlight.net> MIME-Version: 1.0 In-Reply-To: <20191203111626.GA86476@C02WT3WMHTD6.lpcnextlight.net> User-Agent: Mutt/1.12.1 (2019-06-15) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: o-Up9yDDNi2PMlUFhLBSCg-1 X-Mimecast-Spam-Score: 0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191204_022217_946440_EAEBAD9A X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-nvme@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sebastian Andrzej Siewior , hch@lst.de, linux-nvme@lists.infradead.org, sagi@grimberg.me Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-nvme" Errors-To: linux-nvme-bounces+linux-nvme=archiver.kernel.org@lists.infradead.org On Tue, Dec 03, 2019 at 04:16:26AM -0700, Keith Busch wrote: > On Tue, Dec 03, 2019 at 11:09:30AM +0100, Sebastian Andrzej Siewior wrote: > > On 2019-12-03 07:22:04 [+0900], Keith Busch wrote: > > > The nvme threaded interrupt handler reduces CPU time spent in hard irq > > > context, but waking it increases latency for low queue depth workloads. > > > > > > Poll the completion queue once from the primary handler and wake the > > > thread only if more completions remain after. Since there is a window > > > of time where the threaded and primary handlers may run simultaneously, > > > add a new nvmeq flag so that the two can synchronize which owns processing > > > the queue. > > > > It depends on what you mean by "run simultaneously" but it sounds like > > this does not happen. > > > > The primary handler disables the interrupt source and returns > > IRQ_WAKE_THREAD. From now on, the primary handler won't fire (unless it > > is a shared handler and someone else gets an interrupt). > > The driver won't share these interrupts, despite some wierd pci > host bridges that force sharing among other devices (ex: see the > only user of handle_untracked_irq). That isn't what I was considering > though. > > It's true the controller won't send new MSIs once masked, but my > concern is for MSIs on the wire that pass that MMIO mask write. Could you explain a bit what is the 'MSIs on the wire'? And where is it from? Thanks, Ming _______________________________________________ linux-nvme mailing list linux-nvme@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-nvme