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Wed, 18 May 2022 06:28:04 -0700 (PDT) Date: Wed, 18 May 2022 18:57:57 +0530 From: Manivannan Sadhasivam To: Christoph Hellwig Cc: bhelgaas@google.com, lorenzo.pieralisi@arm.com, kbusch@kernel.org, linux-nvme@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, svarbanov@mm-sol.com, bjorn.andersson@linaro.org, axboe@fb.com, quic_vbadigan@quicinc.com, quic_krichai@quicinc.com, quic_nitirawa@quicinc.com, vidyas@nvidia.com, sagi@grimberg.me, linux-pm@vger.kernel.org, rafael@kernel.org, Prasad Malisetty Subject: Re: [PATCH v2 3/3] PCI: qcom: Add system PM support Message-ID: <20220518132757.GC4791@thinkpad> References: <20220518131913.26974-1-manivannan.sadhasivam@linaro.org> <20220518131913.26974-4-manivannan.sadhasivam@linaro.org> <20220518132358.GA26902@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220518132358.GA26902@lst.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220518_062805_586614_848B074B X-CRM114-Status: GOOD ( 17.16 ) X-BeenThere: linux-nvme@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-nvme" Errors-To: linux-nvme-bounces+linux-nvme=archiver.kernel.org@lists.infradead.org On Wed, May 18, 2022 at 03:23:58PM +0200, Christoph Hellwig wrote: > On Wed, May 18, 2022 at 06:49:13PM +0530, Manivannan Sadhasivam wrote: > > From: Prasad Malisetty > > > > Add suspend and resume callbacks to handle system suspend and resume in > > the Qcom PCIe controller driver. When the system suspends, PME turnoff > > message will be sent to the device and the RC driver will wait for the > > device to enter L23 Ready state. After that, the PHY will be powered down > > and clocks/regulators will be disabled. > > So what about just not doing this stupid power disabling to start > with? Unlike x86 where we do not have choice due to the BIOS, we > apparently do here. And disabling power is the wrong thing to do at > least for SSDs as it massively increases the wear on the NAND. That's the requirement the Chromebook based on SC7280 has. I will check internally and get back. Thanks, Mani -- மணிவண்ணன் சதாசிவம்