From: Christoph Hellwig <hch@lst.de>
To: Niklas Cassel <Niklas.Cassel@wdc.com>
Cc: Keith Busch <kbusch@kernel.org>, Christoph Hellwig <hch@lst.de>,
"sagi@grimberg.me" <sagi@grimberg.me>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>
Subject: Re: [PATCH] nvme: add support for TP4084 - Time-to-Ready Enhancements
Date: Wed, 25 May 2022 18:23:42 +0200 [thread overview]
Message-ID: <20220525162342.GA2200@lst.de> (raw)
In-Reply-To: <Yo5W96ivET39WVXf@x1-carbon>
On Wed, May 25, 2022 at 04:19:04PM +0000, Niklas Cassel wrote:
> Right now we do not write CC.CRIME bit _before_ the controller is enabled.
> We set CC.CRIME and CC.ENABLE at the same time, which strictly speaking
> is not according to spec.
>
> Should we perhaps consider splitting the write up into two,
> the first write sets everything except the enable bit,
> and the second write sets everything + the enable bit?
Actually various other CC bits require that as well. It hasn't been
an issue so far, but we might as well fix it. That being said to
properly fix it we'd have to read back a register after setting
CC bits to flush posted writes as well.
prev parent reply other threads:[~2022-05-25 16:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-18 6:40 [PATCH] nvme: add support for TP4084 - Time-to-Ready Enhancements Christoph Hellwig
2022-05-18 9:26 ` Hannes Reinecke
2022-05-18 14:36 ` Keith Busch
2022-05-18 15:00 ` Christoph Hellwig
2022-05-18 15:09 ` Keith Busch
2022-05-18 16:14 ` Chaitanya Kulkarni
2022-05-20 11:51 ` Niklas Cassel
2022-05-20 14:13 ` Keith Busch
2022-05-25 16:19 ` Niklas Cassel
2022-05-25 16:23 ` Christoph Hellwig [this message]
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