From: Christoph Hellwig <hch@lst.de>
To: Niklas Cassel <niklas.cassel@wdc.com>
Cc: Keith Busch <kbusch@kernel.org>, Jens Axboe <axboe@fb.com>,
Christoph Hellwig <hch@lst.de>, Sagi Grimberg <sagi@grimberg.me>,
linux-nvme@lists.infradead.org
Subject: Re: [PATCH] nvme: set controller enable bit in a separate write
Date: Fri, 27 May 2022 07:47:28 +0200 [thread overview]
Message-ID: <20220527054727.GA14930@lst.de> (raw)
In-Reply-To: <20220526135721.390434-1-niklas.cassel@wdc.com>
This looks sensible.
On Thu, May 26, 2022 at 03:57:21PM +0200, Niklas Cassel wrote:
> @@ -2227,6 +2227,16 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
> ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
> ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
> ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
> +
> + ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
> + if (ret)
> + return ret;
> +
> + /* Flush write to device (required if transport is PCI) */
> + ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
> + if (ret)
> + return ret;
Maybe we do eventually want a reg_write32_nonposted, but for now I
think this is sufficient.
next prev parent reply other threads:[~2022-05-27 5:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-26 13:57 [PATCH] nvme: set controller enable bit in a separate write Niklas Cassel
2022-05-27 5:47 ` Christoph Hellwig [this message]
2022-05-31 5:42 ` Christoph Hellwig
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