From: Aurelien Aptel <aaptel@nvidia.com>
To: netdev@vger.kernel.org, davem@davemloft.net, kuba@kernel.org,
edumazet@google.com, pabeni@redhat.com, saeedm@nvidia.com,
tariqt@nvidia.com, linux-nvme@lists.infradead.org,
sagi@grimberg.me, hch@lst.de, kbusch@kernel.org, axboe@fb.com,
chaitanyak@nvidia.com
Cc: smalin@nvidia.com, aaptel@nvidia.com, ogerlitz@nvidia.com,
yorayz@nvidia.com, borisp@nvidia.com, aurelien.aptel@gmail.com,
malin1024@gmail.com
Subject: [PATCH v6 12/23] net/mlx5e: Refactor ico sq polling to get budget
Date: Thu, 20 Oct 2022 13:18:27 +0300 [thread overview]
Message-ID: <20221020101838.2712846-13-aaptel@nvidia.com> (raw)
In-Reply-To: <20221020101838.2712846-1-aaptel@nvidia.com>
From: Or Gerlitz <ogerlitz@nvidia.com>
The mlx5e driver uses ICO SQs for internal control operations which
are not visible to the network stack, such as UMR mapping for striding
RQ (MPWQ) and etc more cases.
The upcoming nvmeotcp offload uses ico sq for umr mapping as part of the
offload. As a pre-step for nvmeotcp ico sqs which have their own napi and
need to comply with budget, add the budget as parameter to the polling of
cqs related to ico sqs.
The polling already stops after a limit is reached, so just have the
caller to provide this limit as the budget.
No functional change here.
Signed-off-by: Or Gerlitz <ogerlitz@nvidia.com>
Signed-off-by: Aurelien Aptel <aaptel@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 2 +-
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 4 ++--
drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h
index 4456ad5cedf1..30c456bfc1c8 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h
@@ -41,7 +41,7 @@ void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
int mlx5e_napi_poll(struct napi_struct *napi, int budget);
-int mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
+int mlx5e_poll_ico_cq(struct mlx5e_cq *cq, int budget);
/* RX */
void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct page *page);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index 58084650151f..261802579791 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
@@ -853,7 +853,7 @@ static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr,
shampo->ci = (shampo->ci + umr.len) & (shampo->hd_per_wq - 1);
}
-int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
+int mlx5e_poll_ico_cq(struct mlx5e_cq *cq, int budget)
{
struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
struct mlx5_cqe64 *cqe;
@@ -928,7 +928,7 @@ int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
wi->wqe_type);
}
} while (!last_wqe);
- } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
+ } while ((++i < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
sq->cc = sqcc;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
index 9a458a5d9853..9ddacb5e1bf4 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
@@ -176,8 +176,8 @@ int mlx5e_napi_poll(struct napi_struct *napi, int budget)
busy |= work_done == budget;
}
- mlx5e_poll_ico_cq(&c->icosq.cq);
- if (mlx5e_poll_ico_cq(&c->async_icosq.cq))
+ mlx5e_poll_ico_cq(&c->icosq.cq, MLX5E_TX_CQ_POLL_BUDGET);
+ if (mlx5e_poll_ico_cq(&c->async_icosq.cq, MLX5E_TX_CQ_POLL_BUDGET))
/* Don't clear the flag if nothing was polled to prevent
* queueing more WQEs and overflowing the async ICOSQ.
*/
--
2.31.1
next prev parent reply other threads:[~2022-10-20 10:50 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 10:18 [PATCH v6 00/23] nvme-tcp receive offloads Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 01/23] net: Introduce direct data placement tcp offload Aurelien Aptel
2022-10-21 5:05 ` Jakub Kicinski
2022-10-21 11:19 ` Aurelien Aptel
2022-10-24 11:22 ` Leon Romanovsky
2022-10-24 13:09 ` Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 02/23] iov_iter: DDP copy to iter/pages Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 03/23] net/tls: export get_netdev_for_sock Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 04/23] Revert "nvme-tcp: remove the unused queue_size member in nvme_tcp_queue" Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 05/23] nvme-tcp: Add DDP offload control path Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 06/23] nvme-tcp: Add DDP data-path Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 07/23] nvme-tcp: RX DDGST offload Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 08/23] nvme-tcp: Deal with netdevice DOWN events Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 09/23] nvme-tcp: Add ulp_offload modparam to control enablement of ULP offload Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 10/23] Documentation: add ULP DDP offload documentation Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 11/23] net/mlx5e: Rename from tls to transport static params Aurelien Aptel
2022-10-20 10:18 ` Aurelien Aptel [this message]
2022-10-20 10:18 ` [PATCH v6 13/23] net/mlx5e: Have mdev pointer directly on the icosq structure Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 14/23] net/mlx5e: Refactor doorbell function to allow avoiding a completion Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 15/23] net/mlx5: Add NVMEoTCP caps, HW bits, 128B CQE and enumerations Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 16/23] net/mlx5e: NVMEoTCP, offload initialization Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 17/23] net/mlx5e: TCP flow steering for nvme-tcp acceleration Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 18/23] net/mlx5e: NVMEoTCP, use KLM UMRs for buffer registration Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 19/23] net/mlx5e: NVMEoTCP, queue init/teardown Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 20/23] net/mlx5e: NVMEoTCP, ddp setup and resync Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 21/23] net/mlx5e: NVMEoTCP, async ddp invalidation Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 22/23] net/mlx5e: NVMEoTCP, data-path for DDP+DDGST offload Aurelien Aptel
2022-10-20 10:18 ` [PATCH v6 23/23] net/mlx5e: NVMEoTCP, statistics Aurelien Aptel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221020101838.2712846-13-aaptel@nvidia.com \
--to=aaptel@nvidia.com \
--cc=aurelien.aptel@gmail.com \
--cc=axboe@fb.com \
--cc=borisp@nvidia.com \
--cc=chaitanyak@nvidia.com \
--cc=davem@davemloft.net \
--cc=edumazet@google.com \
--cc=hch@lst.de \
--cc=kbusch@kernel.org \
--cc=kuba@kernel.org \
--cc=linux-nvme@lists.infradead.org \
--cc=malin1024@gmail.com \
--cc=netdev@vger.kernel.org \
--cc=ogerlitz@nvidia.com \
--cc=pabeni@redhat.com \
--cc=saeedm@nvidia.com \
--cc=sagi@grimberg.me \
--cc=smalin@nvidia.com \
--cc=tariqt@nvidia.com \
--cc=yorayz@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox