From mboxrd@z Thu Jan 1 00:00:00 1970 From: keith.busch@intel.com (Keith Busch) Date: Wed, 3 Jun 2015 20:10:54 +0000 (UTC) Subject: Problems writing to intel P3700 NVMe drive In-Reply-To: References: <00c601d098cd$41255e30$c3701a90$@storageio.com> <00cd01d098d1$94047010$bc0d5030$@storageio.com> <000a01d098ee$b52ce0c0$1f86a240$@storageio.com> Message-ID: +cc the pci list Hi Bjorn, A while back, there were a few proposals on changing the pci driver's default MPS tuning from the existing do-nothing policy to something safe so end-users don't need to remember kernel parameters as described below. Is this still active, or can we kick that back to life if not? Thanks, Keith On Thu, 28 May 2015, Keith Busch wrote: > Perhaps not a desirable/permanent solution, but for everyone's benefit, > we can work-around the problem with kernel parameter: > > pci=pcie_bus_safe > > Using 'pcie_bus_perf' instead may also work, though your original > solution of just using x86 sounded perfectly reasonable to me. :) > > On Thu, 28 May 2015, Pavilion Storage wrote: >> Thanks to Keith Busch for the providing the clues. >> The problem was that the PCIe MPSS on the drive and the CPU root >> complex did not match and that caused a problem. Setting it to a >> common value fixed the problem. >> Kishore