RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC

Paul Walmsley
2008-07-08T22:12:58Z

On Tue, 8 Jul 2008, Rajendra Nayak wrote:

> > From: Paul Walmsley [mailto:paul@pwsan.com]
> >
> > A few notes:
> >
> > - The M2 divider switch does not seem to work consistently on the
> > 3430SDP I use to test. In particular, the switch back to
> > M2=1 results
> > in a hung console.
>
> SRAM being mapped as cacheable could be a possible reason for this.

Certainly possible, and that change needs to be included. But why would
it only happen on the M2 2 -> 1 transition?

- Paul