RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC

Paul Walmsley
2008-07-08T23:46:53Z

On Tue, 8 Jul 2008, Woodruff, Richard wrote:

> > > SRAM being mapped as cacheable could be a possible reason for this.
>
> Second this.

Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
marked cacheable too, right? Did CORE M2 divider changes work in CDP
12.17?

Also still curious why, if it's the cache line eviction issue, it only
locks up on the low- to high-speed transition.

> Can you ping the board by chance when you are locked? Is only user
> space locked out or is the board dead. The SRAM thing resulted in a dead
> lock where MPU was done.

The board doesn't respond to pings.

- Paul