RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC

Woodruff, Richard
2008-07-08T23:55:54Z

> > > > SRAM being mapped as cacheable could be a possible reason for
> this.
> >
> > Second this.
>
> Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
> marked cacheable too, right? Did CORE M2 divider changes work in CDP
> 12.17?

No CDP has it marked strongly order for a while now. Probably around 12.14 or 15.

Yes DVFS works without noticeable hitches on CDP SDP. There was a transition period at the kernel jump it may have stopped but its working now. 12.19 is in pre-test.

> Also still curious why, if it's the cache line eviction issue, it only
> locks up on the low- to high-speed transition.

No answer. It could be another issue. Timing dependent?

Generally a high to low failure is either DDR'ish or an issue with low voltage operation.

If say your I2C failed to raise the voltage or you didn't program in enough setup time into volt control you might try and go fast with out having proper voltage yet.

With the MPU cache deadlock you could still attach with JTAG and assess the state of the system.

You at least can measure voltage at time of lock up. Using observability you can even have a go at correlating it to the first accesses.

Regards,
Richard W.