RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC

Woodruff, Richard
2008-07-08T23:12:47Z

Hi Paul,

> > SRAM being mapped as cacheable could be a possible reason for this.

Second this.

> Certainly possible, and that change needs to be included. But why
> would
> it only happen on the M2 2 -> 1 transition?

Can you ping the board by chance when you are locked? Is only user space locked out or is the board dead.

The SRAM thing resulted in a dead lock where MPU was done.

I've also hit other paths in development where the networking device fails and the system gets caught in kernel space in some kind of livelock trying to get nfs root information.

Regards,
Richard W.