From: "Komal Shah" <komal_shah802003@yahoo.com>
To: linux-omap-open-source@linux.omap.com
Subject: [PATCH 2/2] ARM: OMAP: Use read/write_reg functions for PRCM.
Date: Wed, 14 Jun 2006 04:37:21 -0700 [thread overview]
Message-ID: <1150285041.3056.263790643@webmail.messagingengine.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 580 bytes --]
This patch will break the pm.c and pm-domain.c if CONFIG_PM is enabled.
pm.c changes.
- Use prcm_read/write_reg for preg(...)?? _or_ get function
for each of that reg.
- get/set_reg functions for INTC registers??
- get_reg functions for SDRC_DLLA/B for using with
omap2_sram_suspend ??
- Adding proc based register information as in OMAP1?
pm-domain.c
- Add if (cpu_is_omap2420()) and assigning prcm_base at init.
- Use prcm_readl/writel for other registers which uses _reg32
based access as of now.
--
http://www.fastmail.fm - Does exactly what it says on the tin
[-- Attachment #2: 0002-prcm.patch --]
[-- Type: application/octet-stream, Size: 67421 bytes --]
From nobody Mon Sep 17 00:00:00 2001
From: Komal Shah <komal_shah802003@yahoo.com>
Date: Wed, 14 Jun 2006 22:25:05 +0530
Subject: [PATCH 2/2] ARM: OMAP: Use read/write_reg functions for PRCM.
- Moved prcm.c functions to clock.c
Signed-off-by: Komal Shah <komal_shah802003@yahoo.com>
---
arch/arm/mach-omap2/Makefile | 2
arch/arm/mach-omap2/clock.c | 163 +++++++++++++--------
arch/arm/mach-omap2/clock.h | 244 +++++++++++++++----------------
arch/arm/mach-omap2/io.c | 1
arch/arm/mach-omap2/prcm-regs.h | 268 ++++++++++++++++++----------------
arch/arm/mach-omap2/prcm.c | 40 -----
arch/arm/mach-omap2/sram-fn.S | 12 +-
include/asm-arm/arch-omap/omap24xx.h | 2
8 files changed, 376 insertions(+), 356 deletions(-)
delete mode 100644 arch/arm/mach-omap2/prcm.c
7235fc6f4bc42e99fe0c57394aa2ecc16601eb2e
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 266d88e..6bf9091 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@ # Makefile for the linux kernel.
#
# Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
+obj-y := irq.o id.o io.o sram-fn.o memory.o clock.o mux.o devices.o \
serial.o gpmc.o
obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 719a5e2..45e9844 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -38,6 +38,45 @@ #include "clock.h"
static struct prcm_config *curr_prcm_set;
static u32 curr_perf_level = PRCM_FULL_SPEED;
+static void __iomem *prcm_vbase;
+
+static inline u32 prcm_read_reg(int reg)
+{
+ return __raw_readl(prcm_vbase + (reg));
+}
+
+static inline void prcm_write_reg(int reg, u32 value)
+{
+ __raw_writel((value), prcm_vbase + (reg));
+}
+
+u32 omap_prcm_get_reset_sources(void)
+{
+ u32 reg;
+
+ reg = prcm_read_reg(RM_RSTST_WKUP);
+ reg &= 0x7f;
+
+ return reg;
+}
+EXPORT_SYMBOL(omap_prcm_get_reset_sources);
+
+/* Resets clock rates and reboots the system. Only called from system.h */
+void omap_prcm_arch_reset(char mode)
+{
+ u32 rate, reg;
+ struct clk *vclk, *sclk;
+
+ vclk = clk_get(NULL, "virt_prcm_set");
+ sclk = clk_get(NULL, "sys_ck");
+ rate = clk_get_rate(sclk);
+ clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
+
+ reg = prcm_read_reg(RM_RSTCTRL_WKUP);
+ reg |= RM_RST_GS;
+ prcm_write_reg(RM_RSTCTRL_WKUP, reg);
+}
+
/*-------------------------------------------------------------------------
* Omap2 specific clock functions
*-------------------------------------------------------------------------*/
@@ -45,7 +84,7 @@ static u32 curr_perf_level = PRCM_FULL_S
/* Recalculate SYST_CLK */
static void omap2_sys_clk_recalc(struct clk * clk)
{
- u32 div = PRCM_CLKSRC_CTRL;
+ u32 div = prcm_read_reg(PRCM_CLKSRC_CTRL);
div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
div >>= clk->rate_offset;
clk->rate = (clk->parent->rate / div);
@@ -57,11 +96,11 @@ static u32 omap2_get_dpll_rate(struct cl
long long dpll_clk;
int dpll_mult, dpll_div, amult;
- dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
- dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
+ dpll_mult = (prcm_read_reg(CM_CLKSEL1_PLL) >> 12) & 0x03ff;/* 10 bits */
+ dpll_div = (prcm_read_reg(CM_CLKSEL1_PLL) >> 8) & 0x0f; /* 4 bits */
dpll_clk = (long long)tclk->parent->rate * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
- amult = CM_CLKSEL2_PLL & 0x3;
+ amult = prcm_read_reg(CM_CLKSEL2_PLL) & 0x3;
dpll_clk *= amult;
return dpll_clk;
@@ -88,21 +127,21 @@ static void omap2_clk_fixed_enable(struc
if (clk->enable_bit == 0xff) /* Parent will do it */
return;
- cval = CM_CLKEN_PLL;
+ cval = prcm_read_reg(CM_CLKEN_PLL);
if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
return;
cval &= ~(0x3 << clk->enable_bit);
cval |= (0x3 << clk->enable_bit);
- CM_CLKEN_PLL = cval;
+ prcm_write_reg(CM_CLKEN_PLL, cval);
if (clk == &apll96_ck)
cval = (1 << 8);
else if (clk == &apll54_ck)
cval = (1 << 6);
- while (!CM_IDLEST_CKGEN & cval) { /* Wait for lock */
+ while (!prcm_read_reg(CM_IDLEST_CKGEN) & cval) {/* Wait for lock */
++i;
udelay(1);
if (i == 100000)
@@ -125,15 +164,14 @@ static int _omap2_clk_enable(struct clk
clk->name);
return 0;
}
-
- if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
+ if (clk->enable_reg == (void __iomem *)CM_CLKEN_PLL) {
omap2_clk_fixed_enable(clk);
return 0;
}
- regval32 = __raw_readl(clk->enable_reg);
+ regval32 = prcm_read_reg((u32)clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
+ prcm_write_reg((u32)clk->enable_reg, regval32);
return 0;
}
@@ -146,9 +184,9 @@ static void omap2_clk_fixed_disable(stru
if(clk->enable_bit == 0xff) /* let parent off do it */
return;
- cval = CM_CLKEN_PLL;
+ cval = prcm_read_reg(CM_CLKEN_PLL);
cval &= ~(0x3 << clk->enable_bit);
- CM_CLKEN_PLL = cval;
+ prcm_write_reg(CM_CLKEN_PLL, cval);
}
/* Disables clock without considering parent dependencies or use count */
@@ -159,14 +197,14 @@ static void _omap2_clk_disable(struct cl
if (clk->enable_reg == 0)
return;
- if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
+ if (clk->enable_reg == (void __iomem *)CM_CLKEN_PLL) {
omap2_clk_fixed_disable(clk);
return;
}
- regval32 = __raw_readl(clk->enable_reg);
+ regval32 = prcm_read_reg((u32)clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
+ prcm_write_reg((u32)clk->enable_reg, regval32);
}
static int omap2_clk_enable(struct clk *clk)
@@ -210,7 +248,7 @@ static u32 omap2_dpll_round_rate(unsigne
{
u32 high, low;
- if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
+ if ((prcm_read_reg(CM_CLKSEL2_PLL) & 0x3) == 1) { /* DPLL clockout */
high = curr_prcm_set->dpll_speed * 2;
low = curr_prcm_set->dpll_speed;
} else { /* DPLL clockout x 2 */
@@ -251,7 +289,8 @@ static void omap2_clksel_recalc(struct c
fixed = 1;
}
- if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
+ if ((clk == &dss1_fck) &&
+ ((prcm_read_reg(CM_CLKSEL1_CORE) & (0x1f << 8)) == 0)) {
clk->rate = sys_ck.rate;
return;
}
@@ -387,7 +426,7 @@ static u32 omap2_reprogram_sdrc(u32 leve
if (level == PRCM_HALF_SPEED) {
local_irq_save(flags);
- PRCM_VOLTSETUP = 0xffff;
+ prcm_write_reg(PRCM_VOLTSETUP, 0xffff);
omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
slow_dll_ctrl, m_type);
curr_perf_level = PRCM_HALF_SPEED;
@@ -395,7 +434,7 @@ static u32 omap2_reprogram_sdrc(u32 leve
}
if (level == PRCM_FULL_SPEED) {
local_irq_save(flags);
- PRCM_VOLTSETUP = 0xffff;
+ prcm_write_reg(PRCM_VOLTSETUP, 0xffff);
omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
fast_dll_ctrl, m_type);
curr_perf_level = PRCM_FULL_SPEED;
@@ -414,7 +453,7 @@ static int omap2_reprogram_dpll(struct c
local_irq_save(flags);
cur_rate = omap2_get_dpll_rate(&dpll_ck);
- mult = CM_CLKSEL2_PLL & 0x3;
+ mult = prcm_read_reg(CM_CLKSEL2_PLL) & 0x3;
if ((rate == (cur_rate / 2)) && (mult == 2)) {
omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
@@ -425,15 +464,15 @@ static int omap2_reprogram_dpll(struct c
if (valid_rate != rate)
goto dpll_exit;
- if ((CM_CLKSEL2_PLL & 0x3) == 1)
+ if ((prcm_read_reg(CM_CLKSEL2_PLL) & 0x3) == 1)
low = curr_prcm_set->dpll_speed;
else
low = curr_prcm_set->dpll_speed / 2;
- tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
+ tmpset.cm_clksel1_pll = prcm_read_reg(CM_CLKSEL1_PLL);
tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
- tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
+ tmpset.cm_clksel2_pll = prcm_read_reg(CM_CLKSEL2_PLL);
tmpset.cm_clksel2_pll &= ~0x3;
if (rate > low) {
tmpset.cm_clksel2_pll |= 0x2;
@@ -540,11 +579,11 @@ static u32 omap2_get_clksel(u32 *div_sel
switch ((*div_sel & SRC_RATE_SEL_MASK)) {
case CM_MPU_SEL1:
- div_addr = (u32)&CM_CLKSEL_MPU;
+ div_addr = (u32)CM_CLKSEL_MPU;
mask = 0x1f;
break;
case CM_DSP_SEL1:
- div_addr = (u32)&CM_CLKSEL_DSP;
+ div_addr = (u32)CM_CLKSEL_DSP;
if (cpu_is_omap2420()) {
if ((div_off == 0) || (div_off == 8))
mask = 0x1f;
@@ -558,22 +597,22 @@ static u32 omap2_get_clksel(u32 *div_sel
}
break;
case CM_GFX_SEL1:
- div_addr = (u32)&CM_CLKSEL_GFX;
+ div_addr = (u32)CM_CLKSEL_GFX;
if (div_off == 0)
mask = 0x7;
break;
case CM_MODEM_SEL1:
- div_addr = (u32)&CM_CLKSEL_MDM;
+ div_addr = (u32)CM_CLKSEL_MDM;
if (div_off == 0)
mask = 0xf;
break;
case CM_SYSCLKOUT_SEL1:
- div_addr = (u32)&PRCM_CLKOUT_CTRL;
+ div_addr = (u32)PRCM_CLKOUT_CTRL;
if ((div_off == 3) || (div_off = 11))
mask= 0x3;
break;
case CM_CORE_SEL1:
- div_addr = (u32)&CM_CLKSEL1_CORE;
+ div_addr = (u32)CM_CLKSEL1_CORE;
switch (div_off) {
case 0: /* l3 */
case 8: /* dss1 */
@@ -600,7 +639,7 @@ static u32 omap2_get_clksel(u32 *div_sel
return ret;
/* Isolate field */
- reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+ reg_val = prcm_read_reg(div_addr) & (mask << div_off);
/* Normalize back to divider value */
reg_val >>= div_off;
@@ -636,7 +675,6 @@ static int omap2_clk_set_rate(struct clk
{
int ret = -EINVAL;
- void __iomem * reg;
u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
u32 new_div = 0;
@@ -677,17 +715,15 @@ static int omap2_clk_set_rate(struct clk
} else
field_val = new_div;
- reg = (void __iomem *)div_sel;
-
- reg_val = __raw_readl(reg);
+ reg_val = prcm_read_reg(div_sel);
reg_val &= ~(field_mask << div_off);
reg_val |= (field_val << div_off);
- __raw_writel(reg_val, reg);
+ prcm_write_reg(div_sel, reg_val);
clk->rate = clk->parent->rate / field_val;
if (clk->flags & DELAYED_APP)
- __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+ prcm_write_reg(PRCM_CLKCFG_CTRL, 0x01);
ret = 0;
} else if (clk->set_rate != 0)
ret = clk->set_rate(clk, rate);
@@ -707,7 +743,7 @@ static u32 omap2_get_src_field(u32 *type
/* Find target control register.*/
switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
case CM_CORE_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL1_CORE;
+ src_reg_addr = (u32)CM_CLKSEL1_CORE;
if (reg_offset == 13) { /* DSS2_fclk */
mask = 0x1;
if (src_clk == &sys_ck)
@@ -729,7 +765,7 @@ static u32 omap2_get_src_field(u32 *type
}
break;
case CM_CORE_SEL2:
- src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+ src_reg_addr = (u32)CM_CLKSEL2_CORE;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
@@ -739,7 +775,7 @@ static u32 omap2_get_src_field(u32 *type
val = 0x2;
break;
case CM_WKUP_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL_WKUP;
+ src_reg_addr = (u32)CM_CLKSEL_WKUP;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
@@ -749,7 +785,7 @@ static u32 omap2_get_src_field(u32 *type
val = 0x2;
break;
case CM_PLL_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL1_PLL;
+ src_reg_addr = (u32)CM_CLKSEL1_PLL;
mask = 0x1;
if (reg_offset == 0x3) {
if (src_clk == &apll96_ck)
@@ -765,7 +801,7 @@ static u32 omap2_get_src_field(u32 *type
}
break;
case CM_PLL_SEL2:
- src_reg_addr = (u32)&CM_CLKSEL2_PLL;
+ src_reg_addr = (u32)CM_CLKSEL2_PLL;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
@@ -773,7 +809,7 @@ static u32 omap2_get_src_field(u32 *type
val = 0x2;
break;
case CM_SYSCLKOUT_SEL1:
- src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
+ src_reg_addr = (u32)PRCM_CLKOUT_CTRL;
mask = 0x3;
if (src_clk == &dpll_ck)
val = 0;
@@ -797,7 +833,6 @@ static u32 omap2_get_src_field(u32 *type
static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
{
- void __iomem * reg;
u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
int ret = -EINVAL;
@@ -814,18 +849,16 @@ static int omap2_clk_set_parent(struct c
field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
&field_mask);
- reg = (void __iomem *)src_sel;
-
if (clk->usecount > 0)
_omap2_clk_disable(clk);
/* Set new source value (previous dividers if any in effect) */
- reg_val = __raw_readl(reg) & ~(field_mask << src_off);
+ reg_val = prcm_read_reg(src_sel) & ~(field_mask << src_off);
reg_val |= (field_val << src_off);
- __raw_writel(reg_val, reg);
+ prcm_write_reg(src_sel, reg_val);
if (clk->flags & DELAYED_APP)
- __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+ prcm_write_reg(PRCM_CLKCFG_CTRL, 0x01);
if (clk->usecount > 0)
_omap2_clk_enable(clk);
@@ -908,17 +941,17 @@ static int omap2_select_table_rate(struc
done_rate = PRCM_HALF_SPEED;
/* MPU divider */
- CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+ prcm_write_reg(CM_CLKSEL_MPU, prcm->cm_clksel_mpu);
/* dsp + iva1 div(2420), iva2.1(2430) */
- CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+ prcm_write_reg(CM_CLKSEL_DSP, prcm->cm_clksel_dsp);
- CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+ prcm_write_reg(CM_CLKSEL_GFX, prcm->cm_clksel_gfx);
/* Major subsystem dividers */
- CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
+ prcm_write_reg(CM_CLKSEL1_CORE, prcm->cm_clksel1_core);
if (cpu_is_omap2430())
- CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+ prcm_write_reg(CM_CLKSEL_MDM, prcm->cm_clksel_mdm);
/* x2 to enter init_mem */
omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
@@ -952,7 +985,7 @@ static void __init omap2_get_crystal_rat
{
u32 div, aplls, sclk = 13000000;
- aplls = CM_CLKSEL1_PLL;
+ aplls = prcm_read_reg(CM_CLKSEL1_PLL);
aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
aplls >>= 23; /* Isolate field, 0,2,3 */
@@ -963,7 +996,7 @@ static void __init omap2_get_crystal_rat
else if (aplls == 3)
sclk = 12000000;
- div = PRCM_CLKSRC_CTRL;
+ div = prcm_read_reg(PRCM_CLKSRC_CTRL);
div &= ((1 << 7) | (1 << 6));
div >>= sys->rate_offset;
@@ -982,7 +1015,7 @@ static void __init omap2_disable_unused_
ck->enable_reg == 0)
continue;
- regval32 = __raw_readl(ck->enable_reg);
+ regval32 = prcm_read_reg(ck->enable_reg);
if ((regval32 & (1 << ck->enable_bit)) == 0)
continue;
@@ -1069,3 +1102,19 @@ int __init omap2_clk_init(void)
return 0;
}
+
+int __init omap2_prcm_init(void)
+{
+ u32 rev;
+
+ if (cpu_is_omap2420())
+ prcm_vbase = (void __iomem *)io_p2v(OMAP242X_PRCM_BASE);
+
+ rev = prcm_read_reg(PRCM_REVISION);
+
+ printk(KERN_INFO "OMAP PRCM hardware version %d.%d\n",
+ (rev >> 4) & 0x0f, rev & 0x0f);
+
+ return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2781dfb..4f53443 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -601,7 +601,7 @@ static struct clk apll96_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0x2,
.recalc = &omap2_propagate_rate,
};
@@ -612,7 +612,7 @@ static struct clk apll54_ck = {
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0x6,
.recalc = &omap2_propagate_rate,
};
@@ -627,7 +627,7 @@ static struct clk func_54m_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 5,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
.recalc = &omap2_propagate_rate,
};
@@ -654,7 +654,7 @@ static struct clk func_96m_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
.recalc = &omap2_propagate_rate,
};
@@ -666,7 +666,7 @@ static struct clk func_48m_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 3,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
.recalc = &omap2_propagate_rate,
};
@@ -678,7 +678,7 @@ static struct clk func_12m_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
.recalc = &omap2_propagate_rate,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
};
@@ -697,7 +697,7 @@ static struct clk sys_clkout = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 0,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
+ .enable_reg = (void __iomem *)PRCM_CLKOUT_CTRL,
.enable_bit = 7,
.rate_offset = 3,
.recalc = &omap2_clksel_recalc,
@@ -711,7 +711,7 @@ static struct clk sys_clkout2 = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 8,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
+ .enable_reg = (void __iomem *)PRCM_CLKOUT_CTRL,
.enable_bit = 15,
.rate_offset = 11,
.recalc = &omap2_clksel_recalc,
@@ -721,7 +721,7 @@ static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
+ .enable_reg = (void __iomem *)PRCM_CLKEMUL_CTRL,
.enable_bit = 0,
.recalc = &omap2_propagate_rate,
@@ -760,7 +760,7 @@ static struct clk iva2_1_fck = {
DELAYED_APP | RATE_PROPAGATES |
CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
@@ -786,7 +786,7 @@ static struct clk dsp_fck = {
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
@@ -797,7 +797,7 @@ static struct clk dsp_ick = {
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 5,
- .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_DSP,
.enable_bit = 1, /* for ipi */
.recalc = &omap2_clksel_recalc,
};
@@ -808,7 +808,7 @@ static struct clk iva1_ifck = {
.flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
.rate_offset= 8,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 10,
.recalc = &omap2_clksel_recalc,
};
@@ -818,7 +818,7 @@ static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 8,
.recalc = &omap2_clksel_recalc,
};
@@ -859,7 +859,7 @@ static struct clk usb_l4_ick = { /* FS-U
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
CONFIG_PARTICIPANT,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 0,
.rate_offset = 25,
.recalc = &omap2_clksel_recalc,
@@ -878,7 +878,7 @@ static struct clk ssi_ssr_sst_fck = {
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE, /* bit 1 */
.enable_bit = 1,
.rate_offset = 20,
.recalc = &omap2_clksel_recalc,
@@ -900,7 +900,7 @@ static struct clk gfx_3d_fck = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
+ .enable_reg = (void __iomem *)CM_FCLKEN_GFX,
.enable_bit = 2,
.rate_offset= 0,
.recalc = &omap2_clksel_recalc,
@@ -911,7 +911,7 @@ static struct clk gfx_2d_fck = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
+ .enable_reg = (void __iomem *)CM_FCLKEN_GFX,
.enable_bit = 1,
.rate_offset= 0,
.recalc = &omap2_clksel_recalc,
@@ -922,7 +922,7 @@ static struct clk gfx_ick = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
+ .enable_reg = (void __iomem *)CM_ICLKEN_GFX, /* bit 0 */
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -939,7 +939,7 @@ static struct clk mdm_ick = { /* used b
.flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
+ .enable_reg = (void __iomem *)CM_ICLKEN_MDM,
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
@@ -949,7 +949,7 @@ static struct clk mdm_osc_ck = {
.rate = 26000000,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
+ .enable_reg = (void __iomem *)CM_FCLKEN_MDM,
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -975,7 +975,7 @@ static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE, /* bit 1 */
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -992,7 +992,7 @@ static struct clk dss_ick = { /* Enable
.name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1002,7 +1002,7 @@ static struct clk dss1_fck = {
.parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 0,
.rate_offset = 8,
.src_offset = 8,
@@ -1014,7 +1014,7 @@ static struct clk dss2_fck = { /* Alt c
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 1,
.src_offset = 13,
.recalc = &omap2_followparent_recalc,
@@ -1026,7 +1026,7 @@ static struct clk dss_54m_fck = { /* Alt
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 2,
.recalc = &omap2_propagate_rate,
};
@@ -1041,7 +1041,7 @@ static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP, /* Bit0 */
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1051,7 +1051,7 @@ static struct clk gpt1_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_WKUP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
+ .enable_reg = (void __iomem *)CM_FCLKEN_WKUP, /* Bit0 */
.enable_bit = 0,
.src_offset = 0,
.recalc = &omap2_followparent_recalc,
@@ -1061,7 +1061,7 @@ static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit4 */
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1071,7 +1071,7 @@ static struct clk gpt2_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 4,
.src_offset = 2,
.recalc = &omap2_followparent_recalc,
@@ -1081,7 +1081,7 @@ static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit5 */
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1091,7 +1091,7 @@ static struct clk gpt3_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 5,
.src_offset = 4,
.recalc = &omap2_followparent_recalc,
@@ -1101,7 +1101,7 @@ static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit6 */
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
@@ -1111,7 +1111,7 @@ static struct clk gpt4_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 6,
.src_offset = 6,
.recalc = &omap2_followparent_recalc,
@@ -1121,7 +1121,7 @@ static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit7 */
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
@@ -1131,7 +1131,7 @@ static struct clk gpt5_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 7,
.src_offset = 8,
.recalc = &omap2_followparent_recalc,
@@ -1142,7 +1142,7 @@ static struct clk gpt6_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 8,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit8 */
.recalc = &omap2_followparent_recalc,
};
@@ -1151,7 +1151,7 @@ static struct clk gpt6_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 8,
.src_offset = 10,
.recalc = &omap2_followparent_recalc,
@@ -1161,7 +1161,7 @@ static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit9 */
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
@@ -1171,7 +1171,7 @@ static struct clk gpt7_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 9,
.src_offset = 12,
.recalc = &omap2_followparent_recalc,
@@ -1181,7 +1181,7 @@ static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit10 */
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
@@ -1191,7 +1191,7 @@ static struct clk gpt8_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 10,
.src_offset = 14,
.recalc = &omap2_followparent_recalc,
@@ -1201,7 +1201,7 @@ static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 11,
.recalc = &omap2_followparent_recalc,
};
@@ -1211,7 +1211,7 @@ static struct clk gpt9_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 11,
.src_offset = 16,
.recalc = &omap2_followparent_recalc,
@@ -1221,7 +1221,7 @@ static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 12,
.recalc = &omap2_followparent_recalc,
};
@@ -1231,7 +1231,7 @@ static struct clk gpt10_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 12,
.src_offset = 18,
.recalc = &omap2_followparent_recalc,
@@ -1241,7 +1241,7 @@ static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 13,
.recalc = &omap2_followparent_recalc,
};
@@ -1251,7 +1251,7 @@ static struct clk gpt11_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 13,
.src_offset = 20,
.recalc = &omap2_followparent_recalc,
@@ -1261,7 +1261,7 @@ static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit14 */
.enable_bit = 14,
.recalc = &omap2_followparent_recalc,
};
@@ -1271,7 +1271,7 @@ static struct clk gpt12_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 14,
.src_offset = 22,
.recalc = &omap2_followparent_recalc,
@@ -1282,7 +1282,7 @@ static struct clk mcbsp1_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit16 */
.recalc = &omap2_followparent_recalc,
};
@@ -1291,7 +1291,7 @@ static struct clk mcbsp1_fck = {
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.recalc = &omap2_followparent_recalc,
};
@@ -1300,7 +1300,7 @@ static struct clk mcbsp2_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.recalc = &omap2_followparent_recalc,
};
@@ -1309,7 +1309,7 @@ static struct clk mcbsp2_fck = {
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.recalc = &omap2_followparent_recalc,
};
@@ -1317,7 +1317,7 @@ static struct clk mcbsp3_ick = {
.name = "mcbsp3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1326,7 +1326,7 @@ static struct clk mcbsp3_fck = {
.name = "mcbsp3_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1335,7 +1335,7 @@ static struct clk mcbsp4_ick = {
.name = "mcbsp4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1344,7 +1344,7 @@ static struct clk mcbsp4_fck = {
.name = "mcbsp4_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1353,7 +1353,7 @@ static struct clk mcbsp5_ick = {
.name = "mcbsp5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1362,7 +1362,7 @@ static struct clk mcbsp5_fck = {
.name = "mcbsp5_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1371,7 +1371,7 @@ static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
@@ -1380,7 +1380,7 @@ static struct clk mcspi1_fck = {
.name = "mcspi1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
@@ -1389,7 +1389,7 @@ static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 18,
.recalc = &omap2_followparent_recalc,
};
@@ -1398,7 +1398,7 @@ static struct clk mcspi2_fck = {
.name = "mcspi2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 18,
.recalc = &omap2_followparent_recalc,
};
@@ -1407,7 +1407,7 @@ static struct clk mcspi3_ick = {
.name = "mcspi3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
@@ -1416,7 +1416,7 @@ static struct clk mcspi3_fck = {
.name = "mcspi3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
@@ -1425,7 +1425,7 @@ static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 21,
.recalc = &omap2_followparent_recalc,
};
@@ -1434,7 +1434,7 @@ static struct clk uart1_fck = {
.name = "uart1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 21,
.recalc = &omap2_followparent_recalc,
};
@@ -1443,7 +1443,7 @@ static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 22,
.recalc = &omap2_followparent_recalc,
};
@@ -1452,7 +1452,7 @@ static struct clk uart2_fck = {
.name = "uart2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 22,
.recalc = &omap2_followparent_recalc,
};
@@ -1461,7 +1461,7 @@ static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1470,7 +1470,7 @@ static struct clk uart3_fck = {
.name = "uart3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1479,7 +1479,7 @@ static struct clk gpios_ick = {
.name = "gpios_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1488,7 +1488,7 @@ static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_WKUP,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1497,7 +1497,7 @@ static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1506,7 +1506,7 @@ static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_WKUP,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1515,7 +1515,7 @@ static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -1523,7 +1523,7 @@ static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1531,7 +1531,7 @@ static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1539,7 +1539,7 @@ static struct clk icr_ick = {
.name = "icr_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
@@ -1548,7 +1548,7 @@ static struct clk cam_ick = {
.name = "cam_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 31,
.recalc = &omap2_followparent_recalc,
};
@@ -1557,7 +1557,7 @@ static struct clk cam_fck = {
.name = "cam_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 31,
.recalc = &omap2_followparent_recalc,
};
@@ -1566,7 +1566,7 @@ static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 30,
.recalc = &omap2_followparent_recalc,
};
@@ -1575,7 +1575,7 @@ static struct clk wdt4_ick = {
.name = "wdt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 29,
.recalc = &omap2_followparent_recalc,
};
@@ -1584,7 +1584,7 @@ static struct clk wdt4_fck = {
.name = "wdt4_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 29,
.recalc = &omap2_followparent_recalc,
};
@@ -1593,7 +1593,7 @@ static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 28,
.recalc = &omap2_followparent_recalc,
};
@@ -1602,7 +1602,7 @@ static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 28,
.recalc = &omap2_followparent_recalc,
};
@@ -1611,7 +1611,7 @@ static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 27,
.recalc = &omap2_followparent_recalc,
};
@@ -1620,7 +1620,7 @@ static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 27,
.recalc = &omap2_followparent_recalc,
};
@@ -1629,7 +1629,7 @@ static struct clk mmc_ick = {
.name = "mmc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 26,
.recalc = &omap2_followparent_recalc,
};
@@ -1638,7 +1638,7 @@ static struct clk mmc_fck = {
.name = "mmc_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 26,
.recalc = &omap2_followparent_recalc,
};
@@ -1647,7 +1647,7 @@ static struct clk fac_ick = {
.name = "fac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 25,
.recalc = &omap2_followparent_recalc,
};
@@ -1656,7 +1656,7 @@ static struct clk fac_fck = {
.name = "fac_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 25,
.recalc = &omap2_followparent_recalc,
};
@@ -1665,7 +1665,7 @@ static struct clk eac_ick = {
.name = "eac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 24,
.recalc = &omap2_followparent_recalc,
};
@@ -1674,7 +1674,7 @@ static struct clk eac_fck = {
.name = "eac_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 24,
.recalc = &omap2_followparent_recalc,
};
@@ -1683,7 +1683,7 @@ static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 23,
.recalc = &omap2_followparent_recalc,
};
@@ -1692,7 +1692,7 @@ static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 23,
.recalc = &omap2_followparent_recalc,
};
@@ -1702,7 +1702,7 @@ static struct clk i2c2_ick = {
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
@@ -1712,7 +1712,7 @@ static struct clk i2c2_fck = {
.id = 2,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
@@ -1721,7 +1721,7 @@ static struct clk i2chs2_fck = {
.name = "i2chs2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
@@ -1731,7 +1731,7 @@ static struct clk i2c1_ick = {
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
@@ -1741,7 +1741,7 @@ static struct clk i2c1_fck = {
.id = 1,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
@@ -1750,7 +1750,7 @@ static struct clk i2chs1_fck = {
.name = "i2chs1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
@@ -1759,7 +1759,7 @@ static struct clk vlynq_ick = {
.name = "vlynq_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1768,7 +1768,7 @@ static struct clk vlynq_fck = {
.name = "vlynq_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 3,
.src_offset = 15,
.recalc = &omap2_followparent_recalc,
@@ -1778,7 +1778,7 @@ static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN3_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1787,7 +1787,7 @@ static struct clk des_ick = {
.name = "des_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1796,7 +1796,7 @@ static struct clk sha_ick = {
.name = "sha_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -1805,7 +1805,7 @@ static struct clk rng_ick = {
.name = "rng_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1814,7 +1814,7 @@ static struct clk aes_ick = {
.name = "aes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1823,7 +1823,7 @@ static struct clk pka_ick = {
.name = "pka_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1832,7 +1832,7 @@ static struct clk usb_fck = {
.name = "usb_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1841,7 +1841,7 @@ static struct clk usbhs_ick = {
.name = "usbhs_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
@@ -1850,7 +1850,7 @@ static struct clk mmchs1_ick = {
.name = "mmchs1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
@@ -1859,7 +1859,7 @@ static struct clk mmchs1_fck = {
.name = "mmchs1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
@@ -1868,7 +1868,7 @@ static struct clk mmchs2_ick = {
.name = "mmchs2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 8,
.recalc = &omap2_followparent_recalc,
};
@@ -1877,7 +1877,7 @@ static struct clk mmchs2_fck = {
.name = "mmchs2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 8,
.recalc = &omap2_followparent_recalc,
};
@@ -1886,7 +1886,7 @@ static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
@@ -1895,7 +1895,7 @@ static struct clk gpio5_fck = {
.name = "gpio5_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
@@ -1904,7 +1904,7 @@ static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 11,
.recalc = &omap2_followparent_recalc,
};
@@ -1913,7 +1913,7 @@ static struct clk mmchsdb1_fck = {
.name = "mmchsdb1_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 16,
.recalc = &omap2_followparent_recalc,
};
@@ -1922,7 +1922,7 @@ static struct clk mmchsdb2_fck = {
.name = "mmchsdb2_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 68456b7..aba8856 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -67,6 +67,7 @@ void __init omap2_map_common_io(void)
void __init omap2_init_common_hw(void)
{
omap2_mux_init();
+ omap2_prcm_init();
omap2_clk_init();
gpmc_init();
}
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
index db63dd2..5ca5d3e 100644
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ b/arch/arm/mach-omap2/prcm-regs.h
@@ -29,148 +29,154 @@ #define PRCM_FULL_SPEED 2
#ifndef __ASSEMBLER__
-#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
-
-#define PRCM_REVISION PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL PRCM_REG32(0x050)
-#define PRCM_VOLTST PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP PRCM_REG32(0x094)
-#define PRCM_POLCTRL PRCM_REG32(0x098)
+#define PRCM_REVISION 0x000
+#define PRCM_SYSCONFIG 0x010
+#define PRCM_IRQSTATUS_MPU 0x018
+#define PRCM_IRQENABLE_MPU 0x01C
+#define PRCM_VOLTCTRL 0x050
+#define PRCM_VOLTST 0x054
+#define PRCM_CLKSRC_CTRL 0x060
+#define PRCM_CLKOUT_CTRL 0x070
+#define PRCM_CLKEMUL_CTRL 0x078
+#define PRCM_CLKCFG_CTRL 0x080
+#define PRCM_CLKCFG_STATUS 0x084
+#define PRCM_VOLTSETUP 0x090
+#define PRCM_CLKSSETUP 0x094
+#define PRCM_POLCTRL 0x098
/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
+#define GENERAL_PURPOSE1 0x0B0
+#define GENERAL_PURPOSE2 0x0B4
+#define GENERAL_PURPOSE3 0x0B8
+#define GENERAL_PURPOSE4 0x0BC
+#define GENERAL_PURPOSE5 0x0C0
+#define GENERAL_PURPOSE6 0x0C4
+#define GENERAL_PURPOSE7 0x0C8
+#define GENERAL_PURPOSE8 0x0CC
+#define GENERAL_PURPOSE9 0x0D0
+#define GENERAL_PURPOSE10 0x0D4
+#define GENERAL_PURPOSE11 0x0D8
+#define GENERAL_PURPOSE12 0x0DC
+#define GENERAL_PURPOSE13 0x0E0
+#define GENERAL_PURPOSE14 0x0E4
+#define GENERAL_PURPOSE15 0x0E8
+#define GENERAL_PURPOSE16 0x0EC
+#define GENERAL_PURPOSE17 0x0F0
+#define GENERAL_PURPOSE18 0x0F4
+#define GENERAL_PURPOSE19 0x0F8
+#define GENERAL_PURPOSE20 0x0FC
/* MPU */
-#define CM_CLKSEL_MPU PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
-#define RM_RSTST_MPU PRCM_REG32(0x158)
-#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
+#define CM_CLKSEL_MPU 0x140
+#define CM_CLKSTCTRL_MPU 0x148
+#define RM_RSTST_MPU 0x158
+#define PM_WKDEP_MPU 0x1C8
+#define PM_EVGENCTRL_MPU 0x1D4
+#define PM_EVEGENONTIM_MPU 0x1D8
+#define PM_EVEGENOFFTIM_MPU 0x1DC
+#define PM_PWSTCTRL_MPU 0x1E0
+#define PM_PWSTST_MPU 0x1E4
/* CORE */
-#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
-#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
+#define CM_FCLKEN1_CORE 0x200
+#define CM_FCLKEN2_CORE 0x204
+#define CM_FCLKEN3_CORE 0x208
+#define CM_ICLKEN1_CORE 0x210
+#define CM_ICLKEN2_CORE 0x214
+#define CM_ICLKEN3_CORE 0x218
+#define CM_ICLKEN4_CORE 0x21C
+#define CM_IDLEST1_CORE 0x220
+#define CM_IDLEST2_CORE 0x224
+#define CM_IDLEST3_CORE 0x228
+#define CM_IDLEST4_CORE 0x22C
+#define CM_AUTOIDLE1_CORE 0x230
+#define CM_AUTOIDLE2_CORE 0x234
+#define CM_AUTOIDLE3_CORE 0x238
+#define CM_AUTOIDLE4_CORE 0x23C
+#define CM_CLKSEL1_CORE 0x240
+#define CM_CLKSEL2_CORE 0x244
+#define CM_CLKSTCTRL_CORE 0x248
+#define PM_WKEN1_CORE 0x2A0
+#define PM_WKEN2_CORE 0x2A4
+#define PM_WKST1_CORE 0x2B0
+#define PM_WKST2_CORE 0x2B4
+#define PM_WKDEP_CORE 0x2C8
+#define PM_PWSTCTRL_CORE 0x2E0
+#define PM_PWSTST_CORE 0x2E4
/* GFX */
-#define CM_FCLKEN_GFX PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX PRCM_REG32(0x310)
-#define CM_IDLEST_GFX PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
-#define RM_RSTST_GFX PRCM_REG32(0x358)
-#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
+#define CM_FCLKEN_GFX 0x300
+#define CM_ICLKEN_GFX 0x310
+#define CM_IDLEST_GFX 0x320
+#define CM_CLKSEL_GFX 0x340
+#define CM_CLKSTCTRL_GFX 0x348
+#define RM_RSTCTRL_GFX 0x350
+#define RM_RSTST_GFX 0x358
+#define PM_WKDEP_GFX 0x3C8
+#define PM_PWSTCTRL_GFX 0x3E0
+#define PM_PWSTST_GFX 0x3E4
/* WAKE-UP */
-#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
-#define RM_RSTST_WKUP PRCM_REG32(0x458)
-#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP PRCM_REG32(0x4B0)
+#define CM_FCLKEN_WKUP 0x400
+#define CM_ICLKEN_WKUP 0x410
+#define CM_IDLEST_WKUP 0x420
+#define CM_AUTOIDLE_WKUP 0x430
+#define CM_CLKSEL_WKUP 0x440
+#define RM_RSTCTRL_WKUP 0x450
+#define RM_RST_GS (1 << 1)
+#define RM_RST_DPLL (1 << 2)
+#define RM_RSTTIME_WKUP 0x454
+#define RM_RSTST_WKUP 0x458
+#define RM_GLOBAL_COLD_RST (1 << 0)
+#define RM_GLOBAL_WMPU_RST (1 << 1)
+#define RM_SECU_VIOL_RST (1 << 3)
+#define RM_MPU_VIOL_RST (1 << 4)
+#define RM_SECU_WD_RST (1 << 5)
+#define RM_EXTWMPU_RST (1 << 6)
+#define PM_WKEN_WKUP 0x4A0
+#define PM_WKST_WKUP 0x4B0
/* CLOCKS */
-#define CM_CLKEN_PLL PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
+#define CM_CLKEN_PLL 0x500
+#define CM_IDLEST_CKGEN 0x520
+#define CM_AUTOIDLE_PLL 0x530
+#define CM_CLKSEL1_PLL 0x540
+#define CM_CLKSEL2_PLL 0x544
/* DSP */
-#define CM_FCLKEN_DSP PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP PRCM_REG32(0x810)
-#define CM_IDLEST_DSP PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
-#define RM_RSTST_DSP PRCM_REG32(0x858)
-#define PM_WKEN_DSP PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
+#define CM_FCLKEN_DSP 0x800
+#define CM_ICLKEN_DSP 0x810
+#define CM_IDLEST_DSP 0x820
+#define CM_AUTOIDLE_DSP 0x830
+#define CM_CLKSEL_DSP 0x840
+#define CM_CLKSTCTRL_DSP 0x848
+#define RM_RSTCTRL_DSP 0x850
+#define RM_RSTST_DSP 0x858
+#define PM_WKEN_DSP 0x8A0
+#define PM_WKDEP_DSP 0x8C8
+#define PM_PWSTCTRL_DSP 0x8E0
+#define PM_PWSTST_DSP 0x8E4
+#define PRCM_IRQSTATUS_DSP 0x8F0
+#define PRCM_IRQENABLE_DSP 0x8F4
/* IVA */
-#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
+#define PRCM_IRQSTATUS_IVA 0x8F8
+#define PRCM_IRQENABLE_IVA 0x8FC
/* Modem on 2430 */
-#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM PRCM_REG32(0xC20)
-#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
-#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
-#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
-#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
-#define RM_RSTST_MDM PRCM_REG32(0xC58)
-#define PM_WKEN_MDM PRCM_REG32(0xCA0)
-#define PM_WKST_MDM PRCM_REG32(0xCB0)
-#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
-#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
-#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
+#define CM_FCLKEN_MDM 0xC00
+#define CM_ICLKEN_MDM 0xC10
+#define CM_IDLEST_MDM 0xC20
+#define CM_AUTOIDLE_MDM 0xC30
+#define CM_CLKSEL_MDM 0xC40
+#define CM_CLKSTCTRL_MDM 0xC48
+#define RM_RSTCTRL_MDM 0xC50
+#define RM_RSTST_MDM 0xC58
+#define PM_WKEN_MDM 0xCA0
+#define PM_WKST_MDM 0xCB0
+#define PM_WKDEP_MDM 0xCC8
+#define PM_PWSTCTRL_MDM 0xCE0
+#define PM_PWSTST_MDM 0xCE4
#define OMAP24XX_L4_IO_BASE 0x48000000
@@ -425,6 +431,15 @@ #define GPMC_CONFIG5_3 GPMC_REG32(0x100
#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
+/* GPMC CS5 */
+#define GPMC_CONFIG1_5 GPMC_REG32(0x150)
+#define GPMC_CONFIG2_5 GPMC_REG32(0x154)
+#define GPMC_CONFIG3_5 GPMC_REG32(0x158)
+#define GPMC_CONFIG4_5 GPMC_REG32(0x15C)
+#define GPMC_CONFIG5_5 GPMC_REG32(0x160)
+#define GPMC_CONFIG6_5 GPMC_REG32(0x164)
+#define GPMC_CONFIG7_5 GPMC_REG32(0x168)
+
/* DSS */
#define DSS_CONTROL DISP_REG32(0x040)
#define DISPC_CONTROL DISP_REG32(0x440)
@@ -468,8 +483,3 @@ #define MMCHS2_SYSCONFIG __REG32(0x480b4
#endif /* __ASSEMBLER__ */
#endif
-
-
-
-
-
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
deleted file mode 100644
index 8893479..0000000
--- a/arch/arm/mach-omap2/prcm.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/prcm.c
- *
- * OMAP 24xx Power Reset and Clock Management (PRCM) functions
- *
- * Copyright (C) 2005 Nokia Corporation
- *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
- *
- * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include "prcm-regs.h"
-
-u32 omap_prcm_get_reset_sources(void)
-{
- return RM_RSTST_WKUP & 0x7f;
-}
-EXPORT_SYMBOL(omap_prcm_get_reset_sources);
-
-/* Resets clock rates and reboots the system. Only called from system.h */
-void omap_prcm_arch_reset(char mode)
-{
- u32 rate;
- struct clk *vclk, *sclk;
-
- vclk = clk_get(NULL, "virt_prcm_set");
- sclk = clk_get(NULL, "sys_ck");
- rate = clk_get_rate(sclk);
- clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
- RM_RSTCTRL_WKUP |= 2;
-}
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index e559bb0..448c0a1 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -32,12 +32,12 @@ #include "prcm-regs.h"
#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
-#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
-#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
+#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x544)
+#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x050)
+#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x080)
+#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x500)
+#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x520)
+#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x540)
#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP242X_SDRC_BASE + 0x060)
#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP242X_SDRC_BASE + 0x0a4)
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index fa43502..edb2134 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -17,7 +17,7 @@ #define OMAP24XX_IVA_INTC_BASE 0x4000000
#define IRQ_SIR_IRQ 0x0040
#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
-#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
+#define OMAP242X_PRCM_BASE (L4_24XX_BASE + 0x8000)
#define OMAP242X_SDRC_BASE (L3_24XX_BASE + 0x9000)
#endif /* __ASM_ARCH_OMAP24XX_H */
--
1.3.3
[-- Attachment #3: Type: text/plain, Size: 0 bytes --]
next reply other threads:[~2006-06-14 11:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-06-14 11:37 Komal Shah [this message]
2006-08-11 11:12 ` [PATCH 2/2] ARM: OMAP: Use read/write_reg functions for PRCM Tony Lindgren
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