* How to port the musb to a new processor?
@ 2007-08-29 9:27 Bryan Wu
2007-08-29 17:37 ` David Brownell
0 siblings, 1 reply; 3+ messages in thread
From: Bryan Wu @ 2007-08-29 9:27 UTC (permalink / raw)
To: Tony Lindgren, David Brownell, linux-omap-open-source
Hi Tony and David,
There days, I am trying to enable musb stack in my Blackfin Linux tree.
After comparing the musb_regs.h with the BF54x USB register layout, I
found it is not very easy to use the musb_regs.h for the porting.
1. Offset of the musb_regs.h is different with the BF54x
2. Some musb_regs are 8-bit wide, while on BF54x most of them are 16-bit
or 32-bit.
3. Some register not in BF54x and some BF54x register is not in
musb_reg.h
But most BF54x USB register can found one in musb_regs.h
I just wondering how to abstract this definition to BF54x hardware as
Davinci or OMAP does.
Thanks a lot
Best Regards,
- Bryan Wu
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: How to port the musb to a new processor?
2007-08-29 9:27 How to port the musb to a new processor? Bryan Wu
@ 2007-08-29 17:37 ` David Brownell
2007-08-30 9:52 ` Bryan Wu
0 siblings, 1 reply; 3+ messages in thread
From: David Brownell @ 2007-08-29 17:37 UTC (permalink / raw)
To: bryan.wu; +Cc: linux-omap-open-source
On Wednesday 29 August 2007, Bryan Wu wrote:
> Hi Tony and David,
>
> There days, I am trying to enable musb stack in my Blackfin Linux tree.
> After comparing the musb_regs.h with the BF54x USB register layout, I
> found it is not very easy to use the musb_regs.h for the porting.
>
> 1. Offset of the musb_regs.h is different with the BF54x
None of these platforms put the Mentor registers at offset zero.
Usually offset zero has vendor-specific registers.
Chip-specific init is expected to update musb->mregs; it starts
out matching musb->ctrl_base. All the musb_regs.h offsets are
against musb->mregs.
> 2. Some musb_regs are 8-bit wide, while on BF54x most of them are 16-bit
> or 32-bit.
The Mentor docs define only 8 bit and 16 bit registers, except for
an optional vctrl/vstatus PHY register "up to 32 bits" ... that's
not currently used in the driver.
IMO the choice of only 8 and 16 bit register widths was a design
goof on Mentor's part, especially after seeing the hassles from
putting the tusb6010 on an external 16-bit-only data bus. But I'd
have thought changing those would be kind of "out of scope" for any
vendor integrating that IP into their own sillcion, and leaving an
option to switch to updated RTL...
Vendor specific registers can be 32 bits (or 64 bits!) very easily,
and that shouldn't affect the Mentor-related bits of the driver.
> 3. Some register not in BF54x and some BF54x register is not in
> musb_reg.h
"Not in BF54x" ... could you elaborate? The header lists
some registers added by the 1.400 RTL, but those aren't used
by the driver. (Though it would be nice to rely on getting
more of the configuration data from register reads, like how
big is that FIFO RAM...)
> But most BF54x USB register can found one in musb_regs.h
>
> I just wondering how to abstract this definition to BF54x hardware as
> Davinci or OMAP does.
The expectation is that the Mentor registers are a block that
doesn't change ... wrapped on either side by vendor-added
registers to handle things like saner IRQs and DMA; PHY; plus
power/reset/clock management that's not addressed by the public
registers from Mentor; and so on.
If that's how Analog did it, there should be no worries. The
core of the driver (and some vendor-specific parts) will use
the block of Mentor registers, offsetting musb->mregs ... while
vendor/platform glue will use the others, using a vendor header
file to define offsets from musb->ctrl_base to other registers.
- Dave
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: How to port the musb to a new processor?
2007-08-29 17:37 ` David Brownell
@ 2007-08-30 9:52 ` Bryan Wu
0 siblings, 0 replies; 3+ messages in thread
From: Bryan Wu @ 2007-08-30 9:52 UTC (permalink / raw)
To: David Brownell; +Cc: linux-omap-open-source
On Wed, 2007-08-29 at 10:37 -0700, David Brownell wrote:
> On Wednesday 29 August 2007, Bryan Wu wrote:
> > Hi Tony and David,
> >
> > There days, I am trying to enable musb stack in my Blackfin Linux tree.
> > After comparing the musb_regs.h with the BF54x USB register layout, I
> > found it is not very easy to use the musb_regs.h for the porting.
> >
> > 1. Offset of the musb_regs.h is different with the BF54x
>
> None of these platforms put the Mentor registers at offset zero.
> Usually offset zero has vendor-specific registers.
>
Oh, my didn't describe it clearly. The USB OTG registers in BF54x is
layout is different with musb_regs.h, for example:
USB Control Registers
Name Width Address Index Function
USB_FADDR 16 0xFFC03C00 n/a Function address register
USB_POWER 16 0xFFC03C04 n/a Power management register
USB_INTRTX 16 0xFFC03C08 n/a Interrupt register for endpoint 0 and Tx endpoint 1 to 7
USB_INTRRX 16 0xFFC03C0C n/a Interrupt register for Rx endpoints 1 to 7
USB_INTRTXE 16 0xFFC03C10 n/a Interrupt enable register for IntrTx
USB_INTRRXE 16 0xFFC03C14 n/a Interrupt enable register for IntrRx
USB_INTRUSB 16 0xFFC03C18 n/a Interrupt register for common USB interrupts
USB_INTRUSBE 16 0xFFC03C1C n/a Interrupt enable register for IntrUSB
USB_FRAME 16 0xFFC03C20 n/a USB frame number
USB_INDEX 16 0xFFC03C24 n/a Index register for selecting the indexed endpoint registers
USB_TESTMODE 16 0xFFC03C28 n/a Enabled USB 20 test modes (for Analog Devices internal usage only)
USB_GLOBINTR 16 0xFFC03C2C n/a Global Interrupt Mask register and Wakeup Exception Interrupt
USB_GLOBAL_CTL 16 0xFFC03C30 n/a Global Clock Control for the USB controller
The offset of the USB_POWER is 0x04 not 0x01 in musb_regs.h
> Chip-specific init is expected to update musb->mregs; it starts
> out matching musb->ctrl_base. All the musb_regs.h offsets are
> against musb->mregs.
>
>
> > 2. Some musb_regs are 8-bit wide, while on BF54x most of them are 16-bit
> > or 32-bit.
>
> The Mentor docs define only 8 bit and 16 bit registers, except for
> an optional vctrl/vstatus PHY register "up to 32 bits" ... that's
> not currently used in the driver.
>
> IMO the choice of only 8 and 16 bit register widths was a design
> goof on Mentor's part, especially after seeing the hassles from
> putting the tusb6010 on an external 16-bit-only data bus. But I'd
> have thought changing those would be kind of "out of scope" for any
> vendor integrating that IP into their own sillcion, and leaving an
> option to switch to updated RTL...
>
> Vendor specific registers can be 32 bits (or 64 bits!) very easily,
> and that shouldn't affect the Mentor-related bits of the driver.
>
>
In the above example, although only 8 bit in 0xFFC03C00 (USB_FADDR) is
meaningful, but the register is 16 bits wide and they are 4bytes
aligned.
> > 3. Some register not in BF54x and some BF54x register is not in
> > musb_reg.h
>
> "Not in BF54x" ... could you elaborate? The header lists
> some registers added by the 1.400 RTL, but those aren't used
> by the driver. (Though it would be nice to rely on getting
> more of the configuration data from register reads, like how
> big is that FIFO RAM...)
>
I don't find following registers in BF54x. (Maybe I missed something)
/* These are always controlled through the INDEX register */
#define MUSB_TXFIFOSZ|__|_______0x62|___/* 8-bit (see masks) */
#define MUSB_RXFIFOSZ|__|_______0x63|___/* 8-bit (see masks) */
#define MUSB_TXFIFOADD|_|_______0x64|___/* 16-bit offset shifted right 3
*/
#define MUSB_RXFIFOADD|_|_______0x66|___/* 16-bit offset shifted right 3
*/
/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
#define MUSB_HWVERS|____|_______0x6C|___/* 8 bit */
#define MUSB_EPINFO|____|_______0x78|___/* 8 bit */
#define MUSB_RAMINFO|___|_______0x79|___/* 8 bit */
/* "bus control"/target registers, for host side multipoint (external
hubs) */
#define MUSB_TXFUNCADDR||_______0x00
#define MUSB_TXHUBADDR|_|_______0x02
#define MUSB_TXHUBPORT|_|_______0x03
#define MUSB_RXFUNCADDR||_______0x04
#define MUSB_RXHUBADDR|_|_______0x06
#define MUSB_RXHUBPORT|_|_______0x07
> > But most BF54x USB register can found one in musb_regs.h
> >
> > I just wondering how to abstract this definition to BF54x hardware as
> > Davinci or OMAP does.
>
> The expectation is that the Mentor registers are a block that
> doesn't change ... wrapped on either side by vendor-added
> registers to handle things like saner IRQs and DMA; PHY; plus
> power/reset/clock management that's not addressed by the public
> registers from Mentor; and so on.
>
Yes, from the registers layout of BF54x, we got some ADI-added
registers
such as USB PHY control registers, USB DMA registers and some
power/reset/clock operation registers.
> If that's how Analog did it, there should be no worries. The
> core of the driver (and some vendor-specific parts) will use
> the block of Mentor registers, offsetting musb->mregs ... while
> vendor/platform glue will use the others, using a vendor header
> file to define offsets from musb->ctrl_base to other registers.
>
My concern is the layout difference. I cannot just simply set
musb->mregs = 0xFFC03C00 and musb_read(musb->mregs+MUSB_POWER) cannot
give right value on BF54x platform.
Thanks a lot for your help, the full USB OTG registers list of BF548 is
as below:
include/asm-blackfin/mach-bf548/defBF548.h
---
/* USB Control Registers */
#define USB_FADDR 0xffc03c00 /* Function address register */
#define USB_POWER 0xffc03c04 /* Power management register */
#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
#define USB_FRAME 0xffc03c20 /* USB frame number */
#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
/* USB Packet Control Registers */
#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* USB Endpoint FIFO Registers */
#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
/* USB OTG Control Registers */
#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
/* USB Phy Control Registers */
#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
/* (APHY_CNTRL is for ADI usage only) */
#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
/* (APHY_CALIB is for ADI usage only) */
#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
/* (PHY_TEST is for ADI usage only) */
#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
/* USB Endpoint 0 Control Registers */
#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
/* USB Endpoint 1 Control Registers */
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
/* USB Endpoint 2 Control Registers */
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
/* USB Endpoint 3 Control Registers */
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
/* USB Endpoint 4 Control Registers */
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
/* USB Endpoint 5 Control Registers */
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
/* USB Endpoint 6 Control Registers */
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
/* USB Endpoint 7 Control Registers */
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */
#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
/* USB Channel 1 Config Registers */
#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
/* USB Channel 2 Config Registers */
#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
/* USB Channel 3 Config Registers */
#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
/* USB Channel 4 Config Registers */
#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
/* USB Channel 5 Config Registers */
#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
/* USB Channel 6 Config Registers */
#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
/* USB Channel 7 Config Registers */
#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
----
Best Regards,
- Bryan Wu
^ permalink raw reply [flat|nested] 3+ messages in thread
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2007-08-29 9:27 How to port the musb to a new processor? Bryan Wu
2007-08-29 17:37 ` David Brownell
2007-08-30 9:52 ` Bryan Wu
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