* [PATCH 0/3] DMA clean-up for multi-boot
@ 2008-04-30 17:13 Tony Lindgren
2008-04-30 17:13 ` [PATCH 1/3] ARM: OMAP: Make DMA channels dynamic " Tony Lindgren
` (3 more replies)
0 siblings, 4 replies; 21+ messages in thread
From: Tony Lindgren @ 2008-04-30 17:13 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Hi all,
Here are three patches to clean DMA code to support multi-boot
better. I have made quick testing on 24xx and 34xx only so far,
and things seem to work.
I will also do more testing, but I would appreciate if people would
give them a quick spin and see if anything breaks. Functionality
should be same as earlier.
I've removed direct DMA register access in few places such as
omap-hw.c, usb-udc.c, and various audio drivers. So especially
those areas should be tested carefully.
Regards,
Tony
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 1/3] ARM: OMAP: Make DMA channels dynamic for multi-boot 2008-04-30 17:13 [PATCH 0/3] DMA clean-up for multi-boot Tony Lindgren @ 2008-04-30 17:13 ` Tony Lindgren 2008-04-30 17:14 ` [PATCH 2/3] ARM: OMAP: Remove __REG access in DMA code Tony Lindgren 2008-04-30 18:00 ` [PATCH 0/3] DMA clean-up for multi-boot Gadiyar, Anand ` (2 subsequent siblings) 3 siblings, 1 reply; 21+ messages in thread From: Tony Lindgren @ 2008-04-30 17:13 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Make DMA channels dynamic for multi-boot Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/plat-omap/dma.c | 62 +++++++++++++++++++++++++------------- include/asm-arm/arch-omap/dma.h | 7 ++-- 2 files changed, 44 insertions(+), 25 deletions(-) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index c00eda5..d0cfe2b 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -72,7 +72,6 @@ struct omap_dma_lch { long flags; }; -#ifndef CONFIG_ARCH_OMAP1 struct dma_link_info { int *linked_dmach_q; int no_of_lchs_linked; @@ -86,7 +85,9 @@ struct dma_link_info { }; -static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT]; +static struct dma_link_info *dma_linked_lch; + +#ifndef CONFIG_ARCH_OMAP1 /* Chain handling macros */ #define OMAP_DMA_CHAIN_QINIT(chain_id) \ @@ -119,12 +120,14 @@ static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT]; dma_linked_lch[chain_id].q_count++; \ } while (0) #endif + +static int dma_lch_count; static int dma_chan_count; static spinlock_t dma_chan_lock; -static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; +static struct omap_dma_lch *dma_chan; -static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { +static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = { INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, @@ -729,7 +732,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, { u32 w; - if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((lch < 0 || lch >= dma_lch_count))) { printk(KERN_ERR "Invalid channel id\n"); return -EINVAL; } @@ -777,7 +780,7 @@ void omap_start_dma(int lch) { if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; - char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ @@ -821,7 +824,7 @@ void omap_stop_dma(int lch) { if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; - char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); do { @@ -1063,7 +1066,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name, } if (unlikely((no_of_chans < 1 - || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) { + || no_of_chans > dma_lch_count))) { printk(KERN_ERR "Invalid Number of channels requested\n"); return -EINVAL; } @@ -1140,7 +1143,7 @@ int omap_modify_dma_chain_params(int chain_id, /* Check for input params */ if (unlikely((chain_id < 0 - || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1178,7 +1181,7 @@ int omap_free_dma_chain(int chain_id) u32 i; /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1218,7 +1221,7 @@ EXPORT_SYMBOL(omap_free_dma_chain); int omap_dma_chain_status(int chain_id) { /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1267,7 +1270,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, /* Check for input params */ if (unlikely((chain_id < 0 - || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1384,7 +1387,7 @@ int omap_start_dma_chain_transfers(int chain_id) int *channels; u32 w, i; - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1437,7 +1440,7 @@ int omap_stop_dma_chain_transfers(int chain_id) u32 sys_cf; /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1499,7 +1502,7 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) int *channels; /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1539,7 +1542,7 @@ int omap_get_dma_chain_dst_pos(int chain_id) int *channels; /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1573,7 +1576,7 @@ int omap_get_dma_chain_src_pos(int chain_id) int *channels; /* Check for input params */ - if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { + if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); return -EINVAL; } @@ -1726,7 +1729,7 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) printk(KERN_WARNING "Spurious DMA IRQ\n"); return IRQ_HANDLED; } - for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) { + for (i = 0; i < dma_lch_count && val != 0; i++) { if (val & 1) omap2_dma_handle_ch(i); val >>= 1; @@ -2108,6 +2111,25 @@ static int __init omap_init_dma(void) { int ch, r; + if (cpu_class_is_omap1()) + dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; + else + dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; + + dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, + GFP_KERNEL); + if (!dma_chan) + return -ENOMEM; + + if (cpu_class_is_omap2()) { + dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * + dma_lch_count, GFP_KERNEL); + if (!dma_linked_lch) { + kfree(dma_chan); + return -ENOMEM; + } + } + if (cpu_is_omap15xx()) { printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); dma_chan_count = 9; @@ -2144,16 +2166,14 @@ static int __init omap_init_dma(void) u8 revision = omap_readb(OMAP_DMA4_REVISION); printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", revision >> 4, revision & 0xf); - dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT; + dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; } else { dma_chan_count = 0; return 0; } - memset(&lcd_dma, 0, sizeof(lcd_dma)); spin_lock_init(&lcd_dma.lock); spin_lock_init(&dma_chan_lock); - memset(&dma_chan, 0, sizeof(dma_chan)); for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index be0431e..28492c3 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -68,9 +68,10 @@ #define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) #define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) -#ifdef CONFIG_ARCH_OMAP1 +#define OMAP1_LOGICAL_DMA_CH_COUNT 17 +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ -#define OMAP_LOGICAL_DMA_CH_COUNT 17 +#ifdef CONFIG_ARCH_OMAP1 /* Common channel specific registers for omap1 */ #define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) @@ -89,8 +90,6 @@ #else -#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ - /* Common channel specific registers for omap2 */ #define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/3] ARM: OMAP: Remove __REG access in DMA code 2008-04-30 17:13 ` [PATCH 1/3] ARM: OMAP: Make DMA channels dynamic " Tony Lindgren @ 2008-04-30 17:14 ` Tony Lindgren 2008-04-30 17:14 ` [PATCH 3/3] ARM: OMAP: DMA clean-up Tony Lindgren 0 siblings, 1 reply; 21+ messages in thread From: Tony Lindgren @ 2008-04-30 17:14 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Remove __REG access in DMA code, use dma_read/write instead: - dynamically set the omap_dma_base based on the omap type - omap_read/write becomes dma_read/write - dma channel registers are read with dma_ch_read/write Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/plat-omap/dma.c | 486 ++++++++++++++++++++++++-------------- drivers/mtd/nand/omap-hw.c | 8 - drivers/usb/gadget/omap_udc.c | 43 +--- include/asm-arm/arch-omap/dma.h | 200 +++++++++------- sound/arm/omap/omap-alsa-dma.c | 3 +- sound/oss/omap-audio-dma-intfc.c | 3 +- 6 files changed, 428 insertions(+), 315 deletions(-) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index d0cfe2b..5a8e0e0 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -126,6 +126,7 @@ static int dma_chan_count; static spinlock_t dma_chan_lock; static struct omap_dma_lch *dma_chan; +void __iomem *omap_dma_base; static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = { INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, @@ -142,6 +143,24 @@ static inline void omap_enable_channel_irq(int lch); #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ __func__); +#define dma_read(reg) \ +({ \ + u32 __val; \ + if (cpu_class_is_omap1()) \ + __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \ + else \ + __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \ + __val; \ +}) + +#define dma_write(val, reg) \ +({ \ + if (cpu_class_is_omap1()) \ + __raw_writew((u16)val, omap_dma_base + OMAP1_DMA_##reg);\ + else \ + __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \ +}) + #ifdef CONFIG_ARCH_OMAP15XX /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ int omap_dma_in_1510_mode(void) @@ -176,13 +195,14 @@ static inline void set_gdma_dev(int req, int dev) #define set_gdma_dev(req, dev) do {} while (0) #endif +/* Omap1 only */ static void clear_lch_regs(int lch) { int i; - u32 lch_base = OMAP_DMA_BASE + lch * 0x40; + void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch); for (i = 0; i < 0x2c; i += 2) - omap_writew(0, lch_base + i); + __raw_writew(0, lch_base + i); } void omap_set_dma_priority(int lch, int dst_port, int priority) @@ -215,10 +235,14 @@ void omap_set_dma_priority(int lch, int dst_port, int priority) } if (cpu_class_is_omap2()) { + u32 ccr; + + ccr = dma_read(CCR(lch)); if (priority) - OMAP_DMA_CCR_REG(lch) |= (1 << 6); + ccr |= (1 << 6); else - OMAP_DMA_CCR_REG(lch) &= ~(1 << 6); + ccr &= ~(1 << 6); + dma_write(ccr, CCR(lch)); } } @@ -226,22 +250,33 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, int frame_count, int sync_mode, int dma_trigger, int src_or_dst_synch) { - OMAP_DMA_CSDP_REG(lch) &= ~0x03; - OMAP_DMA_CSDP_REG(lch) |= data_type; + u32 l; + + l = dma_read(CSDP(lch)); + l &= ~0x03; + l |= data_type; + dma_write(l, CSDP(lch)); if (cpu_class_is_omap1()) { - OMAP_DMA_CCR_REG(lch) &= ~(1 << 5); + u16 ccr; + + ccr = dma_read(CCR(lch)); + ccr &= ~(1 << 5); if (sync_mode == OMAP_DMA_SYNC_FRAME) - OMAP_DMA_CCR_REG(lch) |= 1 << 5; + ccr |= 1 << 5; + dma_write(ccr, CCR(lch)); - OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2); + ccr = dma_read(CCR2(lch)); + ccr &= ~(1 << 2); if (sync_mode == OMAP_DMA_SYNC_BLOCK) - OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; + ccr |= 1 << 2; + dma_write(ccr, CCR2(lch)); } if (cpu_class_is_omap2() && dma_trigger) { - u32 val = OMAP_DMA_CCR_REG(lch); + u32 val; + val = dma_read(CCR(lch)); val &= ~(3 << 19); if (dma_trigger > 63) val |= 1 << 20; @@ -266,11 +301,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, else val &= ~(1 << 24); /* dest synch */ - OMAP_DMA_CCR_REG(lch) = val; + dma_write(val, CCR(lch)); } - OMAP_DMA_CEN_REG(lch) = elem_count; - OMAP_DMA_CFN_REG(lch) = frame_count; + dma_write(elem_count, CEN(lch)); + dma_write(frame_count, CFN(lch)); } void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) @@ -284,7 +319,9 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) return; } - w = OMAP1_DMA_CCR2_REG(lch) & ~0x03; + w = dma_read(CCR2(lch)); + w &= ~0x03; + switch (mode) { case OMAP_DMA_CONSTANT_FILL: w |= 0x01; @@ -297,23 +334,28 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) default: BUG(); } - OMAP1_DMA_CCR2_REG(lch) = w; + dma_write(w, CCR2(lch)); - w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f; + w = dma_read(LCH_CTRL(lch)); + w &= ~0x0f; /* Default is channel type 2D */ if (mode) { - OMAP1_DMA_COLOR_L_REG(lch) = (u16)color; - OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16); + dma_write((u16)color, COLOR_L(lch)); + dma_write((u16)(color >> 16), COLOR_U(lch)); w |= 1; /* Channel type G */ } - OMAP1_DMA_LCH_CTRL_REG(lch) = w; + dma_write(w, LCH_CTRL(lch)); } void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) { if (cpu_class_is_omap2()) { - OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); - OMAP_DMA_CSDP_REG(lch) |= (mode << 16); + u32 csdp; + + csdp = dma_read(CSDP(lch)); + csdp &= ~(0x3 << 16); + csdp |= (mode << 16); + dma_write(csdp, CSDP(lch)); } } @@ -323,23 +365,37 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, int src_ei, int src_fi) { if (cpu_class_is_omap1()) { - OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2); - OMAP_DMA_CSDP_REG(lch) |= src_port << 2; - } + u16 w; - OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12); - OMAP_DMA_CCR_REG(lch) |= src_amode << 12; + w = dma_read(CSDP(lch)); + w &= ~(0x1f << 2); + w |= src_port << 2; + dma_write(w, CSDP(lch)); - if (cpu_class_is_omap1()) { - OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16; - OMAP1_DMA_CSSA_L_REG(lch) = src_start; + w = dma_read(CCR(lch)); + w &= ~(0x03 << 12); + w |= src_amode << 12; + dma_write(w, CCR(lch)); + + dma_write(src_start >> 16, CSSA_U(lch)); + dma_write((u16)src_start, CSSA_L(lch)); + + dma_write(src_ei, CSEI(lch)); + dma_write(src_fi, CSFI(lch)); } - if (cpu_class_is_omap2()) - OMAP2_DMA_CSSA_REG(lch) = src_start; + if (cpu_class_is_omap2()) { + u32 l; - OMAP_DMA_CSEI_REG(lch) = src_ei; - OMAP_DMA_CSFI_REG(lch) = src_fi; + l = dma_read(CCR(lch)); + l &= ~(0x03 << 12); + l |= src_amode << 12; + dma_write(l, CCR(lch)); + + dma_write(src_start, CSSA(lch)); + dma_write(src_ei, CSEI(lch)); + dma_write(src_fi, CSFI(lch)); + } } void omap_set_dma_params(int lch, struct omap_dma_channel_params * params) @@ -366,21 +422,28 @@ void omap_set_dma_src_index(int lch, int eidx, int fidx) REVISIT_24XX(); return; } - OMAP_DMA_CSEI_REG(lch) = eidx; - OMAP_DMA_CSFI_REG(lch) = fidx; + dma_write(eidx, CSEI(lch)); + dma_write(fidx, CSFI(lch)); } void omap_set_dma_src_data_pack(int lch, int enable) { - OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6); + u32 l; + + l = dma_read(CSDP(lch)); + l &= ~(1 << 6); if (enable) - OMAP_DMA_CSDP_REG(lch) |= (1 << 6); + l |= (1 << 6); + dma_write(l, CSDP(lch)); } void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) { unsigned int burst = 0; - OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7); + u32 l; + + l = dma_read(CSDP(lch)); + l &= ~(0x03 << 7); switch (burst_mode) { case OMAP_DMA_DATA_BURST_DIS: @@ -411,7 +474,9 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) default: BUG(); } - OMAP_DMA_CSDP_REG(lch) |= (burst << 7); + + l |= (burst << 7); + dma_write(l, CSDP(lch)); } /* Note that dest_port is only for OMAP1 */ @@ -419,24 +484,30 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, unsigned long dest_start, int dst_ei, int dst_fi) { + u32 l; + if (cpu_class_is_omap1()) { - OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9); - OMAP_DMA_CSDP_REG(lch) |= dest_port << 9; + l = dma_read(CSDP(lch)); + l &= ~(0x1f << 9); + l |= dest_port << 9; + dma_write(l, CSDP(lch)); } - OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14); - OMAP_DMA_CCR_REG(lch) |= dest_amode << 14; + l = dma_read(CCR(lch)); + l &= ~(0x03 << 14); + l |= dest_amode << 14; + dma_write(l, CCR(lch)); if (cpu_class_is_omap1()) { - OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16; - OMAP1_DMA_CDSA_L_REG(lch) = dest_start; + dma_write(dest_start >> 16, CDSA_U(lch)); + dma_write(dest_start, CDSA_L(lch)); } if (cpu_class_is_omap2()) - OMAP2_DMA_CDSA_REG(lch) = dest_start; + dma_write(dest_start, CDSA(lch)); - OMAP_DMA_CDEI_REG(lch) = dst_ei; - OMAP_DMA_CDFI_REG(lch) = dst_fi; + dma_write(dst_ei, CDEI(lch)); + dma_write(dst_fi, CDFI(lch)); } void omap_set_dma_dest_index(int lch, int eidx, int fidx) @@ -445,21 +516,28 @@ void omap_set_dma_dest_index(int lch, int eidx, int fidx) REVISIT_24XX(); return; } - OMAP_DMA_CDEI_REG(lch) = eidx; - OMAP_DMA_CDFI_REG(lch) = fidx; + dma_write(eidx, CDEI(lch)); + dma_write(fidx, CDFI(lch)); } void omap_set_dma_dest_data_pack(int lch, int enable) { - OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13); + u32 l; + + l = dma_read(CSDP(lch)); + l &= ~(1 << 13); if (enable) - OMAP_DMA_CSDP_REG(lch) |= 1 << 13; + l |= 1 << 13; + dma_write(l, CSDP(lch)); } void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) { unsigned int burst = 0; - OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14); + u32 l; + + l = dma_read(CSDP(lch)); + l &= ~(0x03 << 14); switch (burst_mode) { case OMAP_DMA_DATA_BURST_DIS: @@ -489,7 +567,8 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) BUG(); return; } - OMAP_DMA_CSDP_REG(lch) |= (burst << 14); + l |= (burst << 14); + dma_write(l, CSDP(lch)); } static inline void omap_enable_channel_irq(int lch) @@ -498,12 +577,12 @@ static inline void omap_enable_channel_irq(int lch) /* Clear CSR */ if (cpu_class_is_omap1()) - status = OMAP_DMA_CSR_REG(lch); + status = dma_read(CSR(lch)); else if (cpu_class_is_omap2()) - OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); /* Enable some nice interrupts. */ - OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; + dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } @@ -511,7 +590,7 @@ static inline void omap_enable_channel_irq(int lch) static void omap_disable_channel_irq(int lch) { if (cpu_class_is_omap2()) - OMAP_DMA_CICR_REG(lch) = 0; + dma_write(0, CICR(lch)); } void omap_enable_dma_irq(int lch, u16 bits) @@ -526,36 +605,45 @@ void omap_disable_dma_irq(int lch, u16 bits) static inline void enable_lnk(int lch) { + u32 l; + + l = dma_read(CLNK_CTRL(lch)); + if (cpu_class_is_omap1()) - OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14); + l &= ~(1 << 14); /* Set the ENABLE_LNK bits */ if (dma_chan[lch].next_lch != -1) - OMAP_DMA_CLNK_CTRL_REG(lch) = - dma_chan[lch].next_lch | (1 << 15); + l = dma_chan[lch].next_lch | (1 << 15); #ifndef CONFIG_ARCH_OMAP1 if (dma_chan[lch].next_linked_ch != -1) - OMAP_DMA_CLNK_CTRL_REG(lch) = - dma_chan[lch].next_linked_ch | (1 << 15); + l = dma_chan[lch].next_linked_ch | (1 << 15); #endif + + dma_write(l, CLNK_CTRL(lch)); } static inline void disable_lnk(int lch) { + u32 l; + + l = dma_read(CLNK_CTRL(lch)); + /* Disable interrupts */ if (cpu_class_is_omap1()) { - OMAP_DMA_CICR_REG(lch) = 0; + dma_write(0, CICR(lch)); /* Set the STOP_LNK bit */ - OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; + l |= 1 << 14; } if (cpu_class_is_omap2()) { omap_disable_channel_irq(lch); /* Clear the ENABLE_LNK bit */ - OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); + l &= ~(1 << 15); } + dma_write(l, CLNK_CTRL(lch)); dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } @@ -566,9 +654,9 @@ static inline void omap2_enable_irq_lch(int lch) if (!cpu_class_is_omap2()) return; - val = omap_readl(OMAP_DMA4_IRQENABLE_L0); + val = dma_read(IRQENABLE_L0); val |= 1 << lch; - omap_writel(val, OMAP_DMA4_IRQENABLE_L0); + dma_write(val, IRQENABLE_L0); } int omap_request_dma(int dev_id, const char *dev_name, @@ -625,9 +713,9 @@ int omap_request_dma(int dev_id, const char *dev_name, } /* Disable the 1510 compatibility mode and set the sync device * id. */ - OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10); + dma_write(dev_id | (1 << 10), CCR(free_ch)); } else if (cpu_is_omap730() || cpu_is_omap15xx()) { - OMAP_DMA_CCR_REG(free_ch) = dev_id; + dma_write(dev_id, CCR(free_ch)); } if (cpu_class_is_omap2()) { @@ -635,8 +723,8 @@ int omap_request_dma(int dev_id, const char *dev_name, omap_enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ - OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK; - omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0); + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); + dma_write(1 << free_ch, IRQSTATUS_L0); } *dma_ch_out = free_ch; @@ -662,27 +750,27 @@ void omap_free_dma(int lch) if (cpu_class_is_omap1()) { /* Disable all DMA interrupts for the channel. */ - OMAP_DMA_CICR_REG(lch) = 0; + dma_write(0, CICR(lch)); /* Make sure the DMA transfer is stopped. */ - OMAP_DMA_CCR_REG(lch) = 0; + dma_write(0, CCR(lch)); } if (cpu_class_is_omap2()) { u32 val; /* Disable interrupts */ - val = omap_readl(OMAP_DMA4_IRQENABLE_L0); + val = dma_read(IRQENABLE_L0); val &= ~(1 << lch); - omap_writel(val, OMAP_DMA4_IRQENABLE_L0); + dma_write(val, IRQENABLE_L0); /* Clear the CSR register and IRQ status register */ - OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; - omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0); + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); + dma_write(1 << lch, IRQSTATUS_L0); /* Disable all DMA interrupts for the channel. */ - OMAP_DMA_CICR_REG(lch) = 0; + dma_write(0, CICR(lch)); /* Make sure the DMA transfer is stopped. */ - OMAP_DMA_CCR_REG(lch) = 0; + dma_write(0, CCR(lch)); omap_clear_dma(lch); } } @@ -713,7 +801,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) reg = (arb_rate & 0xff) << 16; reg |= (0xff & max_fifo_depth); - omap_writel(reg, OMAP_DMA4_GCR_REG); + dma_write(reg, GCR); } EXPORT_SYMBOL(omap_dma_set_global_params); @@ -730,20 +818,21 @@ int omap_dma_set_prio_lch(int lch, unsigned char read_prio, unsigned char write_prio) { - u32 w; + u32 l; if (unlikely((lch < 0 || lch >= dma_lch_count))) { printk(KERN_ERR "Invalid channel id\n"); return -EINVAL; } - w = OMAP_DMA_CCR_REG(lch); - w &= ~((1 << 6) | (1 << 26)); + l = dma_read(CCR(lch)); + l &= ~((1 << 6) | (1 << 26)); if (cpu_is_omap2430() || cpu_is_omap34xx()) - w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); + l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); else - w |= ((read_prio & 0x1) << 6); + l |= ((read_prio & 0x1) << 6); + + dma_write(l, CCR(lch)); - OMAP_DMA_CCR_REG(lch) = w; return 0; } EXPORT_SYMBOL(omap_dma_set_prio_lch); @@ -759,18 +848,21 @@ void omap_clear_dma(int lch) local_irq_save(flags); if (cpu_class_is_omap1()) { - int status; - OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN; + u32 l; + + l = dma_read(CCR(lch)); + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); /* Clear pending interrupts */ - status = OMAP_DMA_CSR_REG(lch); + l = dma_read(CSR(lch)); } if (cpu_class_is_omap2()) { int i; - u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80; + void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch); for (i = 0; i < 0x44; i += 4) - omap_writel(0, lch_base + i); + __raw_writel(0, lch_base + i); } local_irq_restore(flags); @@ -778,6 +870,8 @@ void omap_clear_dma(int lch) void omap_start_dma(int lch) { + u32 l; + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; @@ -804,24 +898,28 @@ void omap_start_dma(int lch) } while (next_lch != -1); } else if (cpu_class_is_omap2()) { /* Errata: Need to write lch even if not using chaining */ - OMAP_DMA_CLNK_CTRL_REG(lch) = lch; + dma_write(lch, CLNK_CTRL(lch)); } omap_enable_channel_irq(lch); + l = dma_read(CCR(lch)); + /* Errata: On ES2.0 BUFFERING disable must be set. * This will always fail on ES1.0 */ - if (cpu_is_omap24xx()) { - OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; - } + if (cpu_is_omap24xx()) + l |= OMAP_DMA_CCR_EN; - OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; + l |= OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } void omap_stop_dma(int lch) { + u32 l; + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; @@ -845,9 +943,12 @@ void omap_stop_dma(int lch) /* Disable all interrupts on the channel */ if (cpu_class_is_omap1()) - OMAP_DMA_CICR_REG(lch) = 0; + dma_write(0, CICR(lch)); + + l = dma_read(CCR(lch)); + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); - OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN; dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } @@ -890,11 +991,19 @@ dma_addr_t omap_get_dma_src_pos(int lch) dma_addr_t offset = 0; if (cpu_class_is_omap1()) - offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | - (OMAP1_DMA_CSSA_U_REG(lch) << 16)); + offset = (dma_addr_t)(dma_read(CSSA_L(lch)) | + (dma_read(CSSA_U(lch)) << 16)); - if (cpu_class_is_omap2()) - offset = OMAP_DMA_CSAC_REG(lch); + if (cpu_class_is_omap2()) { + offset = dma_read(CSAC(lch)); + + /* + * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is + * read before the DMA controller finished disabling the channel. + */ + if (offset == 0) + offset = dma_read(CSAC(lch)); + } return offset; } @@ -912,11 +1021,19 @@ dma_addr_t omap_get_dma_dst_pos(int lch) dma_addr_t offset = 0; if (cpu_class_is_omap1()) - offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | - (OMAP1_DMA_CDSA_U_REG(lch) << 16)); + offset = (dma_addr_t)(dma_read(CDSA_L(lch)) | + (dma_read(CDSA_U(lch)) << 16)); - if (cpu_class_is_omap2()) - offset = OMAP_DMA_CDAC_REG(lch); + if (cpu_class_is_omap2()) { + offset = dma_read(CDAC(lch)); + + /* + * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is + * read before the DMA controller finished disabling the channel. + */ + if (offset == 0) + offset = dma_read(CDAC(lch)); + } return offset; } @@ -928,8 +1045,14 @@ dma_addr_t omap_get_dma_dst_pos(int lch) */ int omap_get_dma_src_addr_counter(int lch) { - return (dma_addr_t) OMAP_DMA_CSAC_REG(lch); + return (dma_addr_t)dma_read(CSAC(lch)); +} + +int omap_get_dma_active_status(int lch) +{ + return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0; } +EXPORT_SYMBOL(omap_get_dma_active_status); int omap_dma_running(void) { @@ -941,7 +1064,7 @@ int omap_dma_running(void) return 1; for (lch = 0; lch < dma_chan_count; lch++) - if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN) + if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) return 1; return 0; @@ -1003,7 +1126,7 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue) /* Create chain of DMA channesls */ static void create_dma_lch_chain(int lch_head, int lch_queue) { - u32 w; + u32 l; /* Check if this is the first link in chain */ if (dma_chan[lch_head].next_linked_ch == -1) { @@ -1023,15 +1146,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue) lch_queue; } - w = OMAP_DMA_CLNK_CTRL_REG(lch_head); - w &= ~(0x1f); - w |= lch_queue; - OMAP_DMA_CLNK_CTRL_REG(lch_head) = w; + l = dma_read(CLNK_CTRL(lch_head)); + l &= ~(0x1f); + l |= lch_queue; + dma_write(l, CLNK_CTRL(lch_head)); - w = OMAP_DMA_CLNK_CTRL_REG(lch_queue); - w &= ~(0x1f); - w |= (dma_chan[lch_queue].next_linked_ch); - OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w; + l = dma_read(CLNK_CTRL(lch_queue)); + l &= ~(0x1f); + l |= (dma_chan[lch_queue].next_linked_ch); + dma_write(l, CLNK_CTRL(lch_queue)); } /** @@ -1258,7 +1381,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, int elem_count, int frame_count, void *callbk_data) { int *channels; - u32 w, lch; + u32 l, lch; int start_dma = 0; /* if buffer size is less than 1 then there is @@ -1299,13 +1422,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, /* Set the params to the free channel */ if (src_start != 0) - OMAP2_DMA_CSSA_REG(lch) = src_start; + dma_write(src_start, CSSA(lch)); if (dest_start != 0) - OMAP2_DMA_CDSA_REG(lch) = dest_start; + dma_write(dest_start, CDSA(lch)); /* Write the buffer size */ - OMAP_DMA_CEN_REG(lch) = elem_count; - OMAP_DMA_CFN_REG(lch) = frame_count; + dma_write(elem_count, CEN(lch)); + dma_write(frame_count, CFN(lch)); /* If the chain is dynamically linked, * then we may have to start the chain if its not active */ @@ -1332,8 +1455,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, enable_lnk(dma_chan[lch].prev_linked_ch); dma_chan[lch].state = DMA_CH_QUEUED; start_dma = 0; - if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG - (dma_chan[lch].prev_linked_ch)))) { + if (0 == ((1 << 7) & dma_read( + CCR(dma_chan[lch].prev_linked_ch)))) { disable_lnk(dma_chan[lch]. prev_linked_ch); pr_debug("\n prev ch is stopped\n"); @@ -1349,23 +1472,23 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, } omap_enable_channel_irq(lch); - w = OMAP_DMA_CCR_REG(lch); + l = dma_read(CCR(lch)); - if ((0 == (w & (1 << 24)))) - w &= ~(1 << 25); + if ((0 == (l & (1 << 24)))) + l &= ~(1 << 25); else - w |= (1 << 25); + l |= (1 << 25); if (start_dma == 1) { - if (0 == (w & (1 << 7))) { - w |= (1 << 7); + if (0 == (l & (1 << 7))) { + l |= (1 << 7); dma_chan[lch].state = DMA_CH_STARTED; pr_debug("starting %d\n", lch); - OMAP_DMA_CCR_REG(lch) = w; + dma_write(l, CCR(lch)); } else start_dma = 0; } else { - if (0 == (w & (1 << 7))) - OMAP_DMA_CCR_REG(lch) = w; + if (0 == (l & (1 << 7))) + dma_write(l, CCR(lch)); } dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } @@ -1385,7 +1508,7 @@ EXPORT_SYMBOL(omap_dma_chain_a_transfer); int omap_start_dma_chain_transfers(int chain_id) { int *channels; - u32 w, i; + u32 l, i; if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { printk(KERN_ERR "Invalid chain id\n"); @@ -1409,16 +1532,16 @@ int omap_start_dma_chain_transfers(int chain_id) omap_enable_channel_irq(channels[0]); } - w = OMAP_DMA_CCR_REG(channels[0]); - w |= (1 << 7); + l = dma_read(CCR(channels[0])); + l |= (1 << 7); dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; dma_chan[channels[0]].state = DMA_CH_STARTED; - if ((0 == (w & (1 << 24)))) - w &= ~(1 << 25); + if ((0 == (l & (1 << 24)))) + l &= ~(1 << 25); else - w |= (1 << 25); - OMAP_DMA_CCR_REG(channels[0]) = w; + l |= (1 << 25); + dma_write(l, CCR(channels[0])); dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; return 0; @@ -1436,7 +1559,7 @@ EXPORT_SYMBOL(omap_start_dma_chain_transfers); int omap_stop_dma_chain_transfers(int chain_id) { int *channels; - u32 w, i; + u32 l, i; u32 sys_cf; /* Check for input params */ @@ -1455,18 +1578,18 @@ int omap_stop_dma_chain_transfers(int chain_id) /* DMA Errata: * Special programming model needed to disable DMA before end of block */ - sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG); - w = sys_cf; + sys_cf = dma_read(OCP_SYSCONFIG); + l = sys_cf; /* Middle mode reg set no Standby */ - w &= ~((1 << 12)|(1 << 13)); - omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG); + l &= ~((1 << 12)|(1 << 13)); + dma_write(l, OCP_SYSCONFIG); for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { /* Stop the Channel transmission */ - w = OMAP_DMA_CCR_REG(channels[i]); - w &= ~(1 << 7); - OMAP_DMA_CCR_REG(channels[i]) = w; + l = dma_read(CCR(channels[i])); + l &= ~(1 << 7); + dma_write(l, CCR(channels[i])); /* Disable the link in all the channels */ disable_lnk(channels[i]); @@ -1479,7 +1602,7 @@ int omap_stop_dma_chain_transfers(int chain_id) OMAP_DMA_CHAIN_QINIT(chain_id); /* Errata - put in the old value */ - omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG); + dma_write(sys_cf, OCP_SYSCONFIG); return 0; } EXPORT_SYMBOL(omap_stop_dma_chain_transfers); @@ -1520,8 +1643,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) /* Get the current channel */ lch = channels[dma_linked_lch[chain_id].q_head]; - *ei = OMAP2_DMA_CCEN_REG(lch); - *fi = OMAP2_DMA_CCFN_REG(lch); + *ei = dma_read(CCEN(lch)); + *fi = dma_read(CCFN(lch)); return 0; } @@ -1558,7 +1681,7 @@ int omap_get_dma_chain_dst_pos(int chain_id) /* Get the current channel */ lch = channels[dma_linked_lch[chain_id].q_head]; - return (OMAP_DMA_CDAC_REG(lch)); + return dma_read(CDAC(lch)); } EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); @@ -1592,7 +1715,7 @@ int omap_get_dma_chain_src_pos(int chain_id) /* Get the current channel */ lch = channels[dma_linked_lch[chain_id].q_head]; - return (OMAP_DMA_CSAC_REG(lch)); + return dma_read(CSAC(lch)); } EXPORT_SYMBOL(omap_get_dma_chain_src_pos); #endif @@ -1603,13 +1726,13 @@ EXPORT_SYMBOL(omap_get_dma_chain_src_pos); static int omap1_dma_handle_ch(int ch) { - u16 csr; + u32 csr; if (enable_1510_mode && ch >= 6) { csr = dma_chan[ch].saved_csr; dma_chan[ch].saved_csr = 0; } else - csr = OMAP_DMA_CSR_REG(ch); + csr = dma_read(CSR(ch)); if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { dma_chan[ch + 6].saved_csr = csr >> 7; csr &= 0x7f; @@ -1661,12 +1784,12 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) static int omap2_dma_handle_ch(int ch) { - u32 status = OMAP_DMA_CSR_REG(ch); + u32 status = dma_read(CSR(ch)); if (!status) { if (printk_ratelimit()) printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch); - omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); + dma_write(1 << ch, IRQSTATUS_L0); return 0; } if (unlikely(dma_chan[ch].dev_id == -1)) { @@ -1689,14 +1812,14 @@ static int omap2_dma_handle_ch(int ch) printk(KERN_INFO "DMA misaligned error with device %d\n", dma_chan[ch].dev_id); - OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; - omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); + dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch)); + dma_write(1 << ch, IRQSTATUS_L0); /* If the ch is not chained then chain_id will be -1 */ if (dma_chan[ch].chain_id != -1) { int chain_id = dma_chan[ch].chain_id; dma_chan[ch].state = DMA_CH_NOTSTARTED; - if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15)) + if (dma_read(CLNK_CTRL(ch)) & (1 << 15)) dma_chan[dma_chan[ch].next_linked_ch].state = DMA_CH_STARTED; if (dma_linked_lch[chain_id].chain_mode == @@ -1706,13 +1829,13 @@ static int omap2_dma_handle_ch(int ch) if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) OMAP_DMA_CHAIN_INCQHEAD(chain_id); - status = OMAP_DMA_CSR_REG(ch); + status = dma_read(CSR(ch)); } if (likely(dma_chan[ch].callback != NULL)) dma_chan[ch].callback(ch, status, dma_chan[ch].data); - OMAP_DMA_CSR_REG(ch) = status; + dma_write(status, CSR(ch)); return 0; } @@ -1723,7 +1846,7 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) u32 val; int i; - val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); + val = dma_read(IRQSTATUS_L0); if (val == 0) { if (printk_ratelimit()) printk(KERN_WARNING "Spurious DMA IRQ\n"); @@ -2111,10 +2234,19 @@ static int __init omap_init_dma(void) { int ch, r; - if (cpu_class_is_omap1()) + if (cpu_class_is_omap1()) { + omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE); dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; - else + } else if (cpu_is_omap24xx()) { + omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE); dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; + } else if (cpu_is_omap34xx()) { + omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE); + dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; + } else { + pr_err("DMA init failed for unsupported omap\n"); + return -ENODEV; + } dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, GFP_KERNEL); @@ -2136,21 +2268,21 @@ static int __init omap_init_dma(void) enable_1510_mode = 1; } else if (cpu_is_omap16xx() || cpu_is_omap730()) { printk(KERN_INFO "OMAP DMA hardware version %d\n", - omap_readw(OMAP_DMA_HW_ID)); + dma_read(HW_ID)); printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", - (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | - omap_readw(OMAP_DMA_CAPS_0_L), - (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | - omap_readw(OMAP_DMA_CAPS_1_L), - omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3), - omap_readw(OMAP_DMA_CAPS_4)); + (dma_read(CAPS_0_U) << 16) | + dma_read(CAPS_0_L), + (dma_read(CAPS_1_U) << 16) | + dma_read(CAPS_1_L), + dma_read(CAPS_2), dma_read(CAPS_3), + dma_read(CAPS_4)); if (!enable_1510_mode) { u16 w; /* Disable OMAP 3.0/3.1 compatibility mode. */ - w = omap_readw(OMAP_DMA_GSCR); + w = dma_read(GSCR); w |= 1 << 3; - omap_writew(w, OMAP_DMA_GSCR); + dma_write(w, GSCR); dma_chan_count = 16; } else dma_chan_count = 9; @@ -2163,7 +2295,7 @@ static int __init omap_init_dma(void) omap_writew(w, OMAP1610_DMA_LCD_CTRL); } } else if (cpu_class_is_omap2()) { - u8 revision = omap_readb(OMAP_DMA4_REVISION); + u8 revision = dma_read(REVISION) & 0xff; printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", revision >> 4, revision & 0xf); dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; diff --git a/drivers/mtd/nand/omap-hw.c b/drivers/mtd/nand/omap-hw.c index 77817eb..1602977 100644 --- a/drivers/mtd/nand/omap-hw.c +++ b/drivers/mtd/nand/omap-hw.c @@ -269,14 +269,6 @@ static void omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, printk(KERN_WARNING "omap-hw-nand: DMA timeout after %u ms, max. seen latency %u ms\n", jiffies_to_msecs(jiffies_spent), jiffies_to_msecs(max_jiffies)); - if (OMAP_DMA_CCR_REG(dma_ch) & (1 << 7)) { - /* If the DMA transfer is still running, something - * is really wrong. */ - printk(KERN_ERR "omap-hw-nand: DMA transfer still running. Not good.\n"); - printk(KERN_INFO "DMA ch %d: CCR %04x, CSR %04x, CCDEN_L %04x\n", - dma_ch, omap_readw(OMAP_DMA_CCR_REG(dma_ch)), omap_readw(OMAP_DMA_CSR_REG(dma_ch)), - omap_readw(OMAP_DMA_BASE + 0x40 * (dma_ch) + 0x34)); - } } if (!is_write) dma_cache_maint(addr, len, DMA_FROM_DEVICE); diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c index 699ff42..c76ba46 100644 --- a/drivers/usb/gadget/omap_udc.c +++ b/drivers/usb/gadget/omap_udc.c @@ -492,32 +492,6 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) /*-------------------------------------------------------------------------*/ -static inline dma_addr_t dma_csac(unsigned lch) -{ - dma_addr_t csac; - - /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is - * read before the DMA controller finished disabling the channel. - */ - csac = OMAP_DMA_CSAC_REG(lch); - if (csac == 0) - csac = OMAP_DMA_CSAC_REG(lch); - return csac; -} - -static inline dma_addr_t dma_cdac(unsigned lch) -{ - dma_addr_t cdac; - - /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is - * read before the DMA controller finished disabling the channel. - */ - cdac = OMAP_DMA_CDAC_REG(lch); - if (cdac == 0) - cdac = OMAP_DMA_CDAC_REG(lch); - return cdac; -} - static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) { dma_addr_t end; @@ -528,7 +502,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) if (cpu_is_omap15xx()) return 0; - end = dma_csac(ep->lch); + end = omap_get_dma_src_pos(ep->lch); if (end == ep->dma_counter) return 0; @@ -538,15 +512,11 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) return end - start; } -#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \ - ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \ - : dma_cdac(x)) - static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) { dma_addr_t end; - end = DMA_DEST_LAST(ep->lch); + end = omap_get_dma_dst_pos(ep->lch); if (end == ep->dma_counter) return 0; @@ -597,7 +567,7 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req) 0, 0); omap_start_dma(ep->lch); - ep->dma_counter = dma_csac(ep->lch); + ep->dma_counter = omap_get_dma_src_pos(ep->lch); UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; req->dma_bytes = length; @@ -655,7 +625,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 0, 0); - ep->dma_counter = DMA_DEST_LAST(ep->lch); + ep->dma_counter = omap_get_dma_dst_pos(ep->lch); UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); @@ -835,7 +805,8 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) /* channel type P: hw synch (fifo) */ if (cpu_class_is_omap1() && !cpu_is_omap15xx()) - OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2; + omap_set_dma_color_mode(ep->lch, + OMAP_DMA_TRANSPARENT_COPY, 0); } just_restart: @@ -882,7 +853,7 @@ static void dma_channel_release(struct omap_ep *ep) else req = NULL; - active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0; + active = omap_get_dma_active_status(ep->lch); DBG("%s release %s %cxdma%d %p\n", ep->ep.name, active ? "active" : "idle", diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 28492c3..e62eb6e 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -22,107 +22,126 @@ #define __ASM_ARCH_DMA_H /* Hardware registers for omap1 */ -#define OMAP_DMA_BASE (0xfffed800) -#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) -#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) -#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) -#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) -#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) -#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) -#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) -#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) -#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) -#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) -#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) -#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) -#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) -#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) -#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) -#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) -#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) -#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) -#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) -#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) - -/* Hardware registers for omap2 */ -#if defined(CONFIG_ARCH_OMAP3) -#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) -#else /* CONFIG_ARCH_OMAP2 */ -#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) -#endif - -#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) -#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) -#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) -#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) -#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) -#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) -#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) -#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) -#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) -#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) -#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) -#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) -#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) -#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) -#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) -#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) +#define OMAP1_DMA_BASE (0xfffed800) + +#define OMAP1_DMA_GCR 0x400 +#define OMAP1_DMA_GSCR 0x404 +#define OMAP1_DMA_GRST 0x408 +#define OMAP1_DMA_HW_ID 0x442 +#define OMAP1_DMA_PCH2_ID 0x444 +#define OMAP1_DMA_PCH0_ID 0x446 +#define OMAP1_DMA_PCH1_ID 0x448 +#define OMAP1_DMA_PCHG_ID 0x44a +#define OMAP1_DMA_PCHD_ID 0x44c +#define OMAP1_DMA_CAPS_0_U 0x44e +#define OMAP1_DMA_CAPS_0_L 0x450 +#define OMAP1_DMA_CAPS_1_U 0x452 +#define OMAP1_DMA_CAPS_1_L 0x454 +#define OMAP1_DMA_CAPS_2 0x456 +#define OMAP1_DMA_CAPS_3 0x458 +#define OMAP1_DMA_CAPS_4 0x45a +#define OMAP1_DMA_PCH2_SR 0x460 +#define OMAP1_DMA_PCH0_SR 0x480 +#define OMAP1_DMA_PCH1_SR 0x482 +#define OMAP1_DMA_PCHD_SR 0x4c0 + +/* Hardware registers for omap2 and omap3 */ +#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) +#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) + +#define OMAP_DMA4_REVISION 0x00 +#define OMAP_DMA4_GCR 0x78 +#define OMAP_DMA4_IRQSTATUS_L0 0x08 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c +#define OMAP_DMA4_IRQSTATUS_L2 0x10 +#define OMAP_DMA4_IRQSTATUS_L3 0x14 +#define OMAP_DMA4_IRQENABLE_L0 0x18 +#define OMAP_DMA4_IRQENABLE_L1 0x1c +#define OMAP_DMA4_IRQENABLE_L2 0x20 +#define OMAP_DMA4_IRQENABLE_L3 0x24 +#define OMAP_DMA4_SYSSTATUS 0x28 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c +#define OMAP_DMA4_CAPS_0 0x64 +#define OMAP_DMA4_CAPS_2 0x6c +#define OMAP_DMA4_CAPS_3 0x70 +#define OMAP_DMA4_CAPS_4 0x74 #define OMAP1_LOGICAL_DMA_CH_COUNT 17 #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ -#ifdef CONFIG_ARCH_OMAP1 - /* Common channel specific registers for omap1 */ -#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) -#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) -#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) -#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) -#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) -#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) -#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) -#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) -#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) -#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) -#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) -#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) -#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) - -#else +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) /* Common channel specific registers for omap2 */ -#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) -#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) -#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) -#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) -#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) -#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) -#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) -#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) -#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) -#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) -#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) -#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) -#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) - -#endif +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) /* Channel specific registers only on omap1 */ -#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) -#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) -#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) -#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) -#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) -#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) -#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) -#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) +#define OMAP1_DMA_CCEN(n) 0 +#define OMAP1_DMA_CCFN(n) 0 /* Channel specific registers only on omap2 */ -#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) -#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) -#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) -#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) -#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) + +/* Dummy defines to keep multi-omap compiles happy */ +#define OMAP1_DMA_REVISION 0 +#define OMAP1_DMA_IRQSTATUS_L0 0 +#define OMAP1_DMA_IRQENABLE_L0 0 +#define OMAP1_DMA_OCP_SYSCONFIG 0 +#define OMAP_DMA4_HW_ID 0 +#define OMAP_DMA4_CAPS_0_L 0 +#define OMAP_DMA4_CAPS_0_U 0 +#define OMAP_DMA4_CAPS_1_L 0 +#define OMAP_DMA4_CAPS_1_U 0 +#define OMAP_DMA4_GSCR 0 + +#define OMAP_DMA4_LCH_CTRL(n) 0 +#define OMAP_DMA4_COLOR_L(n) 0 +#define OMAP_DMA4_COLOR_U(n) 0 +#define OMAP_DMA4_CCR2(n) 0 +#define OMAP1_DMA_CSSA(n) 0 +#define OMAP1_DMA_CDSA(n) 0 +#define OMAP_DMA4_CSSA_L(n) 0 +#define OMAP_DMA4_CSSA_U(n) 0 +#define OMAP_DMA4_CDSA_L(n) 0 +#define OMAP_DMA4_CDSA_U(n) 0 /*----------------------------------------------------------------------------*/ @@ -488,6 +507,7 @@ extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); extern int omap_get_dma_src_addr_counter(int lch); extern void omap_clear_dma(int lch); +extern int omap_get_dma_active_status(int lch); extern int omap_dma_running(void); extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams); diff --git a/sound/arm/omap/omap-alsa-dma.c b/sound/arm/omap/omap-alsa-dma.c index 3f9ff68..d263933 100644 --- a/sound/arm/omap/omap-alsa-dma.c +++ b/sound/arm/omap/omap-alsa-dma.c @@ -108,7 +108,6 @@ #define DCCR_FS (1 << 5) #define DCCR_PRIO (1 << 6) -#define DCCR_EN (1 << 7) #define DCCR_AI (1 << 8) #define DCCR_REPEAT (1 << 9) /* if 0 the channel works in 3.1 compatible mode */ @@ -420,7 +419,7 @@ static void sound_dma_irq_handler(int sound_curr_lch, u16 ch_status, sound_curr_lch, ch_status, dma_status, data); if (dma_status & (DCSR_ERROR)) { - OMAP_DMA_CCR_REG(sound_curr_lch) &= ~DCCR_EN; + omap_stop_dma(sound_curr_lch); ERR("DCSR_ERROR!\n"); FN_OUT(-1); return; diff --git a/sound/oss/omap-audio-dma-intfc.c b/sound/oss/omap-audio-dma-intfc.c index 146e288..d568582 100644 --- a/sound/oss/omap-audio-dma-intfc.c +++ b/sound/oss/omap-audio-dma-intfc.c @@ -108,7 +108,6 @@ #define DCCR_FS (1 << 5) #define DCCR_PRIO (1 << 6) -#define DCCR_EN (1 << 7) #define DCCR_AI (1 << 8) #define DCCR_REPEAT (1 << 9) /* if 0 the channel works in 3.1 compatible mode*/ @@ -872,7 +871,7 @@ static void sound_dma_irq_handler(int sound_curr_lch, u16 ch_status, void *data) if (dma_status & (DCSR_ERROR)) { if (cpu_is_omap15xx() || cpu_is_omap16xx()) - OMAP_DMA_CCR_REG(sound_curr_lch) &= ~DCCR_EN; + omap_stop_dma(sound_curr_lch); ERR("DCSR_ERROR!\n"); FN_OUT(-1); return; -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/3] ARM: OMAP: DMA clean-up 2008-04-30 17:14 ` [PATCH 2/3] ARM: OMAP: Remove __REG access in DMA code Tony Lindgren @ 2008-04-30 17:14 ` Tony Lindgren 0 siblings, 0 replies; 21+ messages in thread From: Tony Lindgren @ 2008-04-30 17:14 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren DMA clean-up, mostly checkpatch.pl fixes. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/plat-omap/dma.c | 246 +++++++++++++++++++++------------------ include/asm-arm/arch-omap/dma.h | 23 ++-- 2 files changed, 146 insertions(+), 123 deletions(-) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 5a8e0e0..3222476 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/plat-omap/dma.c * - * Copyright (C) 2003 Nokia Corporation + * Copyright (C) 2003 - 2008 Nokia Corporation * Author: Juha Yrjölä <juha.yrjola@nokia.com> * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> * Graphics DMA and LCD DMA graphics tranformations @@ -25,11 +25,11 @@ #include <linux/errno.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/io.h> #include <asm/system.h> #include <asm/hardware.h> #include <asm/dma.h> -#include <asm/io.h> #include <asm/arch/tc.h> @@ -43,13 +43,13 @@ enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; #endif -#define OMAP_DMA_ACTIVE 0x01 -#define OMAP_DMA_CCR_EN (1 << 7) +#define OMAP_DMA_ACTIVE 0x01 +#define OMAP_DMA_CCR_EN (1 << 7) #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe -#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) +#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) -static int enable_1510_mode = 0; +static int enable_1510_mode; struct omap_dma_lch { int next_lch; @@ -57,7 +57,7 @@ struct omap_dma_lch { u16 saved_csr; u16 enabled_irqs; const char *dev_name; - void (* callback)(int lch, u16 ch_status, void *data); + void (*callback)(int lch, u16 ch_status, void *data); void *data; #ifndef CONFIG_ARCH_OMAP1 @@ -245,6 +245,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority) dma_write(ccr, CCR(lch)); } } +EXPORT_SYMBOL(omap_set_dma_priority); void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, int frame_count, int sync_mode, @@ -307,6 +308,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, dma_write(elem_count, CEN(lch)); dma_write(frame_count, CFN(lch)); } +EXPORT_SYMBOL(omap_set_dma_transfer_params); void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) { @@ -346,6 +348,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) } dma_write(w, LCH_CTRL(lch)); } +EXPORT_SYMBOL(omap_set_dma_color_mode); void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) { @@ -358,12 +361,15 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) dma_write(csdp, CSDP(lch)); } } +EXPORT_SYMBOL(omap_set_dma_write_mode); /* Note that src_port is only for omap1 */ void omap_set_dma_src_params(int lch, int src_port, int src_amode, unsigned long src_start, int src_ei, int src_fi) { + u32 l; + if (cpu_class_is_omap1()) { u16 w; @@ -371,34 +377,27 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, w &= ~(0x1f << 2); w |= src_port << 2; dma_write(w, CSDP(lch)); + } - w = dma_read(CCR(lch)); - w &= ~(0x03 << 12); - w |= src_amode << 12; - dma_write(w, CCR(lch)); + l = dma_read(CCR(lch)); + l &= ~(0x03 << 12); + l |= src_amode << 12; + dma_write(l, CCR(lch)); + if (cpu_class_is_omap1()) { dma_write(src_start >> 16, CSSA_U(lch)); dma_write((u16)src_start, CSSA_L(lch)); - - dma_write(src_ei, CSEI(lch)); - dma_write(src_fi, CSFI(lch)); } - if (cpu_class_is_omap2()) { - u32 l; - - l = dma_read(CCR(lch)); - l &= ~(0x03 << 12); - l |= src_amode << 12; - dma_write(l, CCR(lch)); - + if (cpu_class_is_omap2()) dma_write(src_start, CSSA(lch)); - dma_write(src_ei, CSEI(lch)); - dma_write(src_fi, CSFI(lch)); - } + + dma_write(src_ei, CSEI(lch)); + dma_write(src_fi, CSFI(lch)); } +EXPORT_SYMBOL(omap_set_dma_src_params); -void omap_set_dma_params(int lch, struct omap_dma_channel_params * params) +void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) { omap_set_dma_transfer_params(lch, params->data_type, params->elem_count, params->frame_count, @@ -415,16 +414,17 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params) omap_dma_set_prio_lch(lch, params->read_prio, params->write_prio); } +EXPORT_SYMBOL(omap_set_dma_params); void omap_set_dma_src_index(int lch, int eidx, int fidx) { - if (cpu_class_is_omap2()) { - REVISIT_24XX(); + if (cpu_class_is_omap2()) return; - } + dma_write(eidx, CSEI(lch)); dma_write(fidx, CSFI(lch)); } +EXPORT_SYMBOL(omap_set_dma_src_index); void omap_set_dma_src_data_pack(int lch, int enable) { @@ -436,6 +436,7 @@ void omap_set_dma_src_data_pack(int lch, int enable) l |= (1 << 6); dma_write(l, CSDP(lch)); } +EXPORT_SYMBOL(omap_set_dma_src_data_pack); void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) { @@ -478,6 +479,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) l |= (burst << 7); dma_write(l, CSDP(lch)); } +EXPORT_SYMBOL(omap_set_dma_src_burst_mode); /* Note that dest_port is only for OMAP1 */ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, @@ -509,16 +511,17 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, dma_write(dst_ei, CDEI(lch)); dma_write(dst_fi, CDFI(lch)); } +EXPORT_SYMBOL(omap_set_dma_dest_params); void omap_set_dma_dest_index(int lch, int eidx, int fidx) { - if (cpu_class_is_omap2()) { - REVISIT_24XX(); + if (cpu_class_is_omap2()) return; - } + dma_write(eidx, CDEI(lch)); dma_write(fidx, CDFI(lch)); } +EXPORT_SYMBOL(omap_set_dma_dest_index); void omap_set_dma_dest_data_pack(int lch, int enable) { @@ -530,6 +533,7 @@ void omap_set_dma_dest_data_pack(int lch, int enable) l |= 1 << 13; dma_write(l, CSDP(lch)); } +EXPORT_SYMBOL(omap_set_dma_dest_data_pack); void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) { @@ -570,6 +574,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) l |= (burst << 14); dma_write(l, CSDP(lch)); } +EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); static inline void omap_enable_channel_irq(int lch) { @@ -597,11 +602,13 @@ void omap_enable_dma_irq(int lch, u16 bits) { dma_chan[lch].enabled_irqs |= bits; } +EXPORT_SYMBOL(omap_enable_dma_irq); void omap_disable_dma_irq(int lch, u16 bits) { dma_chan[lch].enabled_irqs &= ~bits; } +EXPORT_SYMBOL(omap_disable_dma_irq); static inline void enable_lnk(int lch) { @@ -617,8 +624,9 @@ static inline void enable_lnk(int lch) l = dma_chan[lch].next_lch | (1 << 15); #ifndef CONFIG_ARCH_OMAP1 - if (dma_chan[lch].next_linked_ch != -1) - l = dma_chan[lch].next_linked_ch | (1 << 15); + if (cpu_class_is_omap2()) + if (dma_chan[lch].next_linked_ch != -1) + l = dma_chan[lch].next_linked_ch | (1 << 15); #endif dma_write(l, CLNK_CTRL(lch)); @@ -660,7 +668,7 @@ static inline void omap2_enable_irq_lch(int lch) } int omap_request_dma(int dev_id, const char *dev_name, - void (* callback)(int lch, u16 ch_status, void *data), + void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) { int ch, free_ch = -1; @@ -693,10 +701,14 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->dev_name = dev_name; chan->callback = callback; chan->data = data; + #ifndef CONFIG_ARCH_OMAP1 - chan->chain_id = -1; - chan->next_linked_ch = -1; + if (cpu_class_is_omap2()) { + chan->chain_id = -1; + chan->next_linked_ch = -1; + } #endif + chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; if (cpu_class_is_omap1()) @@ -711,8 +723,10 @@ int omap_request_dma(int dev_id, const char *dev_name, set_gdma_dev(free_ch + 1, dev_id); dev_id = free_ch + 1; } - /* Disable the 1510 compatibility mode and set the sync device - * id. */ + /* + * Disable the 1510 compatibility mode and set the sync device + * id. + */ dma_write(dev_id | (1 << 10), CCR(free_ch)); } else if (cpu_is_omap730() || cpu_is_omap15xx()) { dma_write(dev_id, CCR(free_ch)); @@ -720,7 +734,6 @@ int omap_request_dma(int dev_id, const char *dev_name, if (cpu_class_is_omap2()) { omap2_enable_irq_lch(free_ch); - omap_enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); @@ -731,6 +744,7 @@ int omap_request_dma(int dev_id, const char *dev_name, return 0; } +EXPORT_SYMBOL(omap_request_dma); void omap_free_dma(int lch) { @@ -738,11 +752,12 @@ void omap_free_dma(int lch) spin_lock_irqsave(&dma_chan_lock, flags); if (dma_chan[lch].dev_id == -1) { - printk("omap_dma: trying to free nonallocated DMA channel %d\n", + pr_err("omap_dma: trying to free unallocated DMA channel %d\n", lch); spin_unlock_irqrestore(&dma_chan_lock, flags); return; } + dma_chan[lch].dev_id = -1; dma_chan[lch].next_lch = -1; dma_chan[lch].callback = NULL; @@ -774,6 +789,7 @@ void omap_free_dma(int lch) omap_clear_dma(lch); } } +EXPORT_SYMBOL(omap_free_dma); /** * @brief omap_dma_set_global_params : Set global priority settings for dma @@ -867,6 +883,7 @@ void omap_clear_dma(int lch) local_irq_restore(flags); } +EXPORT_SYMBOL(omap_clear_dma); void omap_start_dma(int lch) { @@ -905,8 +922,10 @@ void omap_start_dma(int lch) l = dma_read(CCR(lch)); - /* Errata: On ES2.0 BUFFERING disable must be set. - * This will always fail on ES1.0 */ + /* + * Errata: On ES2.0 BUFFERING disable must be set. + * This will always fail on ES1.0 + */ if (cpu_is_omap24xx()) l |= OMAP_DMA_CCR_EN; @@ -915,6 +934,7 @@ void omap_start_dma(int lch) dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } +EXPORT_SYMBOL(omap_start_dma); void omap_stop_dma(int lch) { @@ -951,13 +971,14 @@ void omap_stop_dma(int lch) dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } +EXPORT_SYMBOL(omap_stop_dma); /* * Allows changing the DMA callback function or data. This may be needed if * the driver shares a single DMA channel for multiple dma triggers. */ int omap_set_dma_callback(int lch, - void (* callback)(int lch, u16 ch_status, void *data), + void (*callback)(int lch, u16 ch_status, void *data), void *data) { unsigned long flags; @@ -977,6 +998,7 @@ int omap_set_dma_callback(int lch, return 0; } +EXPORT_SYMBOL(omap_set_dma_callback); /* * Returns current physical source address for the given DMA channel. @@ -1007,6 +1029,7 @@ dma_addr_t omap_get_dma_src_pos(int lch) return offset; } +EXPORT_SYMBOL(omap_get_dma_src_pos); /* * Returns current physical destination address for the given DMA channel. @@ -1037,6 +1060,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch) return offset; } +EXPORT_SYMBOL(omap_get_dma_dst_pos); /* * Returns current source transfer counting for the given DMA channel. @@ -1047,6 +1071,7 @@ int omap_get_dma_src_addr_counter(int lch) { return (dma_addr_t)dma_read(CSAC(lch)); } +EXPORT_SYMBOL(omap_get_dma_src_addr_counter); int omap_get_dma_active_status(int lch) { @@ -1075,7 +1100,7 @@ int omap_dma_running(void) * For this DMA link to start, you still need to start (see omap_start_dma) * the first one. That will fire up the entire queue. */ -void omap_dma_link_lch (int lch_head, int lch_queue) +void omap_dma_link_lch(int lch_head, int lch_queue) { if (omap_dma_in_1510_mode()) { printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); @@ -1092,11 +1117,12 @@ void omap_dma_link_lch (int lch_head, int lch_queue) dma_chan[lch_head].next_lch = lch_queue; } +EXPORT_SYMBOL(omap_dma_link_lch); /* * Once the DMA queue is stopped, we can destroy it. */ -void omap_dma_unlink_lch (int lch_head, int lch_queue) +void omap_dma_unlink_lch(int lch_head, int lch_queue) { if (omap_dma_in_1510_mode()) { printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); @@ -1111,7 +1137,6 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue) dump_stack(); } - if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { printk(KERN_ERR "omap_dma: You need to stop the DMA channels " @@ -1121,6 +1146,9 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue) dma_chan[lch_head].next_lch = -1; } +EXPORT_SYMBOL(omap_dma_unlink_lch); + +/*----------------------------------------------------------------------------*/ #ifndef CONFIG_ARCH_OMAP1 /* Create chain of DMA channesls */ @@ -1244,6 +1272,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name, for (i = 0; i < (no_of_chans - 1); i++) create_dma_lch_chain(channels[i], channels[i + 1]); } + return 0; } EXPORT_SYMBOL(omap_request_dma_chain); @@ -1286,6 +1315,7 @@ int omap_modify_dma_chain_params(int chain_id, */ omap_set_dma_params(channels[i], ¶ms); } + return 0; } EXPORT_SYMBOL(omap_modify_dma_chain_params); @@ -1329,6 +1359,7 @@ int omap_free_dma_chain(int chain_id) dma_linked_lch[chain_id].linked_dmach_q = NULL; dma_linked_lch[chain_id].chain_mode = -1; dma_linked_lch[chain_id].chain_state = -1; + return (0); } EXPORT_SYMBOL(omap_free_dma_chain); @@ -1359,6 +1390,7 @@ int omap_dma_chain_status(int chain_id) if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) return OMAP_DMA_CHAIN_INACTIVE; + return OMAP_DMA_CHAIN_ACTIVE; } EXPORT_SYMBOL(omap_dma_chain_status); @@ -1384,8 +1416,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, u32 l, lch; int start_dma = 0; - /* if buffer size is less than 1 then there is - * no use of starting the chain */ + /* + * if buffer size is less than 1 then there is + * no use of starting the chain + */ if (elem_count < 1) { printk(KERN_ERR "Invalid buffer size\n"); return -EINVAL; @@ -1430,12 +1464,16 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, dma_write(elem_count, CEN(lch)); dma_write(frame_count, CFN(lch)); - /* If the chain is dynamically linked, - * then we may have to start the chain if its not active */ + /* + * If the chain is dynamically linked, + * then we may have to start the chain if its not active + */ if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { - /* In Dynamic chain, if the chain is not started, - * queue the channel */ + /* + * In Dynamic chain, if the chain is not started, + * queue the channel + */ if (dma_linked_lch[chain_id].chain_state == DMA_CHAIN_NOTSTARTED) { /* Enable the link in previous channel */ @@ -1445,8 +1483,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, dma_chan[lch].state = DMA_CH_QUEUED; } - /* Chain is already started, make sure its active, - * if not then start the chain */ + /* + * Chain is already started, make sure its active, + * if not then start the chain + */ else { start_dma = 1; @@ -1493,6 +1533,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } } + return 0; } EXPORT_SYMBOL(omap_dma_chain_a_transfer); @@ -1544,6 +1585,7 @@ int omap_start_dma_chain_transfers(int chain_id) dma_write(l, CCR(channels[0])); dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; + return 0; } EXPORT_SYMBOL(omap_start_dma_chain_transfers); @@ -1575,7 +1617,8 @@ int omap_stop_dma_chain_transfers(int chain_id) } channels = dma_linked_lch[chain_id].linked_dmach_q; - /* DMA Errata: + /* + * DMA Errata: * Special programming model needed to disable DMA before end of block */ sys_cf = dma_read(OCP_SYSCONFIG); @@ -1603,6 +1646,7 @@ int omap_stop_dma_chain_transfers(int chain_id) /* Errata - put in the old value */ dma_write(sys_cf, OCP_SYSCONFIG); + return 0; } EXPORT_SYMBOL(omap_stop_dma_chain_transfers); @@ -1718,7 +1762,7 @@ int omap_get_dma_chain_src_pos(int chain_id) return dma_read(CSAC(lch)); } EXPORT_SYMBOL(omap_get_dma_chain_src_pos); -#endif +#endif /* ifndef CONFIG_ARCH_OMAP1 */ /*----------------------------------------------------------------------------*/ @@ -1754,6 +1798,7 @@ static int omap1_dma_handle_ch(int ch) dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; if (likely(dma_chan[ch].callback != NULL)) dma_chan[ch].callback(ch, csr, dma_chan[ch].data); + return 1; } @@ -1788,7 +1833,8 @@ static int omap2_dma_handle_ch(int ch) if (!status) { if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch); + printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", + ch); dma_write(1 << ch, IRQSTATUS_L0); return 0; } @@ -1876,7 +1922,7 @@ static struct irqaction omap24xx_dma_irq; static struct lcd_dma_info { spinlock_t lock; int reserved; - void (* callback)(u16 status, void *data); + void (*callback)(u16 status, void *data); void *cb_data; int active; @@ -1898,6 +1944,7 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, lcd_dma.xres = fb_xres; lcd_dma.yres = fb_yres; } +EXPORT_SYMBOL(omap_set_lcd_dma_b1); void omap_set_lcd_dma_src_port(int port) { @@ -1908,12 +1955,13 @@ void omap_set_lcd_dma_ext_controller(int external) { lcd_dma.ext_ctrl = external; } +EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); void omap_set_lcd_dma_single_transfer(int single) { lcd_dma.single_transfer = single; } - +EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); void omap_set_lcd_dma_b1_rotation(int rotate) { @@ -1924,6 +1972,7 @@ void omap_set_lcd_dma_b1_rotation(int rotate) } lcd_dma.rotate = rotate; } +EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); void omap_set_lcd_dma_b1_mirror(int mirror) { @@ -1933,6 +1982,7 @@ void omap_set_lcd_dma_b1_mirror(int mirror) } lcd_dma.mirror = mirror; } +EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); void omap_set_lcd_dma_b1_vxres(unsigned long vxres) { @@ -1943,6 +1993,7 @@ void omap_set_lcd_dma_b1_vxres(unsigned long vxres) } lcd_dma.vxres = vxres; } +EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) { @@ -1953,6 +2004,7 @@ void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) lcd_dma.xscale = xscale; lcd_dma.yscale = yscale; } +EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); static void set_b1_regs(void) { @@ -1983,8 +2035,11 @@ static void set_b1_regs(void) xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; BUG_ON(vxres < lcd_dma.xres); -#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es) + +#define PIXADDR(x, y) (lcd_dma.addr + \ + ((y) * vxres * yscale + (x) * xscale) * es) #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) + switch (lcd_dma.rotate) { case 0: if (!lcd_dma.mirror) { @@ -1993,8 +2048,8 @@ static void set_b1_regs(void) /* 1510 DMA requires the bottom address to be 2 more * than the actual last memory access location. */ if (omap_dma_in_1510_mode() && - lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) - bottom += 2; + lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) + bottom += 2; ei = PIXSTEP(0, 0, 1, 0); fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); } else { @@ -2121,7 +2176,7 @@ static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -int omap_request_lcd_dma(void (* callback)(u16 status, void *data), +int omap_request_lcd_dma(void (*callback)(u16 status, void *data), void *data) { spin_lock_irq(&lcd_dma.lock); @@ -2147,6 +2202,7 @@ int omap_request_lcd_dma(void (* callback)(u16 status, void *data), return 0; } +EXPORT_SYMBOL(omap_request_lcd_dma); void omap_free_lcd_dma(void) { @@ -2163,12 +2219,14 @@ void omap_free_lcd_dma(void) lcd_dma.reserved = 0; spin_unlock(&lcd_dma.lock); } +EXPORT_SYMBOL(omap_free_lcd_dma); void omap_enable_lcd_dma(void) { u16 w; - /* Set the Enable bit only if an external controller is + /* + * Set the Enable bit only if an external controller is * connected. Otherwise the OMAP internal controller will * start the transfer when it gets enabled. */ @@ -2185,6 +2243,7 @@ void omap_enable_lcd_dma(void) w |= 1 << 7; omap_writew(w, OMAP1610_DMA_LCD_CCR); } +EXPORT_SYMBOL(omap_enable_lcd_dma); void omap_setup_lcd_dma(void) { @@ -2200,16 +2259,18 @@ void omap_setup_lcd_dma(void) u16 w; w = omap_readw(OMAP1610_DMA_LCD_CCR); - /* If DMA was already active set the end_prog bit to have + /* + * If DMA was already active set the end_prog bit to have * the programmed register set loaded into the active * register set. */ w |= 1 << 11; /* End_prog */ if (!lcd_dma.single_transfer) - w |= (3 << 8); /* Auto_init, repeat */ + w |= (3 << 8); /* Auto_init, repeat */ omap_writew(w, OMAP1610_DMA_LCD_CCR); } } +EXPORT_SYMBOL(omap_setup_lcd_dma); void omap_stop_lcd_dma(void) { @@ -2227,6 +2288,7 @@ void omap_stop_lcd_dma(void) w &= ~(1 << 8); omap_writew(w, OMAP1610_DMA_LCD_CTRL); } +EXPORT_SYMBOL(omap_stop_lcd_dma); /*----------------------------------------------------------------------------*/ @@ -2316,8 +2378,10 @@ static int __init omap_init_dma(void) continue; if (cpu_class_is_omap1()) { - /* request_irq() doesn't like dev_id (ie. ch) being - * zero, so we have to kludge around this. */ + /* + * request_irq() doesn't like dev_id (ie. ch) being + * zero, so we have to kludge around this. + */ r = request_irq(omap1_dma_irq[ch], omap1_dma_irq_handler, 0, "DMA", (void *) (ch + 1)); @@ -2362,48 +2426,4 @@ static int __init omap_init_dma(void) arch_initcall(omap_init_dma); -EXPORT_SYMBOL(omap_get_dma_src_pos); -EXPORT_SYMBOL(omap_get_dma_dst_pos); -EXPORT_SYMBOL(omap_get_dma_src_addr_counter); -EXPORT_SYMBOL(omap_clear_dma); -EXPORT_SYMBOL(omap_set_dma_priority); -EXPORT_SYMBOL(omap_request_dma); -EXPORT_SYMBOL(omap_free_dma); -EXPORT_SYMBOL(omap_start_dma); -EXPORT_SYMBOL(omap_stop_dma); -EXPORT_SYMBOL(omap_set_dma_callback); -EXPORT_SYMBOL(omap_enable_dma_irq); -EXPORT_SYMBOL(omap_disable_dma_irq); - -EXPORT_SYMBOL(omap_set_dma_transfer_params); -EXPORT_SYMBOL(omap_set_dma_color_mode); -EXPORT_SYMBOL(omap_set_dma_write_mode); - -EXPORT_SYMBOL(omap_set_dma_src_params); -EXPORT_SYMBOL(omap_set_dma_src_index); -EXPORT_SYMBOL(omap_set_dma_src_data_pack); -EXPORT_SYMBOL(omap_set_dma_src_burst_mode); - -EXPORT_SYMBOL(omap_set_dma_dest_params); -EXPORT_SYMBOL(omap_set_dma_dest_index); -EXPORT_SYMBOL(omap_set_dma_dest_data_pack); -EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); - -EXPORT_SYMBOL(omap_set_dma_params); - -EXPORT_SYMBOL(omap_dma_link_lch); -EXPORT_SYMBOL(omap_dma_unlink_lch); - -EXPORT_SYMBOL(omap_request_lcd_dma); -EXPORT_SYMBOL(omap_free_lcd_dma); -EXPORT_SYMBOL(omap_enable_lcd_dma); -EXPORT_SYMBOL(omap_setup_lcd_dma); -EXPORT_SYMBOL(omap_stop_lcd_dma); -EXPORT_SYMBOL(omap_set_lcd_dma_b1); -EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); -EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); -EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); -EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); -EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); -EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index e62eb6e..00b1f68 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -435,18 +435,21 @@ struct omap_dma_channel_params { int frame_count; /* number of frames in a element */ int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ - int src_amode; /* constant , post increment, indexed , double indexed */ + int src_amode; /* constant, post increment, indexed, + double indexed */ unsigned long src_start; /* source address : physical */ int src_ei; /* source element index */ int src_fi; /* source frame index */ int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ - int dst_amode; /* constant , post increment, indexed , double indexed */ + int dst_amode; /* constant, post increment, indexed, + double indexed */ unsigned long dst_start; /* source address : physical */ int dst_ei; /* source element index */ int dst_fi; /* source frame index */ - int trigger; /* trigger attached if the channel is synchronized */ + int trigger; /* trigger attached if the channel is + synchronized */ int sync_mode; /* sycn on element, frame , block or packet */ int src_or_dst_synch; /* source synch(1) or destination synch(0) */ @@ -463,8 +466,8 @@ struct omap_dma_channel_params { extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, - void (* callback)(int lch, u16 ch_status, void *data), - void *data, int *dma_ch); + void (*callback)(int lch, u16 ch_status, + void *data), void *data, int *dma_ch); extern void omap_enable_dma_irq(int ch, u16 irq_bits); extern void omap_disable_dma_irq(int ch, u16 irq_bits); extern void omap_free_dma(int ch); @@ -495,13 +498,13 @@ extern void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode); extern void omap_set_dma_params(int lch, - struct omap_dma_channel_params * params); + struct omap_dma_channel_params *params); -extern void omap_dma_link_lch (int lch_head, int lch_queue); -extern void omap_dma_unlink_lch (int lch_head, int lch_queue); +extern void omap_dma_link_lch(int lch_head, int lch_queue); +extern void omap_dma_unlink_lch(int lch_head, int lch_queue); extern int omap_set_dma_callback(int lch, - void (* callback)(int lch, u16 ch_status, void *data), + void (*callback)(int lch, u16 ch_status, void *data), void *data); extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); @@ -541,7 +544,7 @@ extern int omap_dma_chain_status(int chain_id); #endif /* LCD DMA functions */ -extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), +extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), void *data); extern void omap_free_lcd_dma(void); extern void omap_setup_lcd_dma(void); -- 1.5.3.6 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 21+ messages in thread
* RE: [PATCH 0/3] DMA clean-up for multi-boot 2008-04-30 17:13 [PATCH 0/3] DMA clean-up for multi-boot Tony Lindgren 2008-04-30 17:13 ` [PATCH 1/3] ARM: OMAP: Make DMA channels dynamic " Tony Lindgren @ 2008-04-30 18:00 ` Gadiyar, Anand 2008-05-02 15:15 ` Gadiyar, Anand 2008-05-05 10:14 ` Jarkko Nikula 3 siblings, 0 replies; 21+ messages in thread From: Gadiyar, Anand @ 2008-04-30 18:00 UTC (permalink / raw) To: Tony Lindgren, linux-omap@vger.kernel.org > Hi all, > > Here are three patches to clean DMA code to support multi-boot > better. I have made quick testing on 24xx and 34xx only so far, > and things seem to work. > > I will also do more testing, but I would appreciate if people would > give them a quick spin and see if anything breaks. Functionality > should be same as earlier. > I'll try and test these over the next couple of days. I had some DMA cleanups pending. Will wait till these get in. - Anand > I've removed direct DMA register access in few places such as > omap-hw.c, usb-udc.c, and various audio drivers. So especially > those areas should be tested carefully. > > Regards, > > Tony > > -- > To unsubscribe from this list: send the line "unsubscribe > linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH 0/3] DMA clean-up for multi-boot 2008-04-30 17:13 [PATCH 0/3] DMA clean-up for multi-boot Tony Lindgren 2008-04-30 17:13 ` [PATCH 1/3] ARM: OMAP: Make DMA channels dynamic " Tony Lindgren 2008-04-30 18:00 ` [PATCH 0/3] DMA clean-up for multi-boot Gadiyar, Anand @ 2008-05-02 15:15 ` Gadiyar, Anand 2008-05-02 18:11 ` Tony Lindgren 2008-05-05 10:14 ` Jarkko Nikula 3 siblings, 1 reply; 21+ messages in thread From: Gadiyar, Anand @ 2008-05-02 15:15 UTC (permalink / raw) To: Tony Lindgren, linux-omap@vger.kernel.org > Hi all, > > Here are three patches to clean DMA code to support multi-boot > better. I have made quick testing on 24xx and 34xx only so far, > and things seem to work. > > I will also do more testing, but I would appreciate if people would > give them a quick spin and see if anything breaks. Functionality > should be same as earlier. > > I've removed direct DMA register access in few places such as > omap-hw.c, usb-udc.c, and various audio drivers. So especially > those areas should be tested carefully. > > Regards, > > Tony I ran some DMA tests I had on a 3430SDP and they work just fine. Have not tried on OMAP2 yet. Will run some more tests over the weekend. Regards, Anand ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 0/3] DMA clean-up for multi-boot 2008-05-02 15:15 ` Gadiyar, Anand @ 2008-05-02 18:11 ` Tony Lindgren 2008-05-16 17:34 ` Tony Lindgren 0 siblings, 1 reply; 21+ messages in thread From: Tony Lindgren @ 2008-05-02 18:11 UTC (permalink / raw) To: Gadiyar, Anand; +Cc: linux-omap@vger.kernel.org * Gadiyar, Anand <gadiyar@ti.com> [080502 08:15]: > > Hi all, > > > > Here are three patches to clean DMA code to support multi-boot > > better. I have made quick testing on 24xx and 34xx only so far, > > and things seem to work. > > > > I will also do more testing, but I would appreciate if people would > > give them a quick spin and see if anything breaks. Functionality > > should be same as earlier. > > > > I've removed direct DMA register access in few places such as > > omap-hw.c, usb-udc.c, and various audio drivers. So especially > > those areas should be tested carefully. > > > > Regards, > > > > Tony > > I ran some DMA tests I had on a 3430SDP and they work just fine. Have not tried on OMAP2 yet. > Will run some more tests over the weekend. Thanks for testing, I still need to test it on at least 15xx but need to reflash my 1510 innovator first. Tony ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 0/3] DMA clean-up for multi-boot 2008-05-02 18:11 ` Tony Lindgren @ 2008-05-16 17:34 ` Tony Lindgren 0 siblings, 0 replies; 21+ messages in thread From: Tony Lindgren @ 2008-05-16 17:34 UTC (permalink / raw) To: Gadiyar, Anand; +Cc: linux-omap@vger.kernel.org * Tony Lindgren <tony@atomide.com> [080502 11:13]: > * Gadiyar, Anand <gadiyar@ti.com> [080502 08:15]: > > > Hi all, > > > > > > Here are three patches to clean DMA code to support multi-boot > > > better. I have made quick testing on 24xx and 34xx only so far, > > > and things seem to work. > > > > > > I will also do more testing, but I would appreciate if people would > > > give them a quick spin and see if anything breaks. Functionality > > > should be same as earlier. > > > > > > I've removed direct DMA register access in few places such as > > > omap-hw.c, usb-udc.c, and various audio drivers. So especially > > > those areas should be tested carefully. > > > > > > Regards, > > > > > > Tony > > > > I ran some DMA tests I had on a 3430SDP and they work just fine. Have not tried on OMAP2 yet. > > Will run some more tests over the weekend. > > Thanks for testing, I still need to test it on at least 15xx but need > to reflash my 1510 innovator first. I've pushed these, turns out my 1510 Innovator seems to have broken SDRAM and won't boot any longer :( So in case somebody has DMA issues on 15xx let me know. Tony ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 0/3] DMA clean-up for multi-boot 2008-04-30 17:13 [PATCH 0/3] DMA clean-up for multi-boot Tony Lindgren ` (2 preceding siblings ...) 2008-05-02 15:15 ` Gadiyar, Anand @ 2008-05-05 10:14 ` Jarkko Nikula 2008-05-05 23:27 ` public git l2 cache off Woodruff, Richard 3 siblings, 1 reply; 21+ messages in thread From: Jarkko Nikula @ 2008-05-05 10:14 UTC (permalink / raw) To: ext Tony Lindgren; +Cc: linux-omap On Wed, 30 Apr 2008 10:13:58 -0700 "ext Tony Lindgren" <tony@atomide.com> wrote: > Hi all, > > Here are three patches to clean DMA code to support multi-boot > better. I have made quick testing on 24xx and 34xx only so far, > and things seem to work. > > I will also do more testing, but I would appreciate if people would > give them a quick spin and see if anything breaks. Functionality > should be same as earlier. > OMAP ASoC is still working on N810. Jarkko ^ permalink raw reply [flat|nested] 21+ messages in thread
* public git l2 cache off. 2008-05-05 10:14 ` Jarkko Nikula @ 2008-05-05 23:27 ` Woodruff, Richard 2008-05-06 5:38 ` Koen Kooi 0 siblings, 1 reply; 21+ messages in thread From: Woodruff, Richard @ 2008-05-05 23:27 UTC (permalink / raw) To: ext Tony Lindgren; +Cc: linux-omap Hi, Looks like a tweak from the ARM or TI tree may be needed. Builds of recent pulls of the OMAP3 kernel show L2 cache is disabled. This really has a huge performance impact. I don't have time right now to suggest a patch but may look some time this week. TI internal kernels do have it enabled. A stop in Lauterbach and a look at the L2EN bit in AUX control register will show it is not correct. Regards, Richard W. ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-05 23:27 ` public git l2 cache off Woodruff, Richard @ 2008-05-06 5:38 ` Koen Kooi 2008-05-06 6:58 ` Koen Kooi 2008-05-06 15:06 ` Woodruff, Richard 0 siblings, 2 replies; 21+ messages in thread From: Koen Kooi @ 2008-05-06 5:38 UTC (permalink / raw) To: Woodruff, Richard; +Cc: linux-omap -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Op 6 mei 2008, om 01:27 heeft Woodruff, Richard het volgende geschreven: > Hi, > > Looks like a tweak from the ARM or TI tree may be needed. Builds of > recent pulls of the OMAP3 kernel show L2 cache is disabled. This > really has a huge performance impact. > > I don't have time right now to suggest a patch but may look some > time this week. TI internal kernels do have it enabled. > > A stop in Lauterbach and a look at the L2EN bit in AUX control > register will show it is not correct. Enabling L2 cache was removed from proc-v7.S since was cortex specific instead of armv7 specific and u-boot explicitly turns of L2 before booting into linux. I made a reverse patch, but my omap3 board doesn't boot if I use it: - --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -665,6 +665,12 @@ config CPU_CACHE_ROUND_ROBIN Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. +config CPU_L2CACHE_DISABLE + bool "Disable level 2 cache" + depends on CPU_V7 + help + Say Y here to disable the level 2 cache. If unsure, say N. + config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index a1d7331..432ddab 100644 - --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -181,6 +181,16 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register +#ifndef CONFIG_CPU_L2CACHE_DISABLE + @ L2 cache configuration in the L2 aux control register + mrc p15, 1, r10, c9, c0, 2 + bic r10, r10, #(1 << 16) @ L2 outer cache + mcr p15, 1, r10, c9, c0, 2 + @ L2 cache is enabled in the aux control register + mrc p15, 0, r10, c1, c0, 1 + orr r10, r10, #2 + mcr p15, 0, r10, c1, c0, 1 +#endif #endif adr r5, v7_crval ldmia r5, {r5, r6} -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFIH+71MkyGM64RGpERAu1EAKCLF8Id735bHUovuZzn56koZw/YywCfb31G KiN6OiMd1EkOBPa76Ogo+zs= =R9mv -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-06 5:38 ` Koen Kooi @ 2008-05-06 6:58 ` Koen Kooi 2008-05-06 15:06 ` Woodruff, Richard 1 sibling, 0 replies; 21+ messages in thread From: Koen Kooi @ 2008-05-06 6:58 UTC (permalink / raw) To: linux-omap -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Op 6 mei 2008, om 07:38 heeft Koen Kooi het volgende geschreven: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > > Op 6 mei 2008, om 01:27 heeft Woodruff, Richard het volgende > geschreven: >> Hi, >> >> Looks like a tweak from the ARM or TI tree may be needed. Builds >> of recent pulls of the OMAP3 kernel show L2 cache is disabled. This >> really has a huge performance impact. >> >> I don't have time right now to suggest a patch but may look some >> time this week. TI internal kernels do have it enabled. >> >> A stop in Lauterbach and a look at the L2EN bit in AUX control >> register will show it is not correct. > > Enabling L2 cache was removed from proc-v7.S since was cortex > specific instead of armv7 specific For reference: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=7092fc38ee770251aed361572bf6bed05fcf3ee2 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFIIAGMMkyGM64RGpERAgh0AJ9lAmo66yaPu6Yxhp7yeW4S5pvaKwCgppYv jUZY8KpVn0AuQDdhjN2gfBg= =fH+z -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: public git l2 cache off. 2008-05-06 5:38 ` Koen Kooi 2008-05-06 6:58 ` Koen Kooi @ 2008-05-06 15:06 ` Woodruff, Richard 2008-05-06 16:20 ` Koen Kooi 2008-05-06 18:13 ` Dirk Behme 1 sibling, 2 replies; 21+ messages in thread From: Woodruff, Richard @ 2008-05-06 15:06 UTC (permalink / raw) To: Koen Kooi; +Cc: linux-omap > Enabling L2 cache was removed from proc-v7.S since was cortex specific > instead of armv7 specific and u-boot explicitly turns of L2 before > booting into linux. I made a reverse patch, but my omap3 board doesn't > boot if I use it: Our 2.6.24 kernel does something close and boots fine on OMAP3-SDP and Labrador boards. Which platform did you try on? I'll try the latest from here on SDP with this and see if it works. There is also a difference in CR handling. I had submitted long back a fix to Russell but let it get by me as I didn't have the time to fix per his comments. I think our version was more correct then the one in place but was still lacking a bit. [*] It seems possible you could have an issue depending on what your boot loader is or isn't doing for you. Regards, Richard W. ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-06 15:06 ` Woodruff, Richard @ 2008-05-06 16:20 ` Koen Kooi 2008-05-06 16:51 ` Woodruff, Richard 2008-05-06 18:13 ` Dirk Behme 1 sibling, 1 reply; 21+ messages in thread From: Koen Kooi @ 2008-05-06 16:20 UTC (permalink / raw) To: Woodruff, Richard; +Cc: linux-omap -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Op 6 mei 2008, om 17:06 heeft Woodruff, Richard het volgende geschreven: >> Enabling L2 cache was removed from proc-v7.S since was cortex >> specific >> instead of armv7 specific and u-boot explicitly turns of L2 before >> booting into linux. I made a reverse patch, but my omap3 board >> doesn't >> boot if I use it: > > Our 2.6.24 kernel does something close and boots fine on OMAP3-SDP > and Labrador boards. Which platform did you try on? Beagleboard (omap3530) > I'll try the latest from here on SDP with this and see if it works. > There is also a difference in CR handling. I had submitted long > back a fix to Russell but let it get by me as I didn't have the time > to fix per his comments. I think our version was more correct then > the one in place but was still lacking a bit. > > [*] It seems possible you could have an issue depending on what your > boot loader is or isn't doing for you. U-boot (both 1.1.4 and 1.3.2) calls l2disable() before booting linux, so linux needs to enable it. I vote for removing the l2disable() in u- boot, but I can see that people might be stuck with broken binary bootloaders... regards, Koen > > > Regards, > Richard W. > > -- > To unsubscribe from this list: send the line "unsubscribe linux- > omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFIIIU6MkyGM64RGpERAskVAJ9v+zkGPPVi5E2Icb+LHPpoX9rdYgCeOQde zo4KEu3uL8kZliQFQ4YESWE= =mmNw -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: public git l2 cache off. 2008-05-06 16:20 ` Koen Kooi @ 2008-05-06 16:51 ` Woodruff, Richard 2008-05-06 17:01 ` Koen Kooi 2008-05-10 8:14 ` Dirk Behme 0 siblings, 2 replies; 21+ messages in thread From: Woodruff, Richard @ 2008-05-06 16:51 UTC (permalink / raw) To: Koen Kooi; +Cc: linux-omap > Beagleboard (omap3530) > > > I'll try the latest from here on SDP with this and see if it works. > > There is also a difference in CR handling. I had submitted long > > back a fix to Russell but let it get by me as I didn't have the time > > to fix per his comments. I think our version was more correct then > > the one in place but was still lacking a bit. > > > > [*] It seems possible you could have an issue depending on what your > > boot loader is or isn't doing for you. > > U-boot (both 1.1.4 and 1.3.2) calls l2disable() before booting linux, > so linux needs to enable it. I vote for removing the l2disable() in u- > boot, but I can see that people might be stuck with broken binary > bootloaders... Yes, this 'might' help for some users if it works. Traditionally things usually have had some complications here at multiple levels in both hardware and software. And yes not everyone can upgrade a boot loader. However, with expanding boot from MMC/SD support things are getting safer. The bit I was more worried about was the boot loader may not be invalidating secure L2 tags correctly. The method to do this correctly is a little different between EMU/HS and GP devices. Also these base methods changed some between ES1 and ES2 of the chip. I hope no one is using an ES1 anymore but I'm sure code remnants exist. The working code variants did some work in u-boot and some in the kernel to handle these conditions. The current balance today in working variants today has u-boot doing more work. This probably merges with fewer conflicts with the arm-kernel. Last I checked u-boot on Beagle was a based on an older version of the code and probably even a wider range of versions exist in the community. As such it's a good bet some of this is at the root of the problems you are seeing. It is important to keep x-loader/u-boot/kernel somewhat in sync for some of these kinds of issues until the development process has settled down and code matured. L2 cache is a huge performance boost on an OMAP3 so it's good to get it. Also you really haven't validated your software if you're running with it off. Regards, Richard W. ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-06 16:51 ` Woodruff, Richard @ 2008-05-06 17:01 ` Koen Kooi 2008-05-06 21:25 ` Tony Lindgren 2008-05-07 7:42 ` Syed Mohammed, Khasim 2008-05-10 8:14 ` Dirk Behme 1 sibling, 2 replies; 21+ messages in thread From: Koen Kooi @ 2008-05-06 17:01 UTC (permalink / raw) To: Woodruff, Richard; +Cc: linux-omap -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Op 6 mei 2008, om 18:51 heeft Woodruff, Richard het volgende geschreven: >> Beagleboard (omap3530) >> >>> I'll try the latest from here on SDP with this and see if it works. >>> There is also a difference in CR handling. I had submitted long >>> back a fix to Russell but let it get by me as I didn't have the time >>> to fix per his comments. I think our version was more correct then >>> the one in place but was still lacking a bit. >>> >>> [*] It seems possible you could have an issue depending on what your >>> boot loader is or isn't doing for you. >> >> U-boot (both 1.1.4 and 1.3.2) calls l2disable() before booting linux, >> so linux needs to enable it. I vote for removing the l2disable() in >> u- >> boot, but I can see that people might be stuck with broken binary >> bootloaders... > > Yes, this 'might' help for some users if it works. Traditionally > things usually have had some complications here at multiple levels > in both hardware and software. And yes not everyone can upgrade a > boot loader. However, with expanding boot from MMC/SD support > things are getting safer. > > The bit I was more worried about was the boot loader may not be > invalidating secure L2 tags correctly. The method to do this > correctly is a little different between EMU/HS and GP devices. Also > these base methods changed some between ES1 and ES2 of the chip. I > hope no one is using an ES1 anymore but I'm sure code remnants exist. > > The working code variants did some work in u-boot and some in the > kernel to handle these conditions. The current balance today in > working variants today has u-boot doing more work. This probably > merges with fewer conflicts with the arm-kernel. Last I checked u- > boot on Beagle was a based on an older version of the code and > probably even a wider range of versions exist in the community. As > such it's a good bet some of this is at the root of the problems you > are seeing. I'm currently using the u-boot Jason built (1.3.2 + beagle patches) which disables l2 cache before boot and I switch between 2.6.22-wtbu (which enables L2) and git HEAD (which doesn't enable L2). regards, Koen > > > It is important to keep x-loader/u-boot/kernel somewhat in sync for > some of these kinds of issues until the development process has > settled down and code matured. > > L2 cache is a huge performance boost on an OMAP3 so it's good to get > it. Also you really haven't validated your software if you're > running with it off. > > Regards, > Richard W. > > -- > To unsubscribe from this list: send the line "unsubscribe linux- > omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFIII79MkyGM64RGpERAtvQAJ48vSb7R+zcqdSvVZVNE2Gi1mCAoACglzMo 3N3Xt8DeBWfdyZ8DmCfc4OY= =lEih -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-06 17:01 ` Koen Kooi @ 2008-05-06 21:25 ` Tony Lindgren 2008-05-07 7:42 ` Syed Mohammed, Khasim 1 sibling, 0 replies; 21+ messages in thread From: Tony Lindgren @ 2008-05-06 21:25 UTC (permalink / raw) To: Koen Kooi; +Cc: Woodruff, Richard, linux-omap * Koen Kooi <k.kooi@student.utwente.nl> [080506 10:02]: > > Op 6 mei 2008, om 18:51 heeft Woodruff, Richard het volgende geschreven: > >> Beagleboard (omap3530) > >> > >>> I'll try the latest from here on SDP with this and see if it works. > >>> There is also a difference in CR handling. I had submitted long > >>> back a fix to Russell but let it get by me as I didn't have the time > >>> to fix per his comments. I think our version was more correct then > >>> the one in place but was still lacking a bit. > >>> > >>> [*] It seems possible you could have an issue depending on what your > >>> boot loader is or isn't doing for you. > >> > >> U-boot (both 1.1.4 and 1.3.2) calls l2disable() before booting linux, > >> so linux needs to enable it. I vote for removing the l2disable() in > >> u- > >> boot, but I can see that people might be stuck with broken binary > >> bootloaders... > > > > Yes, this 'might' help for some users if it works. Traditionally > > things usually have had some complications here at multiple levels > > in both hardware and software. And yes not everyone can upgrade a > > boot loader. However, with expanding boot from MMC/SD support > > things are getting safer. > > > > The bit I was more worried about was the boot loader may not be > > invalidating secure L2 tags correctly. The method to do this > > correctly is a little different between EMU/HS and GP devices. Also > > these base methods changed some between ES1 and ES2 of the chip. I > > hope no one is using an ES1 anymore but I'm sure code remnants exist. > > > > The working code variants did some work in u-boot and some in the > > kernel to handle these conditions. The current balance today in > > working variants today has u-boot doing more work. This probably > > merges with fewer conflicts with the arm-kernel. Last I checked u- > > boot on Beagle was a based on an older version of the code and > > probably even a wider range of versions exist in the community. As > > such it's a good bet some of this is at the root of the problems you > > are seeing. > > I'm currently using the u-boot Jason built (1.3.2 + beagle patches) > which disables l2 cache before boot and I switch between 2.6.22-wtbu > (which enables L2) and git HEAD (which doesn't enable L2). Sounds like the bootloader should configure L2 cache and just leave the C bit off for kernel looking at the "Cortex-A8 L2 cache handling at startup?" thread on linux-arm-kernel. I guess the L2 configuration is implementation specific and cannot be read from the ARM registers. Regards, Tony > > regards, > > Koen > > > > > > > > It is important to keep x-loader/u-boot/kernel somewhat in sync for > > some of these kinds of issues until the development process has > > settled down and code matured. > > > > L2 cache is a huge performance boost on an OMAP3 so it's good to get > > it. Also you really haven't validated your software if you're > > running with it off. > > > > Regards, > > Richard W. > > > > -- > > To unsubscribe from this list: send the line "unsubscribe linux- > > omap" in > > the body of a message to majordomo@vger.kernel.org > > More majordomo info at http://vger.kernel.org/majordomo-info.html > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: public git l2 cache off. 2008-05-06 17:01 ` Koen Kooi 2008-05-06 21:25 ` Tony Lindgren @ 2008-05-07 7:42 ` Syed Mohammed, Khasim 2008-05-07 10:51 ` Koen Kooi 1 sibling, 1 reply; 21+ messages in thread From: Syed Mohammed, Khasim @ 2008-05-07 7:42 UTC (permalink / raw) To: Koen Kooi; +Cc: linux-omap@vger.kernel.org, Woodruff, Richard The below patch should get you going with L2 Cache enabled on GIT kernel, tested on Beagle board. Regards, Khasim --- ../my_linux_omap/arch/arm/mm/Kconfig 2008-05-06 16:37:17.000000000 +0530 +++ arch/arm/mm/Kconfig 2008-05-07 12:40:05.000000000 +0530 @@ -659,6 +659,20 @@ config CPU_DCACHE_SIZE If your SoC is configured to have a different size, define the value here with proper conditions. +choice + prompt "L2 Cache Size" + depends on ARCH_OMAP34XX + +config CPU_LOCKDOWN_TO_64K_L2 + bool "Lock down L2 Cache to 64K" + +config CPU_LOCKDOWN_TO_128K_L2 + bool "Lock down L2 Cache to 128K" + +config CPU_LOCKDOWN_TO_256K_L2 + bool "Lock down L2 Cache to 256K" +endchoice + config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE @@ -674,6 +688,12 @@ config CPU_CACHE_ROUND_ROBIN Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. +config CPU_L2CACHE_DISABLE + bool "Disable level 2 cache" + depends on CPU_V7 + help + Say Y here to disable the level 2 cache. If unsure, say N. + config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 --- ../my_linux_omap/arch/arm/mm/proc-v7.S 2008-04-27 00:13:57.000000000 +0530 +++ arch/arm/mm/proc-v7.S 2008-05-07 12:22:29.000000000 +0530 @@ -182,11 +182,72 @@ __v7_setup: mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register #endif +#if defined(CONFIG_ARCH_OMAP3) + @ L2 cache is enabled in the aux control register + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x11 @ speculative+no-alais protection +#ifdef CONFIG_CPU_L2CACHE_DISABLE + bic r0, r0, #0x2 @ disable L2 Cache. +#else + orr r0, r0, #0x2 @ enaable L2 Cache. +#endif + +/* On 3430 ES2.0 ZeBu and silicon, Aux Ctrl Reg can be written outside + * Secure mode also + */ + mcr p15, 0, r0, c1, c0, 1 + +#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_CPU_LOCKDOWN_TO_64K_L2 + mov r10, #0xfc + mcr p15, 1, r10, c9, c0, 0 +#endif + +#ifdef CONFIG_CPU_LOCKDOWN_TO_128K_L2 + mov r10, #0xf0 + mcr p15, 1, r10, c9, c0, 0 +#endif + +#ifdef CONFIG_CPU_LOCKDOWN_TO_256K_L2 + mov r10, #0x00 + mcr p15, 1, r10, c9, c0, 0 +#endif +#endif + adr r5, v7_crval ldmia r5, {r5, r6} - mrc p15, 0, r0, c1, c0, 0 @ read control register - bic r0, r0, r5 @ clear bits them - orr r0, r0, r6 @ set them + mrc p15, 0, r0, c1, c0, 0 @ read control register + bic r0, r0, r5 @ clear bits them + orr r0, r0, r6 @ set them + mov pc, lr @ return to head.S:__ret + + /* + * TAT N EV F H R + * .EFR M.EE .UI. ..A. .RVI Z... B... .CAM + * 0xxx x0xx 11x0 01x1 0xxx x000 0111 1xxx < forced typical + * r rr rr r rr r r rrr rrrr r < always read only + * .000 ..00 ..0. ..0. .011 1... .... .101 < we want + */ + .type v7_crval, #object +v7_crval: + crval clear=0x7322f006, mmuset=0x00003805, ucset=0x00001804 +#else + +#ifndef CONFIG_CPU_L2CACHE_DISABLE + @ L2 cache configuration in the L2 aux control register + mrc p15, 1, r10, c9, c0, 2 + bic r10, r10, #(1 << 16) @ L2 outer cache + mcr p15, 1, r10, c9, c0, 2 + @ L2 cache is enabled in the aux control register + mrc p15, 0, r10, c1, c0, 1 + orr r10, r10, #2 + mcr p15, 0, r10, c1, c0, 1 +#endif + mrc p15, 0, r0, c1, c0, 0 @ read control register + ldr r10, cr1_clear @ get mask for bits to clear + bic r0, r0, r10 @ clear bits them + ldr r10, cr1_set @ get mask for bits to set + orr r0, r0, r10 @ set them mov pc, lr @ return to head.S:__ret /* @@ -195,9 +256,13 @@ __v7_setup: * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced * 0 110 0011 1.00 .111 1101 < we want */ - .type v7_crval, #object -v7_crval: - crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c + .type cr1_clear, #object + .type cr1_set, #object +cr1_clear: + .word 0x0120c302 +cr1_set: + .word 0x00c0387d +#endif __v7_setup_stack: .space 4 * 11 @ 11 registers @@ -205,7 +270,6 @@ __v7_setup_stack: .type v7_processor_functions, #object ENTRY(v7_processor_functions) .word v7_early_abort - .word pabort_ifar .word cpu_v7_proc_init .word cpu_v7_proc_fin .word cpu_v7_reset @@ -213,6 +277,7 @@ ENTRY(v7_processor_functions) .word cpu_v7_dcache_clean_area .word cpu_v7_switch_mm .word cpu_v7_set_pte_ext + .word pabort_ifar .size v7_processor_functions, . - v7_processor_functions .type cpu_arch_name, #object ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-07 7:42 ` Syed Mohammed, Khasim @ 2008-05-07 10:51 ` Koen Kooi 0 siblings, 0 replies; 21+ messages in thread From: Koen Kooi @ 2008-05-07 10:51 UTC (permalink / raw) To: Syed Mohammed, Khasim; +Cc: linux-omap -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Op 7 mei 2008, om 09:42 heeft Syed Mohammed, Khasim het volgende geschreven: > The below patch should get you going with L2 Cache enabled on GIT > kernel, tested on Beagle board. Unscientific benchmark: mplayer -nosound -vo null -quiet -benchmark -loop 12 matrixbench_normdivx_vbrmp3.avi | grep BENCHMARK kernel without l2 cache, at 381MHz: BENCHMARKs: VC: 193.856s VO: 0.153s A: 0.000s Sys: 2.718s = 196.727s kernel with l2 cache at 500MHz: BENCHMARKs: VC: 56.150s VO: 0.133s A: 0.000s Sys: 1.043s = 57.327s mplayer is 2.7 times faster :) > > > Regards, > Khasim > > > --- ../my_linux_omap/arch/arm/mm/Kconfig 2008-05-06 > 16:37:17.000000000 +0530 > +++ arch/arm/mm/Kconfig 2008-05-07 12:40:05.000000000 +0530 > @@ -659,6 +659,20 @@ config CPU_DCACHE_SIZE > If your SoC is configured to have a different size, define > the value > here with proper conditions. > > +choice > + prompt "L2 Cache Size" > + depends on ARCH_OMAP34XX > + > +config CPU_LOCKDOWN_TO_64K_L2 > + bool "Lock down L2 Cache to 64K" > + > +config CPU_LOCKDOWN_TO_128K_L2 > + bool "Lock down L2 Cache to 128K" > + > +config CPU_LOCKDOWN_TO_256K_L2 > + bool "Lock down L2 Cache to 256K" > +endchoice > + > config CPU_DCACHE_WRITETHROUGH > bool "Force write through D-cache" > depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || > CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || > CPU_ARM1020) && !CPU_DCACHE_DISABLE > @@ -674,6 +688,12 @@ config CPU_CACHE_ROUND_ROBIN > Say Y here to use the predictable round-robin cache > replacement > policy. Unless you specifically require this or are > unsure, say N. > > +config CPU_L2CACHE_DISABLE > + bool "Disable level 2 cache" > + depends on CPU_V7 > + help > + Say Y here to disable the level 2 cache. If unsure, say N. > + > config CPU_BPREDICT_DISABLE > bool "Disable branch prediction" > depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 > > --- ../my_linux_omap/arch/arm/mm/proc-v7.S 2008-04-27 > 00:13:57.000000000 +0530 > +++ arch/arm/mm/proc-v7.S 2008-05-07 12:22:29.000000000 +0530 > @@ -182,11 +182,72 @@ __v7_setup: > mov r10, #0x1f @ domains 0, 1 = > manager > mcr p15, 0, r10, c3, c0, 0 @ load domain access > register > #endif > +#if defined(CONFIG_ARCH_OMAP3) > + @ L2 cache is enabled in the aux control register > + mrc p15, 0, r0, c1, c0, 1 > + orr r0, r0, #0x11 @ speculative+no-alais > protection > +#ifdef CONFIG_CPU_L2CACHE_DISABLE > + bic r0, r0, #0x2 @ disable L2 Cache. > +#else > + orr r0, r0, #0x2 @ enaable L2 Cache. > +#endif > + > +/* On 3430 ES2.0 ZeBu and silicon, Aux Ctrl Reg can be written > outside > + * Secure mode also > + */ > + mcr p15, 0, r0, c1, c0, 1 > + > +#ifdef CONFIG_ARCH_OMAP34XX > +#ifdef CONFIG_CPU_LOCKDOWN_TO_64K_L2 > + mov r10, #0xfc > + mcr p15, 1, r10, c9, c0, 0 > +#endif > + > +#ifdef CONFIG_CPU_LOCKDOWN_TO_128K_L2 > + mov r10, #0xf0 > + mcr p15, 1, r10, c9, c0, 0 > +#endif > + > +#ifdef CONFIG_CPU_LOCKDOWN_TO_256K_L2 > + mov r10, #0x00 > + mcr p15, 1, r10, c9, c0, 0 > +#endif > +#endif > + > adr r5, v7_crval > ldmia r5, {r5, r6} > - mrc p15, 0, r0, c1, c0, 0 @ read control > register > - bic r0, r0, r5 @ clear bits them > - orr r0, r0, r6 @ set them > + mrc p15, 0, r0, c1, c0, 0 @ read control register > + bic r0, r0, r5 @ clear bits them > + orr r0, r0, r6 @ set them > + mov pc, lr @ return to head.S:__ret > + > + /* > + * TAT N EV F H R > + * .EFR M.EE .UI. ..A. .RVI Z... B... .CAM > + * 0xxx x0xx 11x0 01x1 0xxx x000 0111 1xxx < forced typical > + * r rr rr r rr r r rrr rrrr r < always > read only > + * .000 ..00 ..0. ..0. .011 1... .... .101 < we want > + */ > + .type v7_crval, #object > +v7_crval: > + crval clear=0x7322f006, mmuset=0x00003805, ucset=0x00001804 > +#else > + > +#ifndef CONFIG_CPU_L2CACHE_DISABLE > + @ L2 cache configuration in the L2 aux control register > + mrc p15, 1, r10, c9, c0, 2 > + bic r10, r10, #(1 << 16) @ L2 outer cache > + mcr p15, 1, r10, c9, c0, 2 > + @ L2 cache is enabled in the aux control register > + mrc p15, 0, r10, c1, c0, 1 > + orr r10, r10, #2 > + mcr p15, 0, r10, c1, c0, 1 > +#endif > + mrc p15, 0, r0, c1, c0, 0 @ read control > register > + ldr r10, cr1_clear @ get mask for bits > to clear > + bic r0, r0, r10 @ clear bits them > + ldr r10, cr1_set @ get mask for bits > to set > + orr r0, r0, r10 @ set them > mov pc, lr @ return to > head.S:__ret > > /* > @@ -195,9 +256,13 @@ __v7_setup: > * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced > * 0 110 0011 1.00 .111 1101 < we want > */ > - .type v7_crval, #object > -v7_crval: > - crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c > + .type cr1_clear, #object > + .type cr1_set, #object > +cr1_clear: > + .word 0x0120c302 > +cr1_set: > + .word 0x00c0387d > +#endif > > __v7_setup_stack: > .space 4 * 11 @ 11 registers > @@ -205,7 +270,6 @@ __v7_setup_stack: > .type v7_processor_functions, #object > ENTRY(v7_processor_functions) > .word v7_early_abort > - .word pabort_ifar > .word cpu_v7_proc_init > .word cpu_v7_proc_fin > .word cpu_v7_reset > @@ -213,6 +277,7 @@ ENTRY(v7_processor_functions) > .word cpu_v7_dcache_clean_area > .word cpu_v7_switch_mm > .word cpu_v7_set_pte_ext > + .word pabort_ifar > .size v7_processor_functions, . - v7_processor_functions > > .type cpu_arch_name, #object > -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFIIYnKMkyGM64RGpERAot4AJ4yGHnYGjMzBUgiPZs8MVI5D6xsfACfc6gl sEIca4auZilcU1ggRjSFVJI= =6IDq -----END PGP SIGNATURE----- ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-06 16:51 ` Woodruff, Richard 2008-05-06 17:01 ` Koen Kooi @ 2008-05-10 8:14 ` Dirk Behme 1 sibling, 0 replies; 21+ messages in thread From: Dirk Behme @ 2008-05-10 8:14 UTC (permalink / raw) To: Woodruff, Richard; +Cc: Koen Kooi, linux-omap Richard, Woodruff, Richard wrote: >>Beagleboard (omap3530) >> >> >>>I'll try the latest from here on SDP with this and see if it works. >>>There is also a difference in CR handling. I had submitted long >>>back a fix to Russell but let it get by me as I didn't have the time >>>to fix per his comments. I think our version was more correct then >>>the one in place but was still lacking a bit. >>> >>>[*] It seems possible you could have an issue depending on what your >>>boot loader is or isn't doing for you. >> >>U-boot (both 1.1.4 and 1.3.2) calls l2disable() before booting linux, >>so linux needs to enable it. I vote for removing the l2disable() in u- >>boot, but I can see that people might be stuck with broken binary >>bootloaders... > > > Yes, this 'might' help for some users if it works. Traditionally things usually have had some complications here at multiple levels in both hardware and software. And yes not everyone can upgrade a boot loader. However, with expanding boot from MMC/SD support things are getting safer. > > The bit I was more worried about was the boot loader may not be invalidating secure L2 tags correctly. The method to do this correctly is a little different between EMU/HS and GP devices. Also these base methods changed some between ES1 and ES2 of the chip. I hope no one is using an ES1 anymore but I'm sure code remnants exist. > > The working code variants did some work in u-boot and some in the kernel to handle these conditions. The current balance today in working variants today has u-boot doing more work. This probably merges with fewer conflicts with the arm-kernel. Last I checked u-boot on Beagle was a based on an older version of the code and probably even a wider range of versions exist in the community. As such it's a good bet some of this is at the root of the problems you are seeing. On Beagle, we use ES2 GP device. From discussion on ARM kernel list [1] we learned that it's the job of bootloader to initialize L2 cache correctly. Thanks to Khasim we have a patch to enable L2 cache in kernel [2], but this is only to work around "broken" bootloaders. So, we need fixed bootloader (e.g. U-Boot) doing L2 cache initialization correctly. Currently, in U-Boot used for Beagle we have the following (L2) cache handling (cleaned up for easier reading). Do you think this is correct? Can we simply add a l2cache_enable() at the end of following code or do we have to do/fix/change more to pass correctly configured caches from U-Boot to kernel? -- cut -- At U-Boot start: l2cache_enable() for CPU_3430_ES2: __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); ... do U-Boot work ... then just before kernel is called: cleanup_before_linux(): /* turn off I/D-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~(C1_DC | C1_IC); asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); /* invalidate I-cache */ mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache /* turn off L2 cache */ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()): mov r7, r0 @ take a backup of device type cmp r0, #0x3 @ check if the device type is GP moveq r12, #0x1 @ set up to invalide L2 smi: .word 0x01600070 @ Call SMI monitor (smieq) cmp r7, #0x3 @ compare again in case its lost beq finished_inval @ if GP device, inval done above mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field beq finished_inval @ if loc is 0, then no need to clean mov r10, #0 @ start clean at cache level 0 inval_loop1: add r2, r10, r10, lsr #1 @ work out 3x current cache level mov r1, r0, lsr r2 @ extract cache type bits from clidr and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip_inval @ skip if no cache, or just i-cache mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff ands r4, r4, r1, lsr #3 @ find maximum number on the way size clz r5, r4 @ find bit position of way size increment ldr r7, =0x7fff ands r7, r7, r1, lsr #13 @ extract max number of the index size inval_loop2: mov r9, r4 @ create working copy of max way size inval_loop3: orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 orr r11, r11, r7, lsl r2 @ factor index number into r11 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way subs r9, r9, #1 @ decrement the way bge inval_loop3 subs r7, r7, #1 @ decrement the index bge inval_loop2 skip_inval: add r10, r10, #2 @ increment cache number cmp r3, r10 bgt inval_loop1 finished_inval: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb i = 0; /* mem barrier to sync up things */ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); ??? Insert here l2cache_enable() ??? ... Start kernel -- cut -- Many thanks and best regards Dirk [1] http://lists.arm.linux.org.uk/lurker/message/20080506.204317.a16f4c73.en.html [2] http://marc.info/?l=linux-omap&m=121014615706359&w=2 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: public git l2 cache off. 2008-05-06 15:06 ` Woodruff, Richard 2008-05-06 16:20 ` Koen Kooi @ 2008-05-06 18:13 ` Dirk Behme 1 sibling, 0 replies; 21+ messages in thread From: Dirk Behme @ 2008-05-06 18:13 UTC (permalink / raw) To: Woodruff, Richard; +Cc: Koen Kooi, linux-omap Woodruff, Richard wrote: >>Enabling L2 cache was removed from proc-v7.S since was cortex specific >>instead of armv7 specific and u-boot explicitly turns of L2 before >>booting into linux. I made a reverse patch, but my omap3 board doesn't >>boot if I use it: > > > Our 2.6.24 kernel does something close and boots fine on OMAP3-SDP and Labrador boards. Which platform did you try on? I think we are talking about BeagleBoard here. Dirk > I'll try the latest from here on SDP with this and see if it works. There is also a difference in CR handling. I had submitted long back a fix to Russell but let it get by me as I didn't have the time to fix per his comments. I think our version was more correct then the one in place but was still lacking a bit. > > [*] It seems possible you could have an issue depending on what your boot loader is or isn't doing for you. > > Regards, > Richard W. > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2008-05-16 17:34 UTC | newest] Thread overview: 21+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2008-04-30 17:13 [PATCH 0/3] DMA clean-up for multi-boot Tony Lindgren 2008-04-30 17:13 ` [PATCH 1/3] ARM: OMAP: Make DMA channels dynamic " Tony Lindgren 2008-04-30 17:14 ` [PATCH 2/3] ARM: OMAP: Remove __REG access in DMA code Tony Lindgren 2008-04-30 17:14 ` [PATCH 3/3] ARM: OMAP: DMA clean-up Tony Lindgren 2008-04-30 18:00 ` [PATCH 0/3] DMA clean-up for multi-boot Gadiyar, Anand 2008-05-02 15:15 ` Gadiyar, Anand 2008-05-02 18:11 ` Tony Lindgren 2008-05-16 17:34 ` Tony Lindgren 2008-05-05 10:14 ` Jarkko Nikula 2008-05-05 23:27 ` public git l2 cache off Woodruff, Richard 2008-05-06 5:38 ` Koen Kooi 2008-05-06 6:58 ` Koen Kooi 2008-05-06 15:06 ` Woodruff, Richard 2008-05-06 16:20 ` Koen Kooi 2008-05-06 16:51 ` Woodruff, Richard 2008-05-06 17:01 ` Koen Kooi 2008-05-06 21:25 ` Tony Lindgren 2008-05-07 7:42 ` Syed Mohammed, Khasim 2008-05-07 10:51 ` Koen Kooi 2008-05-10 8:14 ` Dirk Behme 2008-05-06 18:13 ` Dirk Behme
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