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From: Catalin Marinas <catalin.marinas@arm.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: "Woodruff, Richard" <r-woodruff2@ti.com>,
	Paul Walmsley <paul@pwsan.com>,
	"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
	"linux-arm-kernel@lists.arm.linux.org.uk"
	<linux-arm-kernel@lists.arm.linux.org.uk>
Subject: Re: [PATCH] ARM MMU: add strongly-ordered memory type
Date: Fri, 08 Aug 2008 17:40:06 +0100	[thread overview]
Message-ID: <1218213606.12256.74.camel@pc1117.cambridge.arm.com> (raw)
In-Reply-To: <20080808131930.GB8643@flint.arm.linux.org.uk>

On Fri, 2008-08-08 at 14:19 +0100, Russell King - ARM Linux wrote:
> On Fri, Aug 08, 2008 at 12:44:49PM +0100, Catalin Marinas wrote:
> > I need to check in ARM when people come from holidays but a simple LDR
> > might not be enough to guarantee that a CPSIE etc. happens after it. You
> > may need to add either an LDR + CMP (or some other usage of the loaded
> > register) or LDR + DSB. I agree that DSB alone is not enough.
> 
> Okay, I give up on this issue.  Weak memory ordering seems to be a
> very very big can of worms.  And then there's this:
> 
> 14:07 < rmk> so we're back to making readl() itself do something with the
>              data... which brings us back to that question about why bother
>              with weak ordering
> 14:10 < willy> you can't have weak ordering for device control registers
> 14:11 < rmk> yes you can, provided they're ordered wrt each other.
> 14:11 < willy> weak ordering works great for SMP or for just covering up latency
> 14:12 < willy> no, you can't.  see writel(); readl(); udelay(1); writel();.
>                You didn't wait for 1 microsecond before accessing the device
>                again.
> 
> Or, to put it another way, it seems that on Linux _all_ devices must
> be strongly ordered or be seen to Linux as being strongly ordered
> (iow, readl and writel and friends _must_ have a barrier.)

Why not put a barrier in udelay? The delay functions are mainly used for
device access.

> TBH, this is becoming soo much of a joke, it's untrue.

For performance in a multi-stage pipeline model, you need weaker
ordering. I'm not a hardware engineer to comment more on this.

> Let's go back to having a strongly ordered memory model.  Please.

On pre-ARMv6, updates to CPSR are guaranteed to take place in program
order with a strongly-ordered memory access. This is still true on
ARMv6/v7 for backward compatibility but the feature is deprecated and it
might not be true for future architecture versions. At some point
barriers might be needed.

-- 
Catalin


  reply	other threads:[~2008-08-08 16:40 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-08-04 23:40 [PATCH] ARM MMU: add strongly-ordered memory type Paul Walmsley
2008-08-05 11:49 ` Ben Dooks
2008-08-05 12:15   ` Woodruff, Richard
2008-08-06 10:20     ` Catalin Marinas
2008-08-06 12:28       ` Woodruff, Richard
2008-08-07 16:55         ` Catalin Marinas
2008-08-07  6:01       ` Paul Walmsley
2008-08-07 16:45         ` Catalin Marinas
2008-08-08  8:45           ` Paul Walmsley
2008-08-06  9:53 ` Catalin Marinas
2008-08-06 12:21   ` Woodruff, Richard
2008-08-07  7:30     ` Russell King - ARM Linux
2008-08-07 16:01       ` Catalin Marinas
2008-08-07 18:56       ` Woodruff, Richard
2008-08-07 19:25         ` Russell King - ARM Linux
2008-08-07 20:38           ` Woodruff, Richard
2008-08-07 21:20             ` Russell King - ARM Linux
2008-08-07 21:59               ` Russell King - ARM Linux
2008-08-07 23:07               ` Woodruff, Richard
2008-08-08  7:16                 ` Russell King - ARM Linux
2008-08-08 11:44               ` Catalin Marinas
2008-08-08 13:19                 ` Russell King - ARM Linux
2008-08-08 16:40                   ` Catalin Marinas [this message]
2008-08-11  7:50                 ` Paul Walmsley

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