* [PATCH v2 00/20] dspbridge cleanups
@ 2009-11-30 21:54 Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Omar Ramirez Luna
2009-12-01 6:49 ` [PATCH v2 00/20] dspbridge cleanups Andy Shevchenko
0 siblings, 2 replies; 28+ messages in thread
From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw)
To: linux-omap
Cc: Omar Ramirez Luna, Artem Bityutskiy, Felipe Balbi,
Felipe Contreras, Hiroshi Doyu, Nishant Menon
These are the split versions of the v1 patches for cleanup.
Added driver version, a tag is going to be created (dspbridge-v0.1)
to match this patch.
Comments for functions will be cleaned in a different patch series,
along with regular multiline comment fixes.
Ioctls, deprecated and not implemented, will be clenaed when the big
ioctl switch replaces the WCD function table.
CC: Artem Bityutskiy <dedekind1@gmail.com>
CC: Felipe Balbi <felipe.balbi@nokia.com>
CC: Felipe Contreras <felipe.contreras@gmail.com>
CC: Hiroshi Doyu <Hiroshi.DOYU@nokia.com>
CC: Nishant Menon <nm@ti.com>
Omar Ramirez Luna (20):
DSPBRIDGE: driver version 0.1
DSPBRIDGE: trivial license fix in tramp and tramp_table_c6000
DSPBRIDGE: trivial file history cleanup for headers
DSPBRIDGE: trivial file history cleanup for driver sources
DSPBRIDGE: checkpatch - space required after comma
DSPBRIDGE: checkpatch - space required before open parenthesis
DSPBRIDGE: checkpatch spacing and indentation
DSPBRIDGE: Checkpatch - line over 80 characters
DSPBRIDGE: checkpatch - printk() should include KERN_ facility level
DSPBRIDGE: checkpatch - braces not necessary for single statement
blocks
DSPBRIDGE: checkpatch - struct file_operations should normally be
const
DSPBRIDGE: checkpatch foo-should-be for pointers
DSPBRIDGE: Fix multiline macros to use do while
DSPBRIDGE: Use _IOxx macro to define ioctls
DSPBRIDGE: trivial cleanup and indentation for io_sm
DSPBRIDGE: trivial fix for multiline comments on io_sm
DSPBRIDGE: Remove DPC, create, destroy and schedule wrappers
DSPBRIDGE: Remove main DPC wrapper for IO and MMUfault
DSPBRIDGE: Remove DPC module from SERVICES layer
DSPBRIDGE: Remove DPC object structure
arch/arm/plat-omap/include/dspbridge/_chnl_sm.h | 47 +-
arch/arm/plat-omap/include/dspbridge/_dcd.h | 40 +-
arch/arm/plat-omap/include/dspbridge/brddefs.h | 18 +-
arch/arm/plat-omap/include/dspbridge/cfg.h | 50 +-
arch/arm/plat-omap/include/dspbridge/cfgdefs.h | 27 +-
arch/arm/plat-omap/include/dspbridge/chnl.h | 45 +-
arch/arm/plat-omap/include/dspbridge/chnl_sm.h | 30 +-
arch/arm/plat-omap/include/dspbridge/chnldefs.h | 26 +-
arch/arm/plat-omap/include/dspbridge/chnlpriv.h | 33 +-
arch/arm/plat-omap/include/dspbridge/clk.h | 11 +-
arch/arm/plat-omap/include/dspbridge/cmm.h | 66 +-
arch/arm/plat-omap/include/dspbridge/cmmdefs.h | 20 +-
arch/arm/plat-omap/include/dspbridge/cod.h | 58 +-
arch/arm/plat-omap/include/dspbridge/dbc.h | 40 +-
arch/arm/plat-omap/include/dspbridge/dbdcd.h | 26 +-
arch/arm/plat-omap/include/dspbridge/dbdcddef.h | 27 +-
arch/arm/plat-omap/include/dspbridge/dbdefs.h | 61 +-
arch/arm/plat-omap/include/dspbridge/dbg.h | 25 +-
arch/arm/plat-omap/include/dspbridge/dbl.h | 14 -
arch/arm/plat-omap/include/dspbridge/dbldefs.h | 12 -
arch/arm/plat-omap/include/dspbridge/dbll.h | 15 +-
arch/arm/plat-omap/include/dspbridge/dblldefs.h | 11 -
arch/arm/plat-omap/include/dspbridge/dbtype.h | 21 +-
arch/arm/plat-omap/include/dspbridge/dehdefs.h | 14 +-
arch/arm/plat-omap/include/dspbridge/dev.h | 64 +-
arch/arm/plat-omap/include/dspbridge/devdefs.h | 15 +-
arch/arm/plat-omap/include/dspbridge/disp.h | 31 +-
arch/arm/plat-omap/include/dspbridge/dispdefs.h | 14 +-
arch/arm/plat-omap/include/dspbridge/dmm.h | 18 +-
arch/arm/plat-omap/include/dspbridge/dpc.h | 167 ---
arch/arm/plat-omap/include/dspbridge/drv.h | 48 +-
arch/arm/plat-omap/include/dspbridge/drvdefs.h | 13 +-
arch/arm/plat-omap/include/dspbridge/dspdrv.h | 33 +-
.../plat-omap/include/dspbridge/dynamic_loader.h | 2 -
arch/arm/plat-omap/include/dspbridge/errbase.h | 37 +-
arch/arm/plat-omap/include/dspbridge/gb.h | 10 +-
arch/arm/plat-omap/include/dspbridge/getsection.h | 21 +-
arch/arm/plat-omap/include/dspbridge/gh.h | 8 -
arch/arm/plat-omap/include/dspbridge/gs.h | 15 +-
arch/arm/plat-omap/include/dspbridge/gt.h | 27 +-
arch/arm/plat-omap/include/dspbridge/host_os.h | 10 -
arch/arm/plat-omap/include/dspbridge/io.h | 21 +-
arch/arm/plat-omap/include/dspbridge/io_sm.h | 46 +-
arch/arm/plat-omap/include/dspbridge/iodefs.h | 13 +-
arch/arm/plat-omap/include/dspbridge/ldr.h | 34 +-
arch/arm/plat-omap/include/dspbridge/list.h | 36 +-
arch/arm/plat-omap/include/dspbridge/mbx_sh.h | 25 +-
arch/arm/plat-omap/include/dspbridge/mem.h | 78 +-
arch/arm/plat-omap/include/dspbridge/memdefs.h | 16 +-
arch/arm/plat-omap/include/dspbridge/mgr.h | 32 +-
arch/arm/plat-omap/include/dspbridge/mgrpriv.h | 14 +-
arch/arm/plat-omap/include/dspbridge/msg.h | 24 +-
arch/arm/plat-omap/include/dspbridge/msgdefs.h | 15 +-
arch/arm/plat-omap/include/dspbridge/nldr.h | 29 +-
arch/arm/plat-omap/include/dspbridge/nldrdefs.h | 14 +-
arch/arm/plat-omap/include/dspbridge/node.h | 48 +-
arch/arm/plat-omap/include/dspbridge/nodedefs.h | 16 +-
arch/arm/plat-omap/include/dspbridge/nodepriv.h | 23 +-
arch/arm/plat-omap/include/dspbridge/ntfy.h | 22 +-
arch/arm/plat-omap/include/dspbridge/proc.h | 47 +-
arch/arm/plat-omap/include/dspbridge/procpriv.h | 13 +-
arch/arm/plat-omap/include/dspbridge/pwr.h | 19 -
arch/arm/plat-omap/include/dspbridge/pwr_sh.h | 12 +-
arch/arm/plat-omap/include/dspbridge/reg.h | 35 +-
arch/arm/plat-omap/include/dspbridge/rmm.h | 26 +-
arch/arm/plat-omap/include/dspbridge/rms_sh.h | 34 +-
arch/arm/plat-omap/include/dspbridge/rmstypes.h | 15 +-
arch/arm/plat-omap/include/dspbridge/services.h | 17 +-
arch/arm/plat-omap/include/dspbridge/std.h | 48 -
arch/arm/plat-omap/include/dspbridge/strm.h | 41 +-
arch/arm/plat-omap/include/dspbridge/strmdefs.h | 14 +-
arch/arm/plat-omap/include/dspbridge/sync.h | 40 +-
arch/arm/plat-omap/include/dspbridge/utildefs.h | 16 +-
arch/arm/plat-omap/include/dspbridge/uuidutil.h | 16 +-
arch/arm/plat-omap/include/dspbridge/wcd.h | 49 +-
arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 200 ++---
arch/arm/plat-omap/include/dspbridge/wmd.h | 57 +-
arch/arm/plat-omap/include/dspbridge/wmdchnl.h | 29 +-
arch/arm/plat-omap/include/dspbridge/wmddeh.h | 30 +-
arch/arm/plat-omap/include/dspbridge/wmdio.h | 24 +-
arch/arm/plat-omap/include/dspbridge/wmdioctl.h | 26 +-
arch/arm/plat-omap/include/dspbridge/wmdmsg.h | 27 +-
drivers/dsp/bridge/Makefile | 3 +-
drivers/dsp/bridge/dynload/dlclasses_hdr.h | 2 -
drivers/dsp/bridge/dynload/dload_internal.h | 2 -
drivers/dsp/bridge/dynload/doff.h | 17 +-
drivers/dsp/bridge/dynload/getsection.c | 2 -
drivers/dsp/bridge/dynload/header.h | 2 -
drivers/dsp/bridge/dynload/module_list.h | 82 +-
drivers/dsp/bridge/dynload/params.h | 43 +-
drivers/dsp/bridge/dynload/reloc.c | 29 +-
drivers/dsp/bridge/dynload/reloc_table.h | 2 -
drivers/dsp/bridge/dynload/reloc_table_c6000.c | 1 -
drivers/dsp/bridge/dynload/tramp.c | 18 +-
drivers/dsp/bridge/dynload/tramp_table_c6000.c | 18 +-
drivers/dsp/bridge/gen/_gt_para.c | 24 +-
drivers/dsp/bridge/gen/gb.c | 17 +-
drivers/dsp/bridge/gen/gh.c | 5 -
drivers/dsp/bridge/gen/gs.c | 20 +-
drivers/dsp/bridge/gen/gt.c | 16 +-
drivers/dsp/bridge/gen/uuidutil.c | 20 +-
drivers/dsp/bridge/hw/GlobalTypes.h | 16 +-
drivers/dsp/bridge/hw/IVA2RegAcM.h | 2 -
drivers/dsp/bridge/hw/MLBAccInt.h | 1 -
drivers/dsp/bridge/hw/MLBRegAcM.h | 319 +++---
drivers/dsp/bridge/hw/MMURegAcM.h | 416 ++++----
drivers/dsp/bridge/hw/PRCMRegAcM.h | 1197 +++++++++-----------
drivers/dsp/bridge/hw/hw_defs.h | 13 +-
drivers/dsp/bridge/hw/hw_dspssC64P.c | 13 +-
drivers/dsp/bridge/hw/hw_dspssC64P.h | 15 +-
drivers/dsp/bridge/hw/hw_mbox.c | 13 +-
drivers/dsp/bridge/hw/hw_mbox.h | 55 +-
drivers/dsp/bridge/hw/hw_mmu.c | 17 +-
drivers/dsp/bridge/hw/hw_mmu.h | 15 +-
drivers/dsp/bridge/hw/hw_prcm.c | 12 +-
drivers/dsp/bridge/hw/hw_prcm.h | 12 +-
drivers/dsp/bridge/pmgr/chnl.c | 52 +-
drivers/dsp/bridge/pmgr/chnlobj.h | 21 +-
drivers/dsp/bridge/pmgr/cmm.c | 106 +--
drivers/dsp/bridge/pmgr/cod.c | 51 +-
drivers/dsp/bridge/pmgr/dbll.c | 65 +-
drivers/dsp/bridge/pmgr/dev.c | 102 +--
drivers/dsp/bridge/pmgr/dmm.c | 47 +-
drivers/dsp/bridge/pmgr/io.c | 25 +-
drivers/dsp/bridge/pmgr/ioobj.h | 19 +-
drivers/dsp/bridge/pmgr/msg.c | 23 +-
drivers/dsp/bridge/pmgr/msgobj.h | 19 +-
drivers/dsp/bridge/pmgr/wcd.c | 211 ++---
drivers/dsp/bridge/rmgr/dbdcd.c | 56 +-
drivers/dsp/bridge/rmgr/disp.c | 39 +-
drivers/dsp/bridge/rmgr/drv.c | 102 +--
drivers/dsp/bridge/rmgr/drv_interface.c | 50 +-
drivers/dsp/bridge/rmgr/drv_interface.h | 12 -
drivers/dsp/bridge/rmgr/dspdrv.c | 79 +--
drivers/dsp/bridge/rmgr/mgr.c | 30 +-
drivers/dsp/bridge/rmgr/nldr.c | 66 +-
drivers/dsp/bridge/rmgr/node.c | 289 ++---
drivers/dsp/bridge/rmgr/proc.c | 102 +--
drivers/dsp/bridge/rmgr/pwr.c | 19 +-
drivers/dsp/bridge/rmgr/rmm.c | 14 -
drivers/dsp/bridge/rmgr/strm.c | 49 +-
drivers/dsp/bridge/services/cfg.c | 78 +--
drivers/dsp/bridge/services/clk.c | 25 +-
drivers/dsp/bridge/services/dbg.c | 35 +-
drivers/dsp/bridge/services/dpc.c | 274 -----
drivers/dsp/bridge/services/list.c | 33 -
drivers/dsp/bridge/services/mem.c | 40 +-
drivers/dsp/bridge/services/ntfy.c | 27 +-
drivers/dsp/bridge/services/reg.c | 21 +-
drivers/dsp/bridge/services/regsup.c | 30 +-
drivers/dsp/bridge/services/regsup.h | 8 -
drivers/dsp/bridge/services/services.c | 30 +-
drivers/dsp/bridge/services/sync.c | 35 +-
drivers/dsp/bridge/wmd/_cmm.h | 22 +-
drivers/dsp/bridge/wmd/_deh.h | 18 +-
drivers/dsp/bridge/wmd/_msg_sm.h | 21 +-
drivers/dsp/bridge/wmd/_tiomap.h | 63 +-
drivers/dsp/bridge/wmd/_tiomap_mmu.h | 16 +-
drivers/dsp/bridge/wmd/_tiomap_pwr.h | 13 +-
drivers/dsp/bridge/wmd/_tiomap_util.h | 13 +-
drivers/dsp/bridge/wmd/chnl_sm.c | 77 +--
drivers/dsp/bridge/wmd/io_sm.c | 978 +++++++++--------
drivers/dsp/bridge/wmd/mmu_fault.c | 34 +-
drivers/dsp/bridge/wmd/mmu_fault.h | 16 +-
drivers/dsp/bridge/wmd/msg_sm.c | 107 +--
drivers/dsp/bridge/wmd/tiomap3430.c | 37 +-
drivers/dsp/bridge/wmd/tiomap3430_pwr.c | 41 +-
drivers/dsp/bridge/wmd/tiomap_io.c | 17 +-
drivers/dsp/bridge/wmd/tiomap_io.h | 14 +-
drivers/dsp/bridge/wmd/tiomap_sm.c | 11 +-
drivers/dsp/bridge/wmd/ue_deh.c | 61 +-
171 files changed, 2490 insertions(+), 6403 deletions(-)
delete mode 100644 arch/arm/plat-omap/include/dspbridge/dpc.h
delete mode 100644 drivers/dsp/bridge/services/dpc.c
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 2009-11-30 21:54 [PATCH v2 00/20] dspbridge cleanups Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 02/20] DSPBRIDGE: trivial license fix in tramp and tramp_table_c6000 Omar Ramirez Luna 2009-12-02 10:57 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Felipe Contreras 2009-12-01 6:49 ` [PATCH v2 00/20] dspbridge cleanups Andy Shevchenko 1 sibling, 2 replies; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap Cc: Omar Ramirez Luna, Artem Bityutskiy, Felipe Contreras, Hiroshi Doyu Prior to any further modification set the driver version to be 0.1 Also in this patch: - Move author and license macros to end of file - License to be GPL v2 as stated on the comments Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Artem Bityutskiy <dedekind1@gmail.com> CC: Felipe Contreras <felipe.contreras@gmail.com> CC: Hiroshi Doyu <Hiroshi.DOYU@nokia.com> --- drivers/dsp/bridge/rmgr/drv_interface.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c index 65ac1e7..9ddd637 100644 --- a/drivers/dsp/bridge/rmgr/drv_interface.c +++ b/drivers/dsp/bridge/rmgr/drv_interface.c @@ -188,9 +188,6 @@ MODULE_PARM_DESC(tc_wordswapon, "TC Word Swap Option. default = 0"); module_param(min_active_opp, ushort, S_IRUSR | S_IWUSR); MODULE_PARM_DESC(min_active_opp, "Minimum ACTIVE VDD1 OPP Level, default = 3"); -MODULE_AUTHOR("Texas Instruments"); -MODULE_LICENSE("GPL"); - static char *driver_name = DRIVER_NAME; #ifdef CONFIG_BRIDGE_DEBUG @@ -731,3 +728,6 @@ static void bridge_destroy_sysfs(void) module_init(bridge_init); module_exit(bridge_exit); +MODULE_AUTHOR("Texas Instruments"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("0.1"); -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 02/20] DSPBRIDGE: trivial license fix in tramp and tramp_table_c6000 2009-11-30 21:54 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna [not found] ` <1259618101-8972-4-git-send-email-omar.ramirez@ti.com> 2009-12-02 10:57 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Felipe Contreras 1 sibling, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna Seems that these files had a licensing mismatch, changing to GPL2. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- drivers/dsp/bridge/dynload/tramp.c | 18 +++++++++++++----- drivers/dsp/bridge/dynload/tramp_table_c6000.c | 18 +++++++++++++----- 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/dsp/bridge/dynload/tramp.c b/drivers/dsp/bridge/dynload/tramp.c index 8c725c7..c2fe02d 100644 --- a/drivers/dsp/bridge/dynload/tramp.c +++ b/drivers/dsp/bridge/dynload/tramp.c @@ -1,11 +1,19 @@ /* - * Copyright 2009 by Texas Instruments Incorporated. - * All rights reserved. Property of Texas Instruments Incorporated. - * Restricted rights to use, duplicate or disclose this code are - * granted through contract. + * tramp.c * - * @(#) DSP/BIOS Bridge + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ + #include "header.h" #if TMS32060 diff --git a/drivers/dsp/bridge/dynload/tramp_table_c6000.c b/drivers/dsp/bridge/dynload/tramp_table_c6000.c index 1a7d974..acda513 100644 --- a/drivers/dsp/bridge/dynload/tramp_table_c6000.c +++ b/drivers/dsp/bridge/dynload/tramp_table_c6000.c @@ -1,11 +1,19 @@ /* - * Copyright 2009 by Texas Instruments Incorporated. - * All rights reserved. Property of Texas Instruments Incorporated. - * Restricted rights to use, duplicate or disclose this code are - * granted through contract. + * tramp_table_c6000.c * - * @(#) DSP/BIOS Bridge + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2005-2006 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ + #include "dload_internal.h" /* These are defined in coff.h, but may not be available on all platforms -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
[parent not found: <1259618101-8972-4-git-send-email-omar.ramirez@ti.com>]
[parent not found: <1259618101-8972-5-git-send-email-omar.ramirez@ti.com>]
* [PATCH v2 05/20] DSPBRIDGE: checkpatch - space required after comma [not found] ` <1259618101-8972-5-git-send-email-omar.ramirez@ti.com> @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 06/20] DSPBRIDGE: checkpatch - space required before open parenthesis Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon ERROR: space required after that ',' (ctx:VxV) Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- drivers/dsp/bridge/hw/GlobalTypes.h | 4 ++-- drivers/dsp/bridge/hw/PRCMRegAcM.h | 24 ++++++++++++------------ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/dsp/bridge/hw/GlobalTypes.h b/drivers/dsp/bridge/hw/GlobalTypes.h index 6f54589..73a2d93 100644 --- a/drivers/dsp/bridge/hw/GlobalTypes.h +++ b/drivers/dsp/bridge/hw/GlobalTypes.h @@ -101,7 +101,7 @@ * DESCRIPTION: Returns a 32 bit value given a 16 bit lower value and a 16 * bit upper value */ -#define RETURN_32BITS_FROM_16LOWER_AND_16UPPER(lower16Bits,upper16Bits)\ +#define RETURN_32BITS_FROM_16LOWER_AND_16UPPER(lower16Bits, upper16Bits)\ (((((u32)lower16Bits) & LOWER_16BIT_MASK)) | \ (((((u32)upper16Bits) & LOWER_16BIT_MASK) << UPPER_16BIT_SHIFT))) @@ -111,7 +111,7 @@ * DESCRIPTION: Returns a 16 bit value given a 8 bit lower value and a 8 * bit upper value */ -#define RETURN_16BITS_FROM_8LOWER_AND_8UPPER(lower8Bits,upper8Bits)\ +#define RETURN_16BITS_FROM_8LOWER_AND_8UPPER(lower8Bits, upper8Bits)\ (((((u32)lower8Bits) & LOWER_8BIT_MASK)) | \ (((((u32)upper8Bits) & LOWER_8BIT_MASK) << UPPER_8BIT_OF16_SHIFT))) diff --git a/drivers/dsp/bridge/hw/PRCMRegAcM.h b/drivers/dsp/bridge/hw/PRCMRegAcM.h index 280a812..4c9d732 100644 --- a/drivers/dsp/bridge/hw/PRCMRegAcM.h +++ b/drivers/dsp/bridge/hw/PRCMRegAcM.h @@ -51,7 +51,7 @@ __raw_readl(((u32)(baseAddress))+CM_ICLKEN_PER_OFFSET)) -#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress,value)\ +#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress, value)\ {\ const u32 offset = CM_FCLKEN_PER_OFFSET;\ register u32 data = \ @@ -66,7 +66,7 @@ } -#define CM_FCLKEN_PER_GPT6WriteRegister32(baseAddress,value)\ +#define CM_FCLKEN_PER_GPT6WriteRegister32(baseAddress, value)\ {\ const u32 offset = CM_FCLKEN_PER_OFFSET;\ register u32 data =\ @@ -81,7 +81,7 @@ } -#define CM_ICLKEN_PER_GPT5WriteRegister32(baseAddress,value)\ +#define CM_ICLKEN_PER_GPT5WriteRegister32(baseAddress, value)\ {\ const u32 offset = CM_ICLKEN_PER_OFFSET;\ register u32 data = \ @@ -96,7 +96,7 @@ } -#define CM_ICLKEN_PER_GPT6WriteRegister32(baseAddress,value)\ +#define CM_ICLKEN_PER_GPT6WriteRegister32(baseAddress, value)\ {\ const u32 offset = CM_ICLKEN_PER_OFFSET;\ register u32 data = \ @@ -116,7 +116,7 @@ __raw_readl(((u32)(baseAddress))+CM_FCLKEN1_CORE_OFFSET)) -#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress,value)\ +#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress, value)\ {\ const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\ register u32 data = \ @@ -131,7 +131,7 @@ } -#define PRCMCM_FCLKEN1_COREEN_GPT7Write32(baseAddress,value)\ +#define PRCMCM_FCLKEN1_COREEN_GPT7Write32(baseAddress, value)\ {\ const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\ register u32 data = \ @@ -360,7 +360,7 @@ PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET)) -#define CM_FCLKEN_IVA2EN_DSPWrite32(baseAddress,value)\ +#define CM_FCLKEN_IVA2EN_DSPWrite32(baseAddress, value)\ {\ const u32 offset = CM_FCLKEN_IVA2_OFFSET;\ register u32 data = \ @@ -426,7 +426,7 @@ } -#define PRCMCM_CLKSEL_DSPSYNC_DSPWrite32(baseAddress,value)\ +#define PRCMCM_CLKSEL_DSPSYNC_DSPWrite32(baseAddress, value)\ {\ const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\ register u32 data = \ @@ -514,7 +514,7 @@ __raw_readl(((baseAddress))+PRCM_RM_RSTCTRL_DSP_OFFSET)) -#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress,value)\ +#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, value)\ {\ const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\ register u32 data =\ @@ -529,7 +529,7 @@ } -#define PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress,value)\ +#define PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, value)\ {\ const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\ register u32 data =\ @@ -544,7 +544,7 @@ } -#define PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress,value)\ +#define PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, value)\ {\ const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\ register u32 data =\ @@ -564,7 +564,7 @@ __raw_readl(((baseAddress))+PRCM_RM_RSTST_DSP_OFFSET)) -#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress,value)\ +#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress, value)\ {\ const u32 offset = PRCM_RM_RSTST_DSP_OFFSET;\ register u32 newValue = ((u32)(value));\ -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 06/20] DSPBRIDGE: checkpatch - space required before open parenthesis 2009-11-30 21:54 ` [PATCH v2 05/20] DSPBRIDGE: checkpatch - space required after comma Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 07/20] DSPBRIDGE: checkpatch spacing and indentation Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon ERROR: space required before the open parenthesis '(' Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- drivers/dsp/bridge/pmgr/dev.c | 2 +- drivers/dsp/bridge/services/dbg.c | 2 +- drivers/dsp/bridge/wmd/io_sm.c | 4 ++-- drivers/dsp/bridge/wmd/msg_sm.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dsp/bridge/pmgr/dev.c b/drivers/dsp/bridge/pmgr/dev.c index a9cce95..5c5e056 100644 --- a/drivers/dsp/bridge/pmgr/dev.c +++ b/drivers/dsp/bridge/pmgr/dev.c @@ -441,7 +441,7 @@ DSP_STATUS DEV_DestroyDevice(struct DEV_OBJECT *hDevObject) /* Call the driver's WMD_DEV_Destroy() function: */ /* Require of DevDestroy */ - if(pDevObject->hWmdContext) { + if (pDevObject->hWmdContext) { status = (*pDevObject->intfFxns.pfnDevDestroy) (pDevObject->hWmdContext); pDevObject->hWmdContext = NULL; diff --git a/drivers/dsp/bridge/services/dbg.c b/drivers/dsp/bridge/services/dbg.c index bc57fa8..bc5c8cd 100644 --- a/drivers/dsp/bridge/services/dbg.c +++ b/drivers/dsp/bridge/services/dbg.c @@ -33,7 +33,7 @@ static struct GT_Mask DBG_debugMask = { NULL, NULL }; /* GT trace var. */ #endif -#if (defined(DEBUG) || defined (DDSP_DEBUG_PRODUCT)) && GT_TRACE +#if (defined(DEBUG) || defined(DDSP_DEBUG_PRODUCT)) && GT_TRACE /* * ======== DBG_Init ======== diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index 396a10b..746689d 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -201,7 +201,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, * size of message buffer in shared memory is configurable in * the base image. */ DEV_GetWMDContext(hDevObject, &hWmdContext); - if(!hWmdContext) { + if (!hWmdContext) { status = DSP_EHANDLE; goto func_end; } @@ -1106,7 +1106,7 @@ func_end: */ void IO_Schedule(struct IO_MGR *pIOMgr) { - if(!MEM_IsValidHandle(pIOMgr, IO_MGRSIGNATURE)) + if (!MEM_IsValidHandle(pIOMgr, IO_MGRSIGNATURE)) return; tiomap3430_bump_dsp_opp_level(); DPC_Schedule(pIOMgr->hDPC); diff --git a/drivers/dsp/bridge/wmd/msg_sm.c b/drivers/dsp/bridge/wmd/msg_sm.c index c29b64e..ad716ab 100644 --- a/drivers/dsp/bridge/wmd/msg_sm.c +++ b/drivers/dsp/bridge/wmd/msg_sm.c @@ -65,7 +65,7 @@ DSP_STATUS WMD_MSG_Create(OUT struct MSG_MGR **phMsgMgr, goto func_end; } DEV_GetIOMgr(hDevObject, &hIOMgr); - if(!hIOMgr) { + if (!hIOMgr) { status = DSP_EPOINTER; goto func_end; } -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 07/20] DSPBRIDGE: checkpatch spacing and indentation 2009-11-30 21:54 ` [PATCH v2 06/20] DSPBRIDGE: checkpatch - space required before open parenthesis Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 08/20] DSPBRIDGE: Checkpatch - line over 80 characters Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon ERROR: code indent should use tabs where possible WARNING: suspect code indent for conditional statements Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- arch/arm/plat-omap/include/dspbridge/_chnl_sm.h | 2 +- arch/arm/plat-omap/include/dspbridge/chnlpriv.h | 2 +- arch/arm/plat-omap/include/dspbridge/dbdefs.h | 6 +- arch/arm/plat-omap/include/dspbridge/io_sm.h | 6 +- drivers/dsp/bridge/dynload/reloc.c | 29 +- drivers/dsp/bridge/hw/hw_mbox.h | 44 +-- drivers/dsp/bridge/pmgr/cod.c | 4 +- drivers/dsp/bridge/pmgr/dbll.c | 45 ++-- drivers/dsp/bridge/rmgr/disp.c | 4 +- drivers/dsp/bridge/rmgr/drv.c | 24 +- drivers/dsp/bridge/rmgr/drv_interface.c | 10 +- drivers/dsp/bridge/rmgr/nldr.c | 28 +- drivers/dsp/bridge/rmgr/node.c | 205 ++++++------ drivers/dsp/bridge/rmgr/proc.c | 14 +- drivers/dsp/bridge/services/cfg.c | 8 +- drivers/dsp/bridge/services/clk.c | 5 +- drivers/dsp/bridge/services/regsup.c | 14 +- drivers/dsp/bridge/wmd/_tiomap.h | 48 ++-- drivers/dsp/bridge/wmd/chnl_sm.c | 2 +- drivers/dsp/bridge/wmd/io_sm.c | 386 +++++++++++------------ drivers/dsp/bridge/wmd/msg_sm.c | 75 +++--- drivers/dsp/bridge/wmd/ue_deh.c | 15 +- 22 files changed, 479 insertions(+), 497 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h index 33c2135..f22b2cb 100644 --- a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h @@ -145,7 +145,7 @@ struct loadMonStruct { struct SYNC_OBJECT *hSyncEvent; /* Name of Sync event */ char szEventName[SYNC_MAXNAMELENGTH + 1]; - u32 hProcess; /* Process which created this channel */ + u32 hProcess; /* Process which created this channel */ u32 pCBArg; /* Argument to use with callback */ struct LST_LIST *pIORequests; /* List of IOR's to driver */ s32 cIOCs; /* Number of IOC's in queue */ diff --git a/arch/arm/plat-omap/include/dspbridge/chnlpriv.h b/arch/arm/plat-omap/include/dspbridge/chnlpriv.h index 86fc468..2eadfa0 100644 --- a/arch/arm/plat-omap/include/dspbridge/chnlpriv.h +++ b/arch/arm/plat-omap/include/dspbridge/chnlpriv.h @@ -83,7 +83,7 @@ u32 cPosition; /* Total bytes transferred. */ u32 cIOCs; /* Number of IOCs in queue. */ u32 cIOReqs; /* Number of IO Requests in queue. */ - u32 hProcess; /* Process owning this channel. */ + u32 hProcess; /* Process owning this channel. */ /* * Name of channel I/O completion event. Not required in Linux */ diff --git a/arch/arm/plat-omap/include/dspbridge/dbdefs.h b/arch/arm/plat-omap/include/dspbridge/dbdefs.h index ade9b91..4385b3a 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/dbdefs.h @@ -21,9 +21,9 @@ #include <linux/types.h> -#include <dspbridge/dbtype.h> /* GPP side type definitions */ -#include <dspbridge/std.h> /* DSP/BIOS type definitions */ -#include <dspbridge/rms_sh.h> /* Types shared between GPP and DSP */ +#include <dspbridge/dbtype.h> /* GPP side type definitions */ +#include <dspbridge/std.h> /* DSP/BIOS type definitions */ +#include <dspbridge/rms_sh.h> /* Types shared between GPP and DSP */ #define PG_SIZE_4K 4096 #define PG_MASK(pg_size) (~((pg_size)-1)) diff --git a/arch/arm/plat-omap/include/dspbridge/io_sm.h b/arch/arm/plat-omap/include/dspbridge/io_sm.h index b8f4fb7..77f9e25 100644 --- a/arch/arm/plat-omap/include/dspbridge/io_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/io_sm.h @@ -291,13 +291,13 @@ extern void IO_IntrDSP2(IN struct IO_MGR *pIOMgr, IN u16 wMbVal); - extern void IO_SM_init(void); + extern void IO_SM_init(void); /* * ========PrintDspTraceBuffer ======== * Print DSP tracebuffer. */ - extern DSP_STATUS PrintDspTraceBuffer(struct WMD_DEV_CONTEXT - *hWmdContext); + extern DSP_STATUS PrintDspTraceBuffer(struct WMD_DEV_CONTEXT + *hWmdContext); #endif /* IOSM_ */ diff --git a/drivers/dsp/bridge/dynload/reloc.c b/drivers/dsp/bridge/dynload/reloc.c index d4457c5..b9e2a9b 100644 --- a/drivers/dsp/bridge/dynload/reloc.c +++ b/drivers/dsp/bridge/dynload/reloc.c @@ -195,20 +195,22 @@ void dload_relocate(struct dload_state *dlthis, TgtAU_t *data, rx = HASH_L(rop_map2[rx]); if (rx < 0) { #if TMS32060 - switch (rp->r_type) { - case R_C60ALIGN: - case R_C60NOCMP: - case R_C60FPHEAD: - /* Ignore these reloc types and return */ - break; - default: - /* Unknown reloc type, print error and return */ - dload_error(dlthis, "Bad coff operator 0x%x", rp->r_type); - } + switch (rp->r_type) { + case R_C60ALIGN: + case R_C60NOCMP: + case R_C60FPHEAD: + /* Ignore these reloc types and return */ + break; + default: + /* Unknown reloc type, print error and return */ + dload_error(dlthis, "Bad coff operator 0x%x", + rp->r_type); + } #else - dload_error(dlthis, "Bad coff operator 0x%x", rp->r_type); + dload_error(dlthis, "Bad coff operator 0x%x", + rp->r_type); #endif - return; + return; } } rx = HASH_I(rop_map2[rx]); @@ -216,7 +218,8 @@ void dload_relocate(struct dload_state *dlthis, TgtAU_t *data, && (rx < (sizeof(rop_info)/sizeof(uint_least16_t))) && (rx > 0)) { reloc_action = rop_action[rx]; reloc_info = rop_info[rx]; } else { - dload_error(dlthis, "Buffer Overflow - Array Index Out of Bounds"); + dload_error(dlthis, "Buffer Overflow - Array Index Out " + "of Bounds"); } /* Compute the relocation amount for the referenced symbol, if any */ diff --git a/drivers/dsp/bridge/hw/hw_mbox.h b/drivers/dsp/bridge/hw/hw_mbox.h index 9e67ede..a561fb5 100644 --- a/drivers/dsp/bridge/hw/hw_mbox.h +++ b/drivers/dsp/bridge/hw/hw_mbox.h @@ -116,11 +116,8 @@ extern HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress, * PURPOSE: : this function writes a u32 from the sub module message * box Specified. */ -extern HW_STATUS HW_MBOX_MsgWrite( - const void __iomem *baseAddress, - const HW_MBOX_Id_t mailBoxId, - const u32 writeValue - ); +extern HW_STATUS HW_MBOX_MsgWrite(const void __iomem *baseAddress, + const HW_MBOX_Id_t mailBoxId, const u32 writeValue); /* * FUNCTION : HW_MBOX_NumMsgGet @@ -150,11 +147,8 @@ extern HW_STATUS HW_MBOX_MsgWrite( * * PURPOSE: : this function gets number of messages in a specified mailbox. */ -extern HW_STATUS HW_MBOX_NumMsgGet( - const void __iomem *baseAddress, - const HW_MBOX_Id_t mailBoxId, - u32 *const pNumMsg - ); +extern HW_STATUS HW_MBOX_NumMsgGet(const void __iomem *baseAddress, + const HW_MBOX_Id_t mailBoxId, u32 *const pNumMsg); /* * FUNCTION : HW_MBOX_EventEnable @@ -186,12 +180,10 @@ extern HW_STATUS HW_MBOX_NumMsgGet( * * PURPOSE: : this function enables the specified IRQ. */ -extern HW_STATUS HW_MBOX_EventEnable( - const void __iomem *baseAddress, - const HW_MBOX_Id_t mailBoxId, - const HW_MBOX_UserId_t userId, - const u32 events - ); +extern HW_STATUS HW_MBOX_EventEnable(const void __iomem *baseAddress, + const HW_MBOX_Id_t mailBoxId, + const HW_MBOX_UserId_t userId, + const u32 events); /* * FUNCTION : HW_MBOX_EventDisable @@ -223,12 +215,10 @@ extern HW_STATUS HW_MBOX_EventEnable( * * PURPOSE: : this function disables the specified IRQ. */ -extern HW_STATUS HW_MBOX_EventDisable( - const void __iomem *baseAddress, - const HW_MBOX_Id_t mailBoxId, - const HW_MBOX_UserId_t userId, - const u32 events - ); +extern HW_STATUS HW_MBOX_EventDisable(const void __iomem *baseAddress, + const HW_MBOX_Id_t mailBoxId, + const HW_MBOX_UserId_t userId, + const u32 events); /* * FUNCTION : HW_MBOX_EventAck @@ -262,12 +252,10 @@ extern HW_STATUS HW_MBOX_EventDisable( * * PURPOSE: : this function sets the status of the specified IRQ. */ -extern HW_STATUS HW_MBOX_EventAck( - const void __iomem *baseAddress, - const HW_MBOX_Id_t mailBoxId, - const HW_MBOX_UserId_t userId, - const u32 event - ); +extern HW_STATUS HW_MBOX_EventAck(const void __iomem *baseAddress, + const HW_MBOX_Id_t mailBoxId, + const HW_MBOX_UserId_t userId, + const u32 event); /* * FUNCTION : HW_MBOX_initSettings diff --git a/drivers/dsp/bridge/pmgr/cod.c b/drivers/dsp/bridge/pmgr/cod.c index 0bbee3c..979778d 100644 --- a/drivers/dsp/bridge/pmgr/cod.c +++ b/drivers/dsp/bridge/pmgr/cod.c @@ -368,7 +368,7 @@ DSP_STATUS COD_GetBaseName(struct COD_MANAGER *hManager, char *pszName, DBC_Require(pszName != NULL); if (uSize <= COD_MAXPATHLENGTH) - strncpy(pszName, hManager->szZLFile, uSize); + strncpy(pszName, hManager->szZLFile, uSize); else status = DSP_EFAIL; @@ -401,7 +401,7 @@ DSP_STATUS COD_GetEntry(struct COD_MANAGER *hManager, u32 *pulEntry) * Get handle to the DBLL loader. */ DSP_STATUS COD_GetLoader(struct COD_MANAGER *hManager, - struct DBLL_TarObj **phLoader) + struct DBLL_TarObj **phLoader) { DSP_STATUS status = DSP_SOK; diff --git a/drivers/dsp/bridge/pmgr/dbll.c b/drivers/dsp/bridge/pmgr/dbll.c index e1c706c..857a5db 100644 --- a/drivers/dsp/bridge/pmgr/dbll.c +++ b/drivers/dsp/bridge/pmgr/dbll.c @@ -648,7 +648,7 @@ DSP_STATUS DBLL_open(struct DBLL_TarObj *target, char *file, DBLL_Flags flags, " 0x%x\n", target, file, pLib); zlLib = zlTarget->head; while (zlLib != NULL) { - if (strcmp(zlLib->fileName, file) == 0) { + if (strcmp(zlLib->fileName, file) == 0) { /* Library is already opened */ zlLib->openRef++; break; @@ -670,7 +670,7 @@ DSP_STATUS DBLL_open(struct DBLL_TarObj *target, char *file, DBLL_Flags flags, zlLib->openRef++; zlLib->pTarget = zlTarget; /* Keep a copy of the file name */ - zlLib->fileName = MEM_Calloc(strlen(file) + 1, + zlLib->fileName = MEM_Calloc(strlen(file) + 1, MEM_PAGED); if (zlLib->fileName == NULL) { GT_0trace(DBLL_debugMask, GT_6CLASS, @@ -678,8 +678,8 @@ DSP_STATUS DBLL_open(struct DBLL_TarObj *target, char *file, DBLL_Flags flags, "allocation failed\n"); status = DSP_EMEMORY; } else { - strncpy(zlLib->fileName, file, - strlen(file) + 1); + strncpy(zlLib->fileName, file, + strlen(file) + 1); } zlLib->symTab = NULL; } @@ -998,7 +998,7 @@ static bool nameMatch(void *key, void *value) DBC_Require(value != NULL); if ((key != NULL) && (value != NULL)) { - if (strcmp((char *)key, ((struct Symbol *)value)->name) == 0) + if (strcmp((char *)key, ((struct Symbol *)value)->name) == 0) return true; } return false; @@ -1157,7 +1157,7 @@ static struct dynload_symbol *addToSymbolTable(struct Dynamic_Loader_Sym *this, struct dynload_symbol *retVal; DBC_Require(this != NULL); - DBC_Require(name); + DBC_Require(name); lib = pSymbol->lib; DBC_Require(MEM_IsValidHandle(lib, DBLL_LIBSIGNATURE)); @@ -1175,15 +1175,15 @@ static struct dynload_symbol *addToSymbolTable(struct Dynamic_Loader_Sym *this, } } /* Allocate string to copy symbol name */ - symbol.name = (char *)MEM_Calloc(strlen((char *const)name) + 1, + symbol.name = (char *)MEM_Calloc(strlen((char *const)name) + 1, MEM_PAGED); if (symbol.name == NULL) return NULL; if (symbol.name != NULL) { /* Just copy name (value will be filled in by dynamic loader) */ - strncpy(symbol.name, (char *const)name, - strlen((char *const)name) + 1); + strncpy(symbol.name, (char *const)name, + strlen((char *const)name) + 1); /* Add symbol to symbol table */ symPtr = (struct Symbol *)GH_insert(lib->symTab, (void *)name, @@ -1301,8 +1301,8 @@ static int rmmAlloc(struct Dynamic_Loader_Allocate *this, /* Attempt to extract the segment ID and requirement information from the name of the section */ - DBC_Require(info->name); - tokenLen = strlen((char *)(info->name)) + 1; + DBC_Require(info->name); + tokenLen = strlen((char *)(info->name)) + 1; szSectName = MEM_Calloc(tokenLen, MEM_PAGED); szLastToken = MEM_Calloc(tokenLen, MEM_PAGED); @@ -1313,11 +1313,11 @@ static int rmmAlloc(struct Dynamic_Loader_Allocate *this, status = DSP_EMEMORY; goto func_cont; } - strncpy(szSectName, (char *)(info->name), tokenLen); + strncpy(szSectName, (char *)(info->name), tokenLen); pszCur = szSectName; while ((pToken = strsep(&pszCur, ":")) && *pToken != '\0') { - strncpy(szSecLastToken, szLastToken, strlen(szLastToken) + 1); - strncpy(szLastToken, pToken, strlen(pToken) + 1); + strncpy(szSecLastToken, szLastToken, strlen(szLastToken) + 1); + strncpy(szLastToken, pToken, strlen(pToken) + 1); pToken = strsep(&pszCur, ":"); count++; /* optimizes processing*/ } @@ -1326,13 +1326,13 @@ static int rmmAlloc(struct Dynamic_Loader_Allocate *this, within the section name - only process if there are at least three tokens within the section name (just a minor optimization)*/ if (count >= 3) - strict_strtol(szLastToken, 10, (long *)&req); + strict_strtol(szLastToken, 10, (long *)&req); if ((req == 0) || (req == 1)) { - if (strcmp(szSecLastToken, "DYN_DARAM") == 0) { + if (strcmp(szSecLastToken, "DYN_DARAM") == 0) { segId = 0; } else { - if (strcmp(szSecLastToken, "DYN_SARAM") == 0) { + if (strcmp(szSecLastToken, "DYN_SARAM") == 0) { segId = 1; } else { if (strcmp(szSecLastToken, @@ -1393,7 +1393,7 @@ func_cont: * ======== rmmDealloc ======== */ static void rmmDealloc(struct Dynamic_Loader_Allocate *this, - struct LDR_SECTION_INFO *info) + struct LDR_SECTION_INFO *info) { struct DBLLAlloc *pAlloc = (struct DBLLAlloc *)this; struct DBLL_LibraryObj *lib; @@ -1471,13 +1471,14 @@ static int writeMem(struct Dynamic_Loader_Initialize *this, void *buf, DBC_Require(this != NULL); lib = pInit->lib; - DBC_Require(MEM_IsValidHandle(lib, DBLL_LIBSIGNATURE)); + if (!MEM_IsValidHandle(lib, DBLL_LIBSIGNATURE)) + return false; + + pTarget = lib->pTarget; memType = (DLOAD_SECTION_TYPE(info->type) == DLOAD_TEXT) ? DBLL_CODE : DBLL_DATA; - if ((lib != NULL) && - ((pTarget = lib->pTarget) != NULL) && - (pTarget->attrs.write != NULL)) { + if (lib && pTarget && pTarget->attrs.write) { retVal = (*pTarget->attrs.write)(pTarget->attrs.wHandle, addr, buf, nBytes, memType); diff --git a/drivers/dsp/bridge/rmgr/disp.c b/drivers/dsp/bridge/rmgr/disp.c index 3b4286b..6ea15b4 100644 --- a/drivers/dsp/bridge/rmgr/disp.c +++ b/drivers/dsp/bridge/rmgr/disp.c @@ -766,8 +766,8 @@ static DSP_STATUS FillStreamDef(RMS_WORD *pdwBuf, u32 *ptotal, u32 offset, * 1 from total. */ total += sizeof(struct RMS_StrmDef) / sizeof(RMS_WORD) - 1; - DBC_Require(strmDef.szDevice); - dwLength = strlen(strmDef.szDevice) + 1; + DBC_Require(strmDef.szDevice); + dwLength = strlen(strmDef.szDevice) + 1; /* Number of RMS_WORDS needed to hold device name */ uNameLen = (dwLength + uCharsInRMSWord - 1) / uCharsInRMSWord; diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c index 7ec1ccc..d455c5b 100644 --- a/drivers/dsp/bridge/rmgr/drv.c +++ b/drivers/dsp/bridge/rmgr/drv.c @@ -888,7 +888,7 @@ DSP_STATUS DRV_Init(void) * Insert a DevObject into the list of Manager object. */ DSP_STATUS DRV_InsertDevObject(struct DRV_OBJECT *hDRVObject, - struct DEV_OBJECT *hDevObject) + struct DEV_OBJECT *hDevObject) { DSP_STATUS status = DSP_SOK; struct DRV_OBJECT *pDRVObject = (struct DRV_OBJECT *)hDRVObject; @@ -919,7 +919,7 @@ DSP_STATUS DRV_InsertDevObject(struct DRV_OBJECT *hDRVObject, * objects. */ DSP_STATUS DRV_RemoveDevObject(struct DRV_OBJECT *hDRVObject, - struct DEV_OBJECT *hDevObject) + struct DEV_OBJECT *hDevObject) { DSP_STATUS status = DSP_EFAIL; struct DRV_OBJECT *pDRVObject = (struct DRV_OBJECT *)hDRVObject; @@ -1001,7 +1001,7 @@ DSP_STATUS DRV_RequestResources(u32 dwContext, u32 *pDevNodeString) *pDevNodeString = 0; } - if (!(strcmp((char *) dwContext, "TIOMAP1510"))) { + if (!(strcmp((char *) dwContext, "TIOMAP1510"))) { GT_0trace(curTrace, GT_1CLASS, " Allocating resources for UMA \n"); status = RequestBridgeResourcesDSP(dwContext, DRV_ASSIGN); @@ -1034,7 +1034,7 @@ DSP_STATUS DRV_ReleaseResources(u32 dwContext, struct DRV_OBJECT *hDrvObject) GT_0trace(curTrace, GT_ENTER, "Entering DRV_Release Resources\n"); - if (!(strcmp((char *)((struct DRV_EXT *)dwContext)->szString, + if (!(strcmp((char *)((struct DRV_EXT *)dwContext)->szString, "TIOMAP1510"))) { GT_0trace(curTrace, GT_1CLASS, " Releasing DSP-Bridge resources \n"); @@ -1149,10 +1149,10 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest) iounmap(pResources->dwDmmuBase); if (pResources->dwPerBase) iounmap(pResources->dwPerBase); - if (pResources->dwPerPmBase) - iounmap((void *)pResources->dwPerPmBase); - if (pResources->dwCorePmBase) - iounmap((void *)pResources->dwCorePmBase); + if (pResources->dwPerPmBase) + iounmap((void *)pResources->dwPerPmBase); + if (pResources->dwCorePmBase) + iounmap((void *)pResources->dwCorePmBase); if (pResources->dwSysCtrlBase) { iounmap(pResources->dwSysCtrlBase); /* don't set pResources->dwSysCtrlBase to null @@ -1284,10 +1284,10 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest) OMAP_DSP_MEM3_SIZE); pResources->dwPerBase = ioremap(OMAP_PER_CM_BASE, OMAP_PER_CM_SIZE); - pResources->dwPerPmBase = ioremap(OMAP_PER_PRM_BASE, - OMAP_PER_PRM_SIZE); - pResources->dwCorePmBase = (u32)ioremap(OMAP_CORE_PRM_BASE, - OMAP_CORE_PRM_SIZE); + pResources->dwPerPmBase = ioremap(OMAP_PER_PRM_BASE, + OMAP_PER_PRM_SIZE); + pResources->dwCorePmBase = (u32)ioremap(OMAP_CORE_PRM_BASE, + OMAP_CORE_PRM_SIZE); pResources->dwDmmuBase = ioremap(OMAP_DMMU_BASE, OMAP_DMMU_SIZE); pResources->dwWdTimerDspBase = NULL; diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c index 2c4038a..f480d22 100644 --- a/drivers/dsp/bridge/rmgr/drv_interface.c +++ b/drivers/dsp/bridge/rmgr/drv_interface.c @@ -650,7 +650,7 @@ DSP_STATUS DRV_RemoveAllResources(HANDLE hPCtxt) * sysfs */ static ssize_t drv_state_show(struct kobject *kobj, struct kobj_attribute *attr, - char *buf) + char *buf) { struct WMD_DEV_CONTEXT *dwContext; struct DEV_OBJECT *hDevObject = NULL; @@ -667,18 +667,18 @@ static ssize_t drv_state_show(struct kobject *kobj, struct kobj_attribute *attr, drv_state = dwContext->dwBrdState; } - return sprintf(buf, "%d\n", drv_state); + return sprintf(buf, "%d\n", drv_state); } static struct kobj_attribute drv_state_attr = __ATTR_RO(drv_state); static struct attribute *attrs[] = { - &drv_state_attr.attr, - NULL, + &drv_state_attr.attr, + NULL, }; static struct attribute_group attr_group = { - .attrs = attrs, + .attrs = attrs, }; static void bridge_create_sysfs(void) diff --git a/drivers/dsp/bridge/rmgr/nldr.c b/drivers/dsp/bridge/rmgr/nldr.c index b28c3c4..5f0d4e1 100644 --- a/drivers/dsp/bridge/rmgr/nldr.c +++ b/drivers/dsp/bridge/rmgr/nldr.c @@ -93,15 +93,15 @@ #define FLAGBIT 7 /* 7th bit is pref./req. flag */ #define SEGMASK 0x3f /* Bits 0 - 5 */ -#define CREATEBIT 0 /* Create segid starts at bit 0 */ -#define DELETEBIT 8 /* Delete segid starts at bit 8 */ +#define CREATEBIT 0 /* Create segid starts at bit 0 */ +#define DELETEBIT 8 /* Delete segid starts at bit 8 */ #define EXECUTEBIT 16 /* Execute segid starts at bit 16 */ /* * Masks that define memory type. Must match defines in dynm.cdb. */ -#define DYNM_CODE 0x2 -#define DYNM_DATA 0x4 +#define DYNM_CODE 0x2 +#define DYNM_DATA 0x4 #define DYNM_CODEDATA (DYNM_CODE | DYNM_DATA) #define DYNM_INTERNAL 0x8 #define DYNM_EXTERNAL 0x10 @@ -151,7 +151,7 @@ ((uuid1).usData3 == (uuid2).usData3) && \ ((uuid1).ucData4 == (uuid2).ucData4) && \ ((uuid1).ucData5 == (uuid2).ucData5) && \ - (strncmp((void *)(uuid1).ucData6, (void *)(uuid2).ucData6, 6)) == 0) + (strncmp((void *)(uuid1).ucData6, (void *)(uuid2).ucData6, 6)) == 0) /* * ======== MemInfo ======== @@ -1006,9 +1006,9 @@ static DSP_STATUS AddOvlyInfo(void *handle, struct DBLL_SectInfo *sectInfo, /* Find the node it belongs to */ for (i = 0; i < hNldr->nOvlyNodes; i++) { pNodeName = hNldr->ovlyTable[i].pNodeName; - DBC_Require(pNodeName); - if (strncmp(pNodeName, pSectName + 1, - strlen(pNodeName)) == 0) { + DBC_Require(pNodeName); + if (strncmp(pNodeName, pSectName + 1, + strlen(pNodeName)) == 0) { /* Found the node */ break; } @@ -1022,14 +1022,14 @@ static DSP_STATUS AddOvlyInfo(void *handle, struct DBLL_SectInfo *sectInfo, if (*pch) { pch++; /* Skip over the ':' */ - if (strncmp(pch, PCREATE, strlen(PCREATE)) == 0) { + if (strncmp(pch, PCREATE, strlen(PCREATE)) == 0) { status = AddOvlySect(hNldr, &hNldr->ovlyTable[i]. pCreateSects, sectInfo, &fExists, addr, nBytes); if (DSP_SUCCEEDED(status) && !fExists) hNldr->ovlyTable[i].nCreateSects++; } else - if (strncmp(pch, PDELETE, strlen(PDELETE)) == 0) { + if (strncmp(pch, PDELETE, strlen(PDELETE)) == 0) { status = AddOvlySect(hNldr, &hNldr->ovlyTable[i]. pDeleteSects, sectInfo, &fExists, addr, nBytes); @@ -1037,7 +1037,7 @@ static DSP_STATUS AddOvlyInfo(void *handle, struct DBLL_SectInfo *sectInfo, hNldr->ovlyTable[i].nDeleteSects++; } else - if (strncmp(pch, PEXECUTE, strlen(PEXECUTE)) == 0) { + if (strncmp(pch, PEXECUTE, strlen(PEXECUTE)) == 0) { status = AddOvlySect(hNldr, &hNldr->ovlyTable[i]. pExecuteSects, sectInfo, &fExists, addr, nBytes); @@ -1087,14 +1087,14 @@ static DSP_STATUS AddOvlyNode(struct DSP_UUID *pUuid, } else { /* Add node to table */ hNldr->ovlyTable[hNldr->nNode].uuid = *pUuid; - DBC_Require(objDef.objData.nodeObj.ndbProps.acName); - uLen = strlen(objDef.objData.nodeObj.ndbProps.acName); + DBC_Require(objDef.objData.nodeObj.ndbProps.acName); + uLen = strlen(objDef.objData.nodeObj.ndbProps.acName); pNodeName = objDef.objData.nodeObj.ndbProps.acName; pBuf = MEM_Calloc(uLen + 1, MEM_PAGED); if (pBuf == NULL) { status = DSP_EMEMORY; } else { - strncpy(pBuf, pNodeName, uLen); + strncpy(pBuf, pNodeName, uLen); hNldr->ovlyTable[hNldr->nNode].pNodeName = pBuf; hNldr->nNode++; } diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c index b229a78..19e12b3 100644 --- a/drivers/dsp/bridge/rmgr/node.c +++ b/drivers/dsp/bridge/rmgr/node.c @@ -257,9 +257,9 @@ static void FreeStream(struct NODE_MGR *hNodeMgr, struct STREAM stream); static DSP_STATUS GetFxnAddress(struct NODE_OBJECT *hNode, u32 *pulFxnAddr, u32 uPhase); static DSP_STATUS GetNodeProps(struct DCD_MANAGER *hDcdMgr, - struct NODE_OBJECT *hNode, - CONST struct DSP_UUID *pNodeId, - struct DCD_GENERICOBJ *pdcdProps); + struct NODE_OBJECT *hNode, + CONST struct DSP_UUID *pNodeId, + struct DCD_GENERICOBJ *pdcdProps); static DSP_STATUS GetProcProps(struct NODE_MGR *hNodeMgr, struct DEV_OBJECT *hDevObject); static DSP_STATUS GetRMSFxns(struct NODE_MGR *hNodeMgr); @@ -293,14 +293,13 @@ static struct NLDR_FXNS nldrFxns = { enum NODE_STATE NODE_GetState(HANDLE hNode) { - struct NODE_OBJECT *pNode = (struct NODE_OBJECT *)hNode; - if (!MEM_IsValidHandle(pNode, NODE_SIGNATURE)) { - GT_1trace(NODE_debugMask, GT_5CLASS, - "NODE_GetState:hNode 0x%x\n", pNode); - return -1; - } else - return pNode->nState; - + struct NODE_OBJECT *pNode = (struct NODE_OBJECT *)hNode; + if (!MEM_IsValidHandle(pNode, NODE_SIGNATURE)) { + GT_1trace(NODE_debugMask, GT_5CLASS, + "NODE_GetState:hNode 0x%x\n", pNode); + return -1; + } else + return pNode->nState; } /* @@ -341,7 +340,7 @@ DSP_STATUS NODE_Allocate(struct PROC_OBJECT *hProcessor, #endif #ifndef RES_CLEANUP_DISABLE - HANDLE nodeRes; + HANDLE nodeRes; #endif DBC_Require(cRefs > 0); @@ -516,8 +515,8 @@ func_cont2: if (nodeType != NODE_MESSAGE) { uNumStreams = MaxInputs(pNode) + MaxOutputs(pNode); pNode->streamConnect = MEM_Calloc(uNumStreams * - sizeof(struct DSP_STREAMCONNECT), - MEM_PAGED); + sizeof(struct DSP_STREAMCONNECT), + MEM_PAGED); if (uNumStreams > 0 && pNode->streamConnect == NULL) status = DSP_EMEMORY; @@ -565,9 +564,9 @@ func_cont2: hCmmMgr, NULL); if (DSP_FAILED(status)) { GT_1trace(NODE_debugMask, GT_5CLASS, - "NODE_Allocate: Failed" - " to create SM translator: 0x%x\n", - status); + "NODE_Allocate: Failed to " + "create SM translator: 0x%x\n", + status); } } } @@ -582,7 +581,7 @@ func_cont2: } else { pmsgArgs->uArgLength = pArgs->cbData; memcpy(pmsgArgs->pData, pArgs->cData, - pArgs->cbData); + pArgs->cbData); } } } @@ -720,8 +719,8 @@ func_end: * Allocates buffer for zero copy messaging. */ DBAPI NODE_AllocMsgBuf(struct NODE_OBJECT *hNode, u32 uSize, - OPTIONAL IN OUT struct DSP_BUFFERATTR *pAttr, - OUT u8 **pBuffer) + OPTIONAL IN OUT struct DSP_BUFFERATTR *pAttr, + OUT u8 **pBuffer) { struct NODE_OBJECT *pNode = (struct NODE_OBJECT *)hNode; DSP_STATUS status = DSP_SOK; @@ -1130,7 +1129,7 @@ func_cont2: } /* Set up create args */ pStream->type = DEVICECONNECT; - dwLength = strlen(hDevNode->pstrDevName); + dwLength = strlen(hDevNode->pstrDevName); if (pConnParam != NULL) { pstrmDef->szDevice = MEM_Calloc(dwLength + 1 + (u32) pConnParam->cbData, @@ -1143,12 +1142,12 @@ func_cont2: status = DSP_EMEMORY; } else { /* Copy device name */ - strncpy(pstrmDef->szDevice, hDevNode->pstrDevName, - dwLength); + strncpy(pstrmDef->szDevice, hDevNode->pstrDevName, + dwLength); if (pConnParam != NULL) { - strncat(pstrmDef->szDevice, - (char *)pConnParam->cData, - (u32)pConnParam->cbData); + strncat(pstrmDef->szDevice, + (char *)pConnParam->cData, + (u32)pConnParam->cbData); } hDevNode->hDeviceOwner = hNode; } @@ -2035,16 +2034,15 @@ DSP_STATUS NODE_GetStrmMgr(struct NODE_OBJECT *hNode, */ enum NLDR_LOADTYPE NODE_GetLoadType(struct NODE_OBJECT *hNode) { - DBC_Require(cRefs > 0); DBC_Require(MEM_IsValidHandle(hNode, NODE_SIGNATURE)); - if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) { - GT_1trace(NODE_debugMask, GT_5CLASS, - "NODE_GetLoadType: Failed. hNode:" - " 0x%x\n", hNode); - return -1; - } else - return hNode->dcdProps.objData.nodeObj.usLoadType; + if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) { + GT_1trace(NODE_debugMask, GT_5CLASS, + "NODE_GetLoadType: Failed. hNode:" + " 0x%x\n", hNode); + return -1; + } else + return hNode->dcdProps.objData.nodeObj.usLoadType; } /* @@ -2056,13 +2054,13 @@ u32 NODE_GetTimeout(struct NODE_OBJECT *hNode) { DBC_Require(cRefs > 0); DBC_Require(MEM_IsValidHandle(hNode, NODE_SIGNATURE)); - if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) { - GT_1trace(NODE_debugMask, GT_5CLASS, - "NODE_GetTimeout: Failed. hNode:" - " 0x%x\n", hNode); - return 0; - } else - return hNode->uTimeout; + if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) { + GT_1trace(NODE_debugMask, GT_5CLASS, + "NODE_GetTimeout: Failed. hNode:" + " 0x%x\n", hNode); + return 0; + } else + return hNode->uTimeout; } /* @@ -2077,10 +2075,10 @@ enum NODE_TYPE NODE_GetType(struct NODE_OBJECT *hNode) if (hNode == (struct NODE_OBJECT *) DSP_HGPPNODE) nodeType = NODE_GPP; else { - if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) - nodeType = -1; - else - nodeType = hNode->nType; + if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) + nodeType = -1; + else + nodeType = hNode->nType; } return nodeType; } @@ -2339,8 +2337,8 @@ func_end: * Register to be notified on specific events for this node. */ DSP_STATUS NODE_RegisterNotify(struct NODE_OBJECT *hNode, u32 uEventMask, - u32 uNotifyType, - struct DSP_NOTIFICATION *hNotification) + u32 uNotifyType, + struct DSP_NOTIFICATION *hNotification) { struct WMD_DRV_INTERFACE *pIntfFxns; DSP_STATUS status = DSP_SOK; @@ -2704,8 +2702,7 @@ static void DeleteNode(struct NODE_OBJECT *hNode, if (hNode->hMsgQueue) { pIntfFxns = hNodeMgr->pIntfFxns; (*pIntfFxns->pfnMsgDeleteQueue) (hNode->hMsgQueue); - hNode->hMsgQueue = NULL; - + hNode->hMsgQueue = NULL; } if (hNode->hSyncDone) (void) SYNC_CloseEvent(hNode->hSyncDone); @@ -2717,7 +2714,7 @@ static void DeleteNode(struct NODE_OBJECT *hNode, FreeStream(hNodeMgr, stream); } MEM_Free(hNode->inputs); - hNode->inputs = NULL; + hNode->inputs = NULL; } if (hNode->outputs) { for (i = 0; i < MaxOutputs(hNode); i++) { @@ -2725,7 +2722,7 @@ static void DeleteNode(struct NODE_OBJECT *hNode, FreeStream(hNodeMgr, stream); } MEM_Free(hNode->outputs); - hNode->outputs = NULL; + hNode->outputs = NULL; } taskArgs = hNode->createArgs.asa.taskArgs; if (taskArgs.strmInDef) { @@ -2733,7 +2730,7 @@ static void DeleteNode(struct NODE_OBJECT *hNode, if (taskArgs.strmInDef[i].szDevice) { MEM_Free(taskArgs.strmInDef[i]. szDevice); - taskArgs.strmInDef[i].szDevice = NULL; + taskArgs.strmInDef[i].szDevice = NULL; } } MEM_Free(taskArgs.strmInDef); @@ -2744,7 +2741,7 @@ static void DeleteNode(struct NODE_OBJECT *hNode, if (taskArgs.strmOutDef[i].szDevice) { MEM_Free(taskArgs.strmOutDef[i]. szDevice); - taskArgs.strmOutDef[i].szDevice = NULL; + taskArgs.strmOutDef[i].szDevice = NULL; } } MEM_Free(taskArgs.strmOutDef); @@ -2782,52 +2779,52 @@ static void DeleteNode(struct NODE_OBJECT *hNode, } } if (nodeType != NODE_MESSAGE) { - if (hNode->streamConnect) { + if (hNode->streamConnect) { MEM_Free(hNode->streamConnect); - hNode->streamConnect = NULL; - } + hNode->streamConnect = NULL; + } } - if (hNode->pstrDevName) { + if (hNode->pstrDevName) { MEM_Free(hNode->pstrDevName); - hNode->pstrDevName = NULL; - } + hNode->pstrDevName = NULL; + } - if (hNode->hNtfy) { + if (hNode->hNtfy) { NTFY_Delete(hNode->hNtfy); - hNode->hNtfy = NULL; - } + hNode->hNtfy = NULL; + } /* These were allocated in DCD_GetObjectDef (via NODE_Allocate) */ - if (hNode->dcdProps.objData.nodeObj.pstrCreatePhaseFxn) { + if (hNode->dcdProps.objData.nodeObj.pstrCreatePhaseFxn) { MEM_Free(hNode->dcdProps.objData.nodeObj.pstrCreatePhaseFxn); - hNode->dcdProps.objData.nodeObj.pstrCreatePhaseFxn = NULL; - } + hNode->dcdProps.objData.nodeObj.pstrCreatePhaseFxn = NULL; + } - if (hNode->dcdProps.objData.nodeObj.pstrExecutePhaseFxn) { + if (hNode->dcdProps.objData.nodeObj.pstrExecutePhaseFxn) { MEM_Free(hNode->dcdProps.objData.nodeObj.pstrExecutePhaseFxn); - hNode->dcdProps.objData.nodeObj.pstrExecutePhaseFxn = NULL; - } + hNode->dcdProps.objData.nodeObj.pstrExecutePhaseFxn = NULL; + } - if (hNode->dcdProps.objData.nodeObj.pstrDeletePhaseFxn) { + if (hNode->dcdProps.objData.nodeObj.pstrDeletePhaseFxn) { MEM_Free(hNode->dcdProps.objData.nodeObj.pstrDeletePhaseFxn); - hNode->dcdProps.objData.nodeObj.pstrDeletePhaseFxn = NULL; - } + hNode->dcdProps.objData.nodeObj.pstrDeletePhaseFxn = NULL; + } - if (hNode->dcdProps.objData.nodeObj.pstrIAlgName) { + if (hNode->dcdProps.objData.nodeObj.pstrIAlgName) { MEM_Free(hNode->dcdProps.objData.nodeObj.pstrIAlgName); - hNode->dcdProps.objData.nodeObj.pstrIAlgName = NULL; - } + hNode->dcdProps.objData.nodeObj.pstrIAlgName = NULL; + } /* Free all SM address translator resources */ - if (hXlator) { + if (hXlator) { (void) CMM_XlatorDelete(hXlator, TRUE); /* force free */ - hXlator = NULL; - } + hXlator = NULL; + } - if (hNode->hNldrNode) { + if (hNode->hNldrNode) { hNodeMgr->nldrFxns.pfnFree(hNode->hNldrNode); - hNode->hNldrNode = NULL; - } + hNode->hNldrNode = NULL; + } hNode->hNodeMgr = NULL; MEM_FreeObject(hNode); hNode = NULL; @@ -2903,8 +2900,8 @@ static void DeleteNodeMgr(struct NODE_MGR *hNodeMgr) * Fills stream information. */ static void FillStreamConnect(struct NODE_OBJECT *hNode1, - struct NODE_OBJECT *hNode2, - u32 uStream1, u32 uStream2) + struct NODE_OBJECT *hNode2, + u32 uStream1, u32 uStream2) { u32 uStrmIndex; struct DSP_STREAMCONNECT *pStrm1 = NULL; @@ -2918,7 +2915,7 @@ static void FillStreamConnect(struct NODE_OBJECT *hNode1, if (node1Type != NODE_DEVICE) { uStrmIndex = hNode1->uNumInputs + - hNode1->uNumOutputs - 1; + hNode1->uNumOutputs - 1; pStrm1 = &(hNode1->streamConnect[uStrmIndex]); pStrm1->cbStruct = sizeof(struct DSP_STREAMCONNECT); pStrm1->uThisNodeStreamIndex = uStream1; @@ -2978,7 +2975,7 @@ static void FillStreamDef(struct NODE_OBJECT *hNode, } else { pstrmDef->uNumBufs = DEFAULTNBUFS; pstrmDef->uBufsize = DEFAULTBUFSIZE / hNodeMgr-> - uDSPDataMauSize; + uDSPDataMauSize; pstrmDef->uSegid = DEFAULTSEGID; pstrmDef->uAlignment = DEFAULTALIGNMENT; pstrmDef->uTimeout = DEFAULTTIMEOUT; @@ -3035,15 +3032,15 @@ static DSP_STATUS GetFxnAddress(struct NODE_OBJECT *hNode, u32 *pulFxnAddr, switch (uPhase) { case CREATEPHASE: pstrFxnName = hNode->dcdProps.objData.nodeObj. - pstrCreatePhaseFxn; + pstrCreatePhaseFxn; break; case EXECUTEPHASE: pstrFxnName = hNode->dcdProps.objData.nodeObj. - pstrExecutePhaseFxn; + pstrExecutePhaseFxn; break; case DELETEPHASE: pstrFxnName = hNode->dcdProps.objData.nodeObj. - pstrDeletePhaseFxn; + pstrDeletePhaseFxn; break; default: /* Should never get here */ @@ -3091,9 +3088,9 @@ void GetNodeInfo(struct NODE_OBJECT *hNode, struct DSP_NODEINFO *pNodeInfo) * Retrieve node properties. */ static DSP_STATUS GetNodeProps(struct DCD_MANAGER *hDcdMgr, - struct NODE_OBJECT *hNode, - CONST struct DSP_UUID *pNodeId, - struct DCD_GENERICOBJ *pdcdProps) + struct NODE_OBJECT *hNode, + CONST struct DSP_UUID *pNodeId, + struct DCD_GENERICOBJ *pdcdProps) { u32 uLen; struct NODE_MSGARGS *pMsgArgs; @@ -3132,15 +3129,15 @@ static DSP_STATUS GetNodeProps(struct DCD_MANAGER *hDcdMgr, #endif } else { /* Copy device name */ - DBC_Require(pndbProps->acName); - uLen = strlen(pndbProps->acName); + DBC_Require(pndbProps->acName); + uLen = strlen(pndbProps->acName); DBC_Assert(uLen < MAXDEVNAMELEN); hNode->pstrDevName = MEM_Calloc(uLen + 1, MEM_PAGED); if (hNode->pstrDevName == NULL) { status = DSP_EMEMORY; } else { - strncpy(hNode->pstrDevName, - pndbProps->acName, uLen); + strncpy(hNode->pstrDevName, + pndbProps->acName, uLen); } } } @@ -3154,15 +3151,15 @@ static DSP_STATUS GetNodeProps(struct DCD_MANAGER *hDcdMgr, pTaskArgs->uStackSeg = pndbProps->uStackSeg; #ifdef DEBUG DBG_Trace(DBG_LEVEL7, - "** (node) Priority: 0x%x\n" "** (node) Stack" - " Size: 0x%x words\n" "** (node) System Stack" - " Size: 0x%x words\n" "** (node) Stack" - " Segment: 0x%x\n\n", - "** (node) profile count : 0x%x \n \n", - pTaskArgs->nPriority, pTaskArgs->uStackSize, - pTaskArgs->uSysStackSize, - pTaskArgs->uStackSeg, - pndbProps->uCountProfiles); + "** (node) Priority: 0x%x\n" "** (node) Stack" + " Size: 0x%x words\n" "** (node) System Stack" + " Size: 0x%x words\n" "** (node) Stack" + " Segment: 0x%x\n\n", + "** (node) profile count : 0x%x \n \n", + pTaskArgs->nPriority, pTaskArgs->uStackSize, + pTaskArgs->uSysStackSize, + pTaskArgs->uStackSeg, + pndbProps->uCountProfiles); #endif } } @@ -3222,7 +3219,7 @@ DSP_STATUS NODE_GetUUIDProps(DSP_HPROCESSOR hProcessor, struct NODE_MGR *hNodeMgr = NULL; struct DEV_OBJECT *hDevObject; DSP_STATUS status = DSP_SOK; - struct DCD_NODEPROPS dcdNodeProps; + struct DCD_NODEPROPS dcdNodeProps; struct DSP_PROCESSORSTATE procStatus; DBC_Require(cRefs > 0); diff --git a/drivers/dsp/bridge/rmgr/proc.c b/drivers/dsp/bridge/rmgr/proc.c index 75dc3af..0c23e2c 100644 --- a/drivers/dsp/bridge/rmgr/proc.c +++ b/drivers/dsp/bridge/rmgr/proc.c @@ -294,8 +294,8 @@ static DSP_STATUS GetExecFile(struct CFG_DEVNODE *hDevNode, return CFG_GetExecFile(hDevNode, size, execFile); } else if (devType == IVA_UNIT) { if (iva_img) { - len = strlen(iva_img); - strncpy(execFile, iva_img, len + 1); + len = strlen(iva_img); + strncpy(execFile, iva_img, len + 1); return DSP_SOK; } } @@ -536,8 +536,8 @@ DSP_STATUS PROC_Detach(struct PROCESS_CONTEXT *pr_ctxt) * on a DSP processor. */ DSP_STATUS PROC_EnumNodes(DSP_HPROCESSOR hProcessor, OUT DSP_HNODE *aNodeTab, - IN u32 uNodeTabSize, OUT u32 *puNumNodes, - OUT u32 *puAllocated) + IN u32 uNodeTabSize, OUT u32 *puNumNodes, + OUT u32 *puAllocated) { DSP_STATUS status = DSP_EFAIL; struct PROC_OBJECT *pProcObject = (struct PROC_OBJECT *)hProcessor; @@ -1049,13 +1049,13 @@ DSP_STATUS PROC_Load(DSP_HPROCESSOR hProcessor, IN CONST s32 iArgc, DBC_Assert(pProcObject->g_pszLastCoff == NULL); /* Allocate memory for pszLastCoff */ pProcObject->g_pszLastCoff = MEM_Calloc( - (strlen((char *)aArgv[0]) + 1), + (strlen((char *)aArgv[0]) + 1), MEM_PAGED); /* If memory allocated, save COFF file name*/ if (pProcObject->g_pszLastCoff) { - strncpy(pProcObject->g_pszLastCoff, + strncpy(pProcObject->g_pszLastCoff, (char *)aArgv[0], - (strlen((char *)aArgv[0]) + 1)); + (strlen((char *)aArgv[0]) + 1)); } } } diff --git a/drivers/dsp/bridge/services/cfg.c b/drivers/dsp/bridge/services/cfg.c index 9667a08..892577a 100644 --- a/drivers/dsp/bridge/services/cfg.c +++ b/drivers/dsp/bridge/services/cfg.c @@ -113,7 +113,7 @@ DSP_STATUS CFG_GetDevObject(struct CFG_DEVNODE *hDevNode, OUT u32 *pdwValue) if (DSP_SUCCEEDED(status)) { /* check the device string and then call the REG_SetValue*/ - if (!(strcmp((char *)((struct DRV_EXT *)hDevNode)->szString, + if (!(strcmp((char *)((struct DRV_EXT *)hDevNode)->szString, "TIOMAP1510"))) { GT_0trace(CFG_debugMask, GT_1CLASS, "Fetching DSP Device from " @@ -217,7 +217,7 @@ DSP_STATUS CFG_GetExecFile(struct CFG_DEVNODE *hDevNode, u32 ulBufSize, } #endif DBC_Ensure(((status == DSP_SOK) && - (strlen(pstrExecFile) <= ulBufSize)) || (status != DSP_SOK)); + (strlen(pstrExecFile) <= ulBufSize)) || (status != DSP_SOK)); return status; } @@ -348,11 +348,11 @@ DSP_STATUS CFG_SetDevObject(struct CFG_DEVNODE *hDevNode, u32 dwValue) if (DSP_SUCCEEDED(status)) { /* Store the WCD device object in the Registry */ - if (!(strcmp((char *)hDevNode, "TIOMAP1510"))) { + if (!(strcmp((char *)hDevNode, "TIOMAP1510"))) { GT_0trace(CFG_debugMask, GT_1CLASS, "Registering the DSP Device \n"); status = REG_SetValue("DEVICE_DSP", (u8 *)&dwValue, - dwBuffSize); + dwBuffSize); } else { GT_0trace(CFG_debugMask, GT_6CLASS, "Failed to Register Device \n"); diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c index ae317c5..a56f01e 100644 --- a/drivers/dsp/bridge/services/clk.c +++ b/drivers/dsp/bridge/services/clk.c @@ -220,7 +220,7 @@ DSP_STATUS CLK_Set_32KHz(IN enum SERVICES_ClkId clk_id) pClk = SERVICES_Clks[clk_id].clk_handle; if (pClk) { if (!(clk_set_parent(pClk, pClkParent) == 0x0)) { - GT_2trace(CLK_debugMask, GT_7CLASS, "CLK_Set_32KHz: " + GT_2trace(CLK_debugMask, GT_7CLASS, "CLK_Set_32KHz: " "Failed to set to 32KHz %s, CLK dev id = %s\n", SERVICES_Clks[clk_id].clk_name, SERVICES_Clks[clk_id].dev); @@ -323,7 +323,8 @@ s32 CLK_Get_UseCnt(IN enum SERVICES_ClkId clk_id) pClk = SERVICES_Clks[clk_id].clk_handle; if (pClk) { - useCount = pClk->usecount; /* FIXME: usecount shouldn't be used */ + /* FIXME: usecount shouldn't be used */ + useCount = pClk->usecount; } else { GT_2trace(CLK_debugMask, GT_7CLASS, "CLK_GetRate: failed to get CLK %s, " diff --git a/drivers/dsp/bridge/services/regsup.c b/drivers/dsp/bridge/services/regsup.c index 5c2421b..4376b36 100644 --- a/drivers/dsp/bridge/services/regsup.c +++ b/drivers/dsp/bridge/services/regsup.c @@ -129,7 +129,7 @@ DSP_STATUS regsupGetValue(char *valName, void *pBuf, u32 *dataSize) /* Need to search through the entries looking for the right one. */ for (i = 0; i < pRegKey->numValueEntries; i++) { /* See if the name matches. */ - if (strncmp(pRegKey->values[i].name, valName, + if (strncmp(pRegKey->values[i].name, valName, BRIDGE_MAX_NAME_SIZE) == 0) { /* We have a match! Copy out the data. */ @@ -171,7 +171,7 @@ DSP_STATUS regsupSetValue(char *valName, void *pBuf, u32 dataSize) /* Need to search through the entries looking for the right one. */ for (i = 0; i < pRegKey->numValueEntries; i++) { /* See if the name matches. */ - if (strncmp(pRegKey->values[i].name, valName, + if (strncmp(pRegKey->values[i].name, valName, BRIDGE_MAX_NAME_SIZE) == 0) { /* Make sure the new data size is the same. */ if (dataSize != pRegKey->values[i].dataSize) { @@ -247,16 +247,16 @@ DSP_STATUS regsupEnumValue(IN u32 dwIndex, IN CONST char *pstrKey, /* Need to search through the entries looking for the right one. */ for (i = 0; i < pRegKey->numValueEntries; i++) { /* See if the name matches. */ - if ((strncmp(pRegKey->values[i].name, pstrKey, + if ((strncmp(pRegKey->values[i].name, pstrKey, dwKeyLen) == 0) && count++ == dwIndex) { /* We have a match! Copy out the data. */ memcpy(pstrData, pRegKey->values[i].pData, pRegKey->values[i].dataSize); /* Get the size for the caller. */ *pdwDataSize = pRegKey->values[i].dataSize; - *pdwValueSize = strlen(&(pRegKey-> + *pdwValueSize = strlen(&(pRegKey-> values[i].name[dwKeyLen])); - strncpy(pstrValue, + strncpy(pstrValue, &(pRegKey->values[i].name[dwKeyLen]), *pdwValueSize + 1); GT_3trace(REG_debugMask, GT_2CLASS, @@ -285,7 +285,7 @@ DSP_STATUS regsupDeleteValue(IN CONST char *pstrValue) for (i = 0; ((i < BRIDGE_MAX_NUM_REG_ENTRIES) && (i < pRegKey->numValueEntries)); i++) { /* See if the name matches... */ - if (strncmp(pRegKey->values[i].name, pstrValue, + if (strncmp(pRegKey->values[i].name, pstrValue, BRIDGE_MAX_NAME_SIZE) == 0) { /* We have a match! Delete this key. To delete a * key, we free all resources associated with this @@ -301,7 +301,7 @@ DSP_STATUS regsupDeleteValue(IN CONST char *pstrValue) pRegKey->values[i].pData = NULL; } else { /* move the last one here */ - strncpy(pRegKey->values[i].name, pRegKey-> + strncpy(pRegKey->values[i].name, pRegKey-> values[pRegKey->numValueEntries - 1].name, BRIDGE_MAX_NAME_SIZE); pRegKey->values[i].dataSize = diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h index ac6e115..5c613b4 100644 --- a/drivers/dsp/bridge/wmd/_tiomap.h +++ b/drivers/dsp/bridge/wmd/_tiomap.h @@ -328,28 +328,28 @@ enum INTH_SensitiveEdge_t { /* This mini driver's device context: */ struct WMD_DEV_CONTEXT { struct DEV_OBJECT *hDevObject; /* Handle to WCD device object. */ - u32 dwDspBaseAddr; /* Arm's API to DSP virtual base addr */ + u32 dwDspBaseAddr; /* Arm's API to DSP virt base addr */ /* * DSP External memory prog address as seen virtually by the OS on * the host side. */ - u32 dwDspExtBaseAddr; /* See the comment above */ - u32 dwAPIRegBase; /* API memory mapped registers */ - void __iomem *dwDSPMmuBase; /* DSP MMU Mapped registers */ - void __iomem *dwMailBoxBase; /* Mail box mapped registers */ - void __iomem *cmbase; /* CM mapped registers */ - void __iomem *sysctrlbase; /* SysCtrl mapped registers */ - void __iomem *prmbase; /* PRM mapped registers */ - void __iomem *perbase; /* PER mapped registers */ - u32 dwAPIClkBase; /* CLK Registers */ - u32 dwDSPClkM2Base; /* DSP Clock Module m2 */ - u32 dwPublicRhea; /* Pub Rhea */ - u32 dwIntAddr; /* MB INTR reg */ - u32 dwTCEndianism; /* TC Endianism register */ - u32 dwTestBase; /* DSP MMU Mapped registers */ - u32 dwSelfLoop; /* Pointer to the selfloop */ - u32 dwDSPStartAdd; /* API Boot vector */ - u32 dwInternalSize; /* Internal memory size */ + u32 dwDspExtBaseAddr; /* See the comment above */ + u32 dwAPIRegBase; /* API mem map'd registers */ + void __iomem *dwDSPMmuBase; /* DSP MMU Mapped registers */ + void __iomem *dwMailBoxBase; /* Mail box mapped registers */ + void __iomem *cmbase; /* CM mapped registers */ + void __iomem *sysctrlbase; /* SysCtrl mapped registers */ + void __iomem *prmbase; /* PRM mapped registers */ + void __iomem *perbase; /* PER mapped registers */ + u32 dwAPIClkBase; /* CLK Registers */ + u32 dwDSPClkM2Base; /* DSP Clock Module m2 */ + u32 dwPublicRhea; /* Pub Rhea */ + u32 dwIntAddr; /* MB INTR reg */ + u32 dwTCEndianism; /* TC Endianism register */ + u32 dwTestBase; /* DSP MMU Mapped registers */ + u32 dwSelfLoop; /* Pointer to the selfloop */ + u32 dwDSPStartAdd; /* API Boot vector */ + u32 dwInternalSize; /* Internal memory size */ /* * Processor specific info is set when prog loaded and read from DCD. @@ -357,14 +357,14 @@ struct WMD_DEV_CONTEXT { */ /* DMMU TLB entries */ struct WMDIOCTL_EXTPROC aTLBEntry[WMDIOCTL_NUMOFMMUTLB]; - u32 dwBrdState; /* Last known board state. */ - u32 ulIntMask; /* int mask */ - u16 ioBase; /* Board I/O base */ - u32 numTLBEntries; /* DSP MMU TLB entry counter */ - u32 fixedTLBEntries; /* Fixed DSPMMU TLB entry count */ + u32 dwBrdState; /* Last known board state. */ + u32 ulIntMask; /* int mask */ + u16 ioBase; /* Board I/O base */ + u32 numTLBEntries; /* DSP MMU TLB entry counter */ + u32 fixedTLBEntries; /* Fixed DSPMMU TLB entry count */ /* TC Settings */ - bool tcWordSwapOn; /* Traffic Controller Word Swap */ + bool tcWordSwapOn; /* Traffic Controller Word Swap */ struct PgTableAttrs *pPtAttrs; u32 uDspPerClks; } ; diff --git a/drivers/dsp/bridge/wmd/chnl_sm.c b/drivers/dsp/bridge/wmd/chnl_sm.c index 7157eea..867792e 100644 --- a/drivers/dsp/bridge/wmd/chnl_sm.c +++ b/drivers/dsp/bridge/wmd/chnl_sm.c @@ -861,7 +861,7 @@ DSP_STATUS WMD_CHNL_Open(OUT struct CHNL_OBJECT **phChnl, pChnl->uMode = uMode; pChnl->hUserEvent = hSyncEvent; /* for Linux */ pChnl->hSyncEvent = hSyncEvent; - /* get the process handle */ + /* Get the process handle */ pChnl->hProcess = current->tgid; pChnl->pCBArg = 0; pChnl->cBytesMoved = 0; diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index 746689d..c923c47 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -214,17 +214,15 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, if (DSP_FAILED(status)) goto func_cont; - /* - * Create a Single Threaded Work Queue - */ - - if (ref_count == 0) - bridge_workqueue = create_workqueue("bridge_work-queue"); - - if (bridge_workqueue <= 0) - DBG_Trace(DBG_LEVEL1, "Workque Create" - " failed 0x%d \n", bridge_workqueue); + /* + * Create a Single Threaded Work Queue + */ + if (ref_count == 0) + bridge_workqueue = create_workqueue("bridge_work-queue"); + if (bridge_workqueue <= 0) + DBG_Trace(DBG_LEVEL1, "Workque Create failed 0x%d \n", + bridge_workqueue); /* Allocate IO manager object: */ MEM_AllocObject(pIOMgr, struct IO_MGR, IO_MGRSIGNATURE); @@ -232,12 +230,12 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = DSP_EMEMORY; goto func_cont; } - /*Intializing Work Element*/ - if (ref_count == 0) { - INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM); - ref_count = 1; - } else - PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM); + /*Intializing Work Element*/ + if (ref_count == 0) { + INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM); + ref_count = 1; + } else + PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM); /* Initialize CHNL_MGR object: */ #ifndef DSP_TRACEBUF_DISABLED @@ -269,18 +267,15 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, if (devType == DSP_UNIT) { HW_MBOX_initSettings(hostRes.dwMboxBase); /* Plug the channel ISR:. */ - if ((request_irq(INT_MAIL_MPU_IRQ, IO_ISR, 0, - "DspBridge\tmailbox", (void *)pIOMgr)) == 0) - status = DSP_SOK; - else - status = DSP_EFAIL; + if ((request_irq(INT_MAIL_MPU_IRQ, IO_ISR, 0, + "DspBridge\tmailbox", (void *)pIOMgr)) == 0) { + status = DSP_SOK; + DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n", + pIOMgr); + } else + status = CHNL_E_ISR; } - if (DSP_SUCCEEDED(status)) - DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n", - pIOMgr); - else - status = CHNL_E_ISR; - } else + } else status = CHNL_E_ISR; func_cont: if (DSP_FAILED(status)) { @@ -307,7 +302,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) struct WMD_DEV_CONTEXT *hWmdContext; if (MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE)) { /* Unplug IRQ: */ - /* Disable interrupts from the board: */ + /* Disable interrupts from the board: */ status = DEV_GetWMDContext(hIOMgr->hDevObject, &hWmdContext); if (DSP_SUCCEEDED(status)) (void)CHNLSM_DisableInterrupt(hWmdContext); @@ -913,14 +908,13 @@ func_end: */ static void IO_DispatchPM(struct work_struct *work) { - struct IO_MGR *pIOMgr = - container_of(work, struct IO_MGR, io_workq); + struct IO_MGR *pIOMgr = container_of(work, struct IO_MGR, io_workq); DSP_STATUS status; u32 pArg[2]; DBG_Trace(DBG_LEVEL7, "IO_DispatchPM: Entering IO_DispatchPM : \n"); - /* Perform Power message processing here */ + /* Perform Power message processing here */ while (pIOMgr->iQuePowerHead != pIOMgr->iQuePowerTail) { pArg[0] = *(u32 *)&(pIOMgr->dQuePowerMbxVal[pIOMgr-> iQuePowerTail]); @@ -1044,7 +1038,7 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) if (hIOMgr->iQuePowerHead >= MAX_PM_REQS) hIOMgr->iQuePowerHead = 0; - queue_work(bridge_workqueue, &hIOMgr->io_workq); + queue_work(bridge_workqueue, &hIOMgr->io_workq); } if (hIOMgr->wIntrVal == MBX_DEH_RESET) { DBG_Trace(DBG_LEVEL6, "*** DSP RESET ***\n"); @@ -1187,8 +1181,8 @@ static void InputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, pChnl = pChnlMgr->apChannel[chnlId]; if ((pChnl != NULL) && CHNL_IsInput(pChnl->uMode)) { if ((pChnl->dwState & ~CHNL_STATEEOS) == CHNL_STATEREADY) { - if (!pChnl->pIORequests) - goto func_end; + if (!pChnl->pIORequests) + goto func_end; /* Get the I/O request, and attempt a transfer: */ pChirp = (struct CHNL_IRP *)LST_GetHead(pChnl-> pIORequests); @@ -1229,8 +1223,8 @@ static void InputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, "chnl = 0x%x\n", pChnl); } /* Tell DSP if no more I/O buffers available: */ - if (!pChnl->pIORequests) - goto func_end; + if (!pChnl->pIORequests) + goto func_end; if (LST_IsEmpty(pChnl->pIORequests)) { IO_AndValue(pIOMgr->hWmdContext, struct SHM, sm, hostFreeMask, @@ -1302,19 +1296,19 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) addr = (u32)&(((struct MSG_DSPMSG *)pMsgInput)->dwId); msg.dwId = ReadExt32BitDspData(pIOMgr->hWmdContext, addr); pMsgInput += sizeof(struct MSG_DSPMSG); - if (!hMsgMgr->queueList) - goto func_end; + if (!hMsgMgr->queueList) + goto func_end; /* Determine which queue to put the message in */ hMsgQueue = (struct MSG_QUEUE *)LST_First(hMsgMgr->queueList); DBG_Trace(DBG_LEVEL7, "InputMsg RECVD: dwCmd=0x%x dwArg1=0x%x " "dwArg2=0x%x dwId=0x%x \n", msg.msg.dwCmd, msg.msg.dwArg1, msg.msg.dwArg2, msg.dwId); - /* Interrupt may occur before shared memory and message + /* Interrupt may occur before shared memory and message * input locations have been set up. If all nodes were * cleaned up, hMsgMgr->uMaxMsgs should be 0. */ - if (hMsgQueue && uMsgs > hMsgMgr->uMaxMsgs) - goto func_end; + if (hMsgQueue && uMsgs > hMsgMgr->uMaxMsgs) + goto func_end; while (hMsgQueue != NULL) { if (msg.dwId == hMsgQueue->dwId) { @@ -1329,11 +1323,11 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) } else { /* Not an exit acknowledgement, queue * the message */ - if (!hMsgQueue->msgFreeList) - goto func_end; + if (!hMsgQueue->msgFreeList) + goto func_end; pMsg = (struct MSG_FRAME *)LST_GetHead (hMsgQueue->msgFreeList); - if (hMsgQueue->msgUsedList && pMsg) { + if (hMsgQueue->msgUsedList && pMsg) { pMsg->msgData = msg; LST_PutTail(hMsgQueue-> msgUsedList, @@ -1353,8 +1347,8 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) break; } - if (!hMsgMgr->queueList || !hMsgQueue) - goto func_end; + if (!hMsgMgr->queueList || !hMsgQueue) + goto func_end; hMsgQueue = (struct MSG_QUEUE *)LST_Next(hMsgMgr-> queueList, (struct LST_ELEM *)hMsgQueue); } @@ -1451,8 +1445,8 @@ static void OutputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, goto func_end; pChnl->cIOReqs--; - if (pChnl->cIOReqs < 0 || !pChnl->pIORequests) - goto func_end; + if (pChnl->cIOReqs < 0 || !pChnl->pIORequests) + goto func_end; /* Record fact that no more I/O buffers available: */ if (LST_IsEmpty(pChnl->pIORequests)) @@ -1516,13 +1510,13 @@ static void OutputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) pMsgOutput = pIOMgr->pMsgOutput; /* Copy uMsgs messages into shared memory */ for (i = 0; i < uMsgs; i++) { - if (!hMsgMgr->msgUsedList) { - DBG_Trace(DBG_LEVEL3, "msgUsedList is NULL\n"); - pMsg = NULL; - goto func_end; - } else - pMsg = (struct MSG_FRAME *)LST_GetHead( - hMsgMgr->msgUsedList); + if (!hMsgMgr->msgUsedList) { + DBG_Trace(DBG_LEVEL3, "msgUsedList is NULL\n"); + pMsg = NULL; + goto func_end; + } else + pMsg = (struct MSG_FRAME *)LST_GetHead( + hMsgMgr->msgUsedList); if (pMsg != NULL) { val = (pMsg->msgData).dwId; addr = (u32)&(((struct MSG_DSPMSG *) @@ -1547,8 +1541,8 @@ static void OutputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) WriteExt32BitDspData(pIOMgr->hWmdContext, addr, val); pMsgOutput += sizeof(struct MSG_DSPMSG); - if (!hMsgMgr->msgFreeList) - goto func_end; + if (!hMsgMgr->msgFreeList) + goto func_end; LST_PutTail(hMsgMgr->msgFreeList, (struct LST_ELEM *) pMsg); SYNC_SetEvent(hMsgMgr->hSyncEvent); @@ -1844,7 +1838,7 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) * pointer */ hIOMgr->ulGPPReadPointer += ulNewMessageLength; /* Print the trace messages */ - GT_0trace(dsp_trace_mask, GT_1CLASS, hIOMgr->pMsg); + GT_0trace(dsp_trace_mask, GT_1CLASS, hIOMgr->pMsg); } /* Handle trace buffer wraparound */ else if (ulGPPCurPointer < hIOMgr->ulGPPReadPointer) { @@ -1865,7 +1859,7 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) hIOMgr->ulGPPReadPointer = hIOMgr->ulTraceBufferBegin + ulNewMessageLength; /* Print the trace messages */ - GT_0trace(dsp_trace_mask, GT_1CLASS, hIOMgr->pMsg); + GT_0trace(dsp_trace_mask, GT_1CLASS, hIOMgr->pMsg); } } } @@ -1893,48 +1887,48 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) #if (defined(DEBUG) || defined(DDSP_DEBUG_PRODUCT)) && GT_TRACE static DSP_STATUS PackTraceBuffer(char *lpBuf, u32 nBytes, u32 ulNumWords) { - DSP_STATUS status = DSP_SOK; - char *lpTmpBuf; - char *lpBufStart; - char *lpTmpStart; - u32 nCnt; - char thisChar; - - /* tmp workspace, 1 KB longer than input buf */ - lpTmpBuf = MEM_Calloc((nBytes + ulNumWords), MEM_PAGED); - if (lpTmpBuf == NULL) { - DBG_Trace(DBG_LEVEL7, "PackTrace buffer:OutofMemory \n"); - status = DSP_EMEMORY; - } - - if (DSP_SUCCEEDED(status)) { - lpBufStart = lpBuf; - lpTmpStart = lpTmpBuf; - for (nCnt = nBytes; nCnt > 0; nCnt--) { - thisChar = *lpBuf++; - switch (thisChar) { - case '\0': /* Skip null bytes */ - break; - case '\n': /* Convert \n to \r\n */ - /* NOTE: do not reverse order; Some OS */ - /* editors control doesn't understand "\n\r" */ - *lpTmpBuf++ = '\r'; - *lpTmpBuf++ = '\n'; - break; - default: /* Copy in the actual ascii byte */ - *lpTmpBuf++ = thisChar; - break; - } - } - *lpTmpBuf = '\0'; /* Make sure tmp buf is null terminated */ - /* Cut output down to input buf size */ - strncpy(lpBufStart, lpTmpStart, nBytes); - /*Make sure output is null terminated */ - lpBufStart[nBytes - 1] = '\0'; - MEM_Free(lpTmpStart); - } - - return status; + DSP_STATUS status = DSP_SOK; + char *lpTmpBuf; + char *lpBufStart; + char *lpTmpStart; + u32 nCnt; + char thisChar; + + /* tmp workspace, 1 KB longer than input buf */ + lpTmpBuf = MEM_Calloc((nBytes + ulNumWords), MEM_PAGED); + if (lpTmpBuf == NULL) { + DBG_Trace(DBG_LEVEL7, "PackTrace buffer:OutofMemory \n"); + status = DSP_EMEMORY; + } + + if (DSP_SUCCEEDED(status)) { + lpBufStart = lpBuf; + lpTmpStart = lpTmpBuf; + for (nCnt = nBytes; nCnt > 0; nCnt--) { + thisChar = *lpBuf++; + switch (thisChar) { + case '\0': /* Skip null bytes */ + break; + case '\n': /* Convert \n to \r\n */ + /* NOTE: do not reverse order; Some OS */ + /* editors control doesn't understand "\n\r" */ + *lpTmpBuf++ = '\r'; + *lpTmpBuf++ = '\n'; + break; + default: /* Copy in the actual ascii byte */ + *lpTmpBuf++ = thisChar; + break; + } + } + *lpTmpBuf = '\0'; /* Make sure tmp buf is null terminated */ + /* Cut output down to input buf size */ + strncpy(lpBufStart, lpTmpStart, nBytes); + /*Make sure output is null terminated */ + lpBufStart[nBytes - 1] = '\0'; + MEM_Free(lpTmpStart); + } + + return status; } #endif /* (defined(DEBUG) || defined(DDSP_DEBUG_PRODUCT)) && GT_TRACE */ @@ -1952,106 +1946,106 @@ static DSP_STATUS PackTraceBuffer(char *lpBuf, u32 nBytes, u32 ulNumWords) */ DSP_STATUS PrintDspTraceBuffer(struct WMD_DEV_CONTEXT *hWmdContext) { - DSP_STATUS status = DSP_SOK; + DSP_STATUS status = DSP_SOK; #if (defined(DEBUG) || defined(DDSP_DEBUG_PRODUCT)) && GT_TRACE - struct COD_MANAGER *hCodMgr; - u32 ulTraceEnd; - u32 ulTraceBegin; - u32 ulNumBytes = 0; - u32 ulNumWords = 0; - u32 ulWordSize = 2; - CONST u32 uMaxSize = 512; - char *pszBuf; - u16 *lpszBuf; - - struct WMD_DEV_CONTEXT *pWmdContext = (struct WMD_DEV_CONTEXT *) - hWmdContext; - struct WMD_DRV_INTERFACE *pIntfFxns; - struct DEV_OBJECT *pDevObject = (struct DEV_OBJECT *) - pWmdContext->hDevObject; - - status = DEV_GetCodMgr(pDevObject, &hCodMgr); - if (DSP_FAILED(status)) - GT_0trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: Failed on DEV_GetCodMgr.\n"); - - if (DSP_SUCCEEDED(status)) { - /* Look for SYS_PUTCBEG/SYS_PUTCEND: */ - status = COD_GetSymValue(hCodMgr, COD_TRACEBEG, &ulTraceBegin); - GT_1trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: ulTraceBegin Value 0x%x\n", - ulTraceBegin); - if (DSP_FAILED(status)) - GT_0trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: Failed on " - "COD_GetSymValue.\n"); - } - if (DSP_SUCCEEDED(status)) { - status = COD_GetSymValue(hCodMgr, COD_TRACEEND, &ulTraceEnd); - GT_1trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: ulTraceEnd Value 0x%x\n", - ulTraceEnd); - if (DSP_FAILED(status)) - GT_0trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: Failed on " - "COD_GetSymValue.\n"); - } - if (DSP_SUCCEEDED(status)) { - ulNumBytes = (ulTraceEnd - ulTraceBegin) * ulWordSize; - /* If the chip type is 55 then the addresses will be - * byte addresses; convert them to word addresses. */ - if (ulNumBytes > uMaxSize) - ulNumBytes = uMaxSize; - - /* make sure the data we request fits evenly */ - ulNumBytes = (ulNumBytes / ulWordSize) * ulWordSize; - GT_1trace(dsp_trace_mask, GT_2CLASS, "PrintDspTraceBuffer: " - "ulNumBytes 0x%x\n", ulNumBytes); - ulNumWords = ulNumBytes * ulWordSize; - GT_1trace(dsp_trace_mask, GT_2CLASS, "PrintDspTraceBuffer: " - "ulNumWords 0x%x\n", ulNumWords); - status = DEV_GetIntfFxns(pDevObject, &pIntfFxns); - } - - if (DSP_SUCCEEDED(status)) { - pszBuf = MEM_Calloc(uMaxSize, MEM_NONPAGED); - lpszBuf = MEM_Calloc(ulNumBytes * 2, MEM_NONPAGED); - if (pszBuf != NULL) { - /* Read bytes from the DSP trace buffer... */ - status = (*pIntfFxns->pfnBrdRead)(hWmdContext, - (u8 *)pszBuf, (u32)ulTraceBegin, - ulNumBytes, 0); - if (DSP_FAILED(status)) - GT_0trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: " - "Failed to Read Trace Buffer.\n"); - - if (DSP_SUCCEEDED(status)) { - /* Pack and do newline conversion */ - GT_0trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: " - "before pack and unpack.\n"); - PackTraceBuffer(pszBuf, ulNumBytes, ulNumWords); - GT_1trace(dsp_trace_mask, GT_1CLASS, - "DSP Trace Buffer:\n%s\n", pszBuf); - } - MEM_Free(pszBuf); - MEM_Free(lpszBuf); - } else { - GT_0trace(dsp_trace_mask, GT_2CLASS, - "PrintDspTraceBuffer: Failed to " - "allocate trace buffer.\n"); - status = DSP_EMEMORY; - } - } + struct COD_MANAGER *hCodMgr; + u32 ulTraceEnd; + u32 ulTraceBegin; + u32 ulNumBytes = 0; + u32 ulNumWords = 0; + u32 ulWordSize = 2; + CONST u32 uMaxSize = 512; + char *pszBuf; + u16 *lpszBuf; + + struct WMD_DEV_CONTEXT *pWmdContext = (struct WMD_DEV_CONTEXT *) + hWmdContext; + struct WMD_DRV_INTERFACE *pIntfFxns; + struct DEV_OBJECT *pDevObject = (struct DEV_OBJECT *) + pWmdContext->hDevObject; + + status = DEV_GetCodMgr(pDevObject, &hCodMgr); + if (DSP_FAILED(status)) + GT_0trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: Failed on DEV_GetCodMgr.\n"); + + if (DSP_SUCCEEDED(status)) { + /* Look for SYS_PUTCBEG/SYS_PUTCEND: */ + status = COD_GetSymValue(hCodMgr, COD_TRACEBEG, &ulTraceBegin); + GT_1trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: ulTraceBegin Value 0x%x\n", + ulTraceBegin); + if (DSP_FAILED(status)) + GT_0trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: Failed on " + "COD_GetSymValue.\n"); + } + if (DSP_SUCCEEDED(status)) { + status = COD_GetSymValue(hCodMgr, COD_TRACEEND, &ulTraceEnd); + GT_1trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: ulTraceEnd Value 0x%x\n", + ulTraceEnd); + if (DSP_FAILED(status)) + GT_0trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: Failed on " + "COD_GetSymValue.\n"); + } + if (DSP_SUCCEEDED(status)) { + ulNumBytes = (ulTraceEnd - ulTraceBegin) * ulWordSize; + /* + * If the chip type is 55 then the addresses will be + * byte addresses; convert them to word addresses. + */ + if (ulNumBytes > uMaxSize) + ulNumBytes = uMaxSize; + + /* Make sure the data we request fits evenly */ + ulNumBytes = (ulNumBytes / ulWordSize) * ulWordSize; + GT_1trace(dsp_trace_mask, GT_2CLASS, "PrintDspTraceBuffer: " + "ulNumBytes 0x%x\n", ulNumBytes); + ulNumWords = ulNumBytes * ulWordSize; + GT_1trace(dsp_trace_mask, GT_2CLASS, "PrintDspTraceBuffer: " + "ulNumWords 0x%x\n", ulNumWords); + status = DEV_GetIntfFxns(pDevObject, &pIntfFxns); + } + + if (DSP_SUCCEEDED(status)) { + pszBuf = MEM_Calloc(uMaxSize, MEM_NONPAGED); + lpszBuf = MEM_Calloc(ulNumBytes * 2, MEM_NONPAGED); + if (pszBuf != NULL) { + /* Read bytes from the DSP trace buffer... */ + status = (*pIntfFxns->pfnBrdRead)(hWmdContext, + (u8 *)pszBuf, (u32)ulTraceBegin, + ulNumBytes, 0); + if (DSP_FAILED(status)) + GT_0trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: " + "Failed to Read Trace Buffer.\n"); + + if (DSP_SUCCEEDED(status)) { + /* Pack and do newline conversion */ + GT_0trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: " + "before pack and unpack.\n"); + PackTraceBuffer(pszBuf, ulNumBytes, ulNumWords); + GT_1trace(dsp_trace_mask, GT_1CLASS, + "DSP Trace Buffer:\n%s\n", pszBuf); + } + MEM_Free(pszBuf); + MEM_Free(lpszBuf); + } else { + GT_0trace(dsp_trace_mask, GT_2CLASS, + "PrintDspTraceBuffer: Failed to " + "allocate trace buffer.\n"); + status = DSP_EMEMORY; + } + } #endif - return status; + return status; } void IO_SM_init(void) { - - GT_create(&dsp_trace_mask, "DT"); /* DSP Trace Mask */ - + GT_create(&dsp_trace_mask, "DT"); /* DSP Trace Mask */ } diff --git a/drivers/dsp/bridge/wmd/msg_sm.c b/drivers/dsp/bridge/wmd/msg_sm.c index ad716ab..8e0aa9d 100644 --- a/drivers/dsp/bridge/wmd/msg_sm.c +++ b/drivers/dsp/bridge/wmd/msg_sm.c @@ -166,10 +166,10 @@ DSP_STATUS WMD_MSG_CreateQueue(struct MSG_MGR *hMsgMgr, status = SYNC_OpenEvent(&pMsgQ->hSyncDoneAck, NULL); if (DSP_SUCCEEDED(status)) { - if (!hMsgMgr->msgFreeList) { - status = DSP_EHANDLE; - goto func_end; - } + if (!hMsgMgr->msgFreeList) { + status = DSP_EHANDLE; + goto func_end; + } /* Enter critical section */ (void)SYNC_EnterCS(hMsgMgr->hSyncCS); /* Initialize message frames and put in appropriate queues */ @@ -241,8 +241,8 @@ void WMD_MSG_DeleteQueue(struct MSG_QUEUE *hMsgQueue) LST_RemoveElem(hMsgMgr->queueList, (struct LST_ELEM *)hMsgQueue); /* Free the message queue object */ DeleteMsgQueue(hMsgQueue, hMsgQueue->uMaxMsgs); - if (!hMsgMgr->msgFreeList) - goto func_cont; + if (!hMsgMgr->msgFreeList) + goto func_cont; if (LST_IsEmpty(hMsgMgr->msgFreeList)) SYNC_ResetEvent(hMsgMgr->hSyncEvent); func_cont: @@ -271,10 +271,10 @@ DSP_STATUS WMD_MSG_Get(struct MSG_QUEUE *hMsgQueue, } hMsgMgr = hMsgQueue->hMsgMgr; - if (!hMsgQueue->msgUsedList) { - status = DSP_EHANDLE; - goto func_end; - } + if (!hMsgQueue->msgUsedList) { + status = DSP_EHANDLE; + goto func_end; + } /* Enter critical section */ (void)SYNC_EnterCS(hMsgMgr->hSyncCS); @@ -373,11 +373,10 @@ DSP_STATUS WMD_MSG_Put(struct MSG_QUEUE *hMsgQueue, goto func_end; } hMsgMgr = hMsgQueue->hMsgMgr; - if (!hMsgMgr->msgFreeList) { - status = DSP_EHANDLE; - goto func_end; - } - + if (!hMsgMgr->msgFreeList) { + status = DSP_EHANDLE; + goto func_end; + } (void) SYNC_EnterCS(hMsgMgr->hSyncCS); @@ -427,10 +426,10 @@ DSP_STATUS WMD_MSG_Put(struct MSG_QUEUE *hMsgQueue, status = DSP_EFAIL; } else { if (DSP_SUCCEEDED(status)) { - if (LST_IsEmpty(hMsgMgr->msgFreeList)) { - status = DSP_EPOINTER; - goto func_cont; - } + if (LST_IsEmpty(hMsgMgr->msgFreeList)) { + status = DSP_EPOINTER; + goto func_cont; + } /* Get msg from free list */ pMsgFrame = (struct MSG_FRAME *) LST_GetHead(hMsgMgr->msgFreeList); @@ -545,21 +544,21 @@ static void DeleteMsgMgr(struct MSG_MGR *hMsgMgr) goto func_end; if (hMsgMgr->queueList) { - if (LST_IsEmpty(hMsgMgr->queueList)) { - LST_Delete(hMsgMgr->queueList); - hMsgMgr->queueList = NULL; - } + if (LST_IsEmpty(hMsgMgr->queueList)) { + LST_Delete(hMsgMgr->queueList); + hMsgMgr->queueList = NULL; + } } - if (hMsgMgr->msgFreeList) { + if (hMsgMgr->msgFreeList) { FreeMsgList(hMsgMgr->msgFreeList); - hMsgMgr->msgFreeList = NULL; - } + hMsgMgr->msgFreeList = NULL; + } - if (hMsgMgr->msgUsedList) { + if (hMsgMgr->msgUsedList) { FreeMsgList(hMsgMgr->msgUsedList); - hMsgMgr->msgUsedList = NULL; - } + hMsgMgr->msgUsedList = NULL; + } if (hMsgMgr->hSyncEvent) SYNC_CloseEvent(hMsgMgr->hSyncEvent); @@ -581,11 +580,11 @@ static void DeleteMsgQueue(struct MSG_QUEUE *hMsgQueue, u32 uNumToDSP) struct MSG_FRAME *pMsg; u32 i; - if (!MEM_IsValidHandle(hMsgQueue, MSGQ_SIGNATURE) - || !hMsgQueue->hMsgMgr || !hMsgQueue->hMsgMgr->msgFreeList) - goto func_end; - hMsgMgr = hMsgQueue->hMsgMgr; + if (!MEM_IsValidHandle(hMsgQueue, MSGQ_SIGNATURE) + || !hMsgQueue->hMsgMgr || !hMsgQueue->hMsgMgr->msgFreeList) + goto func_end; + hMsgMgr = hMsgQueue->hMsgMgr; /* Pull off uNumToDSP message frames from Msg manager and free */ for (i = 0; i < uNumToDSP; i++) { @@ -602,12 +601,12 @@ static void DeleteMsgQueue(struct MSG_QUEUE *hMsgQueue, u32 uNumToDSP) if (hMsgQueue->msgFreeList) { FreeMsgList(hMsgQueue->msgFreeList); - hMsgQueue->msgFreeList = NULL; + hMsgQueue->msgFreeList = NULL; } if (hMsgQueue->msgUsedList) { FreeMsgList(hMsgQueue->msgUsedList); - hMsgQueue->msgUsedList = NULL; + hMsgQueue->msgUsedList = NULL; } @@ -636,8 +635,8 @@ static void FreeMsgList(struct LST_LIST *msgList) { struct MSG_FRAME *pMsg; - if (!msgList) - goto func_end; + if (!msgList) + goto func_end; while ((pMsg = (struct MSG_FRAME *)LST_GetHead(msgList)) != NULL) MEM_Free(pMsg); @@ -646,6 +645,6 @@ static void FreeMsgList(struct LST_LIST *msgList) LST_Delete(msgList); func_end: - return; + return; } diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c index 658cd73..c2020a1 100644 --- a/drivers/dsp/bridge/wmd/ue_deh.c +++ b/drivers/dsp/bridge/wmd/ue_deh.c @@ -107,11 +107,11 @@ DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr, pDehMgr->errInfo.dwVal2 = 0L; pDehMgr->errInfo.dwVal3 = 0L; /* Install ISR function for DSP MMU fault */ - if ((request_irq(INT_DSP_MMU_IRQ, MMU_FaultIsr, 0, - "DspBridge\tiommu fault", (void *)pDehMgr)) == 0) - status = DSP_SOK; - else - status = DSP_EFAIL; + if ((request_irq(INT_DSP_MMU_IRQ, MMU_FaultIsr, 0, + "DspBridge\tiommu fault", (void *)pDehMgr)) == 0) + status = DSP_SOK; + else + status = DSP_EFAIL; } } if (DSP_FAILED(status)) { @@ -120,8 +120,7 @@ DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr, *phDehMgr = NULL; } else { *phDehMgr = (struct DEH_MGR *)pDehMgr; - DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n", - pDehMgr); + DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n", pDehMgr); } DBG_Trace(DBG_LEVEL1, "Exiting DEH_Create.\n"); return status; @@ -144,7 +143,7 @@ DSP_STATUS WMD_DEH_Destroy(struct DEH_MGR *hDehMgr) if (pDehMgr->hNtfy) (void)NTFY_Delete(pDehMgr->hNtfy); /* Disable DSP MMU fault */ - free_irq(INT_DSP_MMU_IRQ, pDehMgr); + free_irq(INT_DSP_MMU_IRQ, pDehMgr); (void)DPC_Destroy(pDehMgr->hMmuFaultDpc); /* Deallocate the DEH manager object */ MEM_FreeObject(pDehMgr); -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 08/20] DSPBRIDGE: Checkpatch - line over 80 characters 2009-11-30 21:54 ` [PATCH v2 07/20] DSPBRIDGE: checkpatch spacing and indentation Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon WARNING: line over 80 characters Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- arch/arm/plat-omap/include/dspbridge/dbdefs.h | 2 +- drivers/dsp/bridge/wmd/io_sm.c | 3 ++- drivers/dsp/bridge/wmd/mmu_fault.c | 3 ++- drivers/dsp/bridge/wmd/tiomap3430.c | 23 ++++++++++++++--------- drivers/dsp/bridge/wmd/tiomap3430_pwr.c | 24 ++++++++++++++++-------- drivers/dsp/bridge/wmd/tiomap_sm.c | 11 ++++++----- drivers/dsp/bridge/wmd/ue_deh.c | 14 ++++++++------ 7 files changed, 49 insertions(+), 31 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/dbdefs.h b/arch/arm/plat-omap/include/dspbridge/dbdefs.h index 4385b3a..526b7f3 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/dbdefs.h @@ -554,7 +554,7 @@ bit 6 - MMU element size = 64bit (valid only for non mixed page entries) #define AUTOSTART "AutoStart" /* Statically load flag */ #define CURRENTCONFIG "CurrentConfig" /* Current resources */ #define SHMSIZE "SHMSize" /* Size of SHM reservd on MPU */ -#define TCWORDSWAP "TCWordSwap" /* Traffic Contoller Word Swap */ +#define TCWORDSWAP "TCWordSwap" /* Traffic Controller WordSwp */ #define DSPRESOURCES "DspTMSResources" /* C55 DSP resurces on OMAP */ #endif /* DBDEFS_ */ diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index c923c47..c541400 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -1566,7 +1566,8 @@ static void OutputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) IO_SetValue(pIOMgr->hWmdContext, struct MSG, pCtrl, postSWI, true); /* Tell the DSP we have written the output. */ - CHNLSM_InterruptDSP2(pIOMgr->hWmdContext, MBX_PCPY_CLASS); + CHNLSM_InterruptDSP2(pIOMgr->hWmdContext, + MBX_PCPY_CLASS); } } func_end: diff --git a/drivers/dsp/bridge/wmd/mmu_fault.c b/drivers/dsp/bridge/wmd/mmu_fault.c index b6cbbb3..bb98e56 100644 --- a/drivers/dsp/bridge/wmd/mmu_fault.c +++ b/drivers/dsp/bridge/wmd/mmu_fault.c @@ -140,7 +140,8 @@ static bool MMU_CheckIfFault(struct WMD_DEV_CONTEXT *pDevContext) DBG_Trace(DBG_LEVEL7, "**Failed to get Host Resources in " "MMU_CheckIfFault **\n"); - hwStatus = HW_MMU_EventStatus(pDevContext->dwDSPMmuBase, &dmmuEventMask); + hwStatus = HW_MMU_EventStatus(pDevContext->dwDSPMmuBase, + &dmmuEventMask); if (dmmuEventMask == HW_MMU_TRANSLATION_FAULT) { HW_MMU_FaultAddrRead(pDevContext->dwDSPMmuBase, &faultAddr); DBG_Trace(DBG_LEVEL1, "WMD_DEH_Notify: DSP_MMUFAULT, fault " diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c index c73cea7..cfa8868 100644 --- a/drivers/dsp/bridge/wmd/tiomap3430.c +++ b/drivers/dsp/bridge/wmd/tiomap3430.c @@ -340,12 +340,14 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext) HW_PWR_DOMAIN_DSP, HW_PWR_STATE_ON); /* Set the SW supervised state transition */ - HW_PWR_CLKCTRL_IVA2RegSet(pDevContext->cmbase, HW_SW_SUP_WAKEUP); + HW_PWR_CLKCTRL_IVA2RegSet(pDevContext->cmbase, + HW_SW_SUP_WAKEUP); /* Wait until the state has moved to ON */ HW_PWR_IVA2StateGet(pDevContext->prmbase, HW_PWR_DOMAIN_DSP, &pwrState); /* Disable Automatic transition */ - HW_PWR_CLKCTRL_IVA2RegSet(pDevContext->cmbase, HW_AUTOTRANS_DIS); + HW_PWR_CLKCTRL_IVA2RegSet(pDevContext->cmbase, + HW_AUTOTRANS_DIS); } DBG_Trace(DBG_LEVEL6, "WMD_BRD_Monitor - Middle ****** \n"); GetHWRegs(pDevContext->prmbase, pDevContext->cmbase); @@ -490,7 +492,7 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext, if (dsp_debug) { /* Set the bootmode to self loop */ DBG_Trace(DBG_LEVEL7, - "Set boot mode to self loop for IVA2 Device\n"); + "Set boot mode to self loop for IVA2 Device\n"); HW_DSPSS_BootModeSet(pDevContext->sysctrlbase, HW_DSPSYSC_SELFLOOPBOOT, dwDSPAddr); } else { @@ -540,8 +542,8 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext, } /* end for */ /* - * Lock the above TLB entries and get the BIOS and load monitor timer - * information + * Lock the above TLB entries and get the BIOS and load + * monitor timer information */ HW_MMU_NumLockedSet(pDevContext->dwDSPMmuBase, itmpEntryNdx); HW_MMU_VictimNumSet(pDevContext->dwDSPMmuBase, itmpEntryNdx); @@ -559,10 +561,11 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext, /* Enable the BIOS clock */ (void)DEV_GetSymbol(pDevContext->hDevObject, - BRIDGEINIT_BIOSGPTIMER, &ulBiosGpTimer); + BRIDGEINIT_BIOSGPTIMER, &ulBiosGpTimer); DBG_Trace(DBG_LEVEL7, "BIOS GPTimer : 0x%x\n", ulBiosGpTimer); (void)DEV_GetSymbol(pDevContext->hDevObject, - BRIDGEINIT_LOADMON_GPTIMER, &ulLoadMonitorTimer); + BRIDGEINIT_LOADMON_GPTIMER, + &ulLoadMonitorTimer); DBG_Trace(DBG_LEVEL7, "Load Monitor Timer : 0x%x\n", ulLoadMonitorTimer); @@ -575,7 +578,8 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext, DSPPeripheralClkCtrl(pDevContext, &uClkCmd); extClkId = uClkCmd & MBX_PM_CLK_IDMASK; - for (tmpIndex = 0; tmpIndex < MBX_PM_MAX_RESOURCES; tmpIndex++) { + for (tmpIndex = 0; tmpIndex < MBX_PM_MAX_RESOURCES; + tmpIndex++) { if (extClkId == BPWR_CLKID[tmpIndex]) { clkIdIndex = tmpIndex; break; @@ -583,7 +587,8 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext, } if (clkIdIndex < MBX_PM_MAX_RESOURCES) - status = CLK_Set_32KHz(BPWR_Clks[clkIdIndex].funClk); + status = + CLK_Set_32KHz(BPWR_Clks[clkIdIndex].funClk); else status = DSP_EFAIL; diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c index dc20684..f5eb21c 100644 --- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c +++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c @@ -547,14 +547,18 @@ DSP_STATUS DSP_PeripheralClocks_Disable(struct WMD_DEV_CONTEXT *pDevContext, status = CLK_Disable(BPWR_Clks[clkIdx].intClk); if (BPWR_CLKID[clkIdx] == BPWR_MCBSP1) { /* clear MCBSP1_CLKS, on McBSP1 OFF */ - value = __raw_readl(pDevContext->sysctrlbase + 0x274); + value = __raw_readl(pDevContext->sysctrlbase + + 0x274); value &= ~(1 << 2); - __raw_writel(value, pDevContext->sysctrlbase + 0x274); + __raw_writel(value, pDevContext->sysctrlbase + + 0x274); } else if (BPWR_CLKID[clkIdx] == BPWR_MCBSP2) { /* clear MCBSP2_CLKS, on McBSP2 OFF */ - value = __raw_readl(pDevContext->sysctrlbase + 0x274); + value = __raw_readl(pDevContext->sysctrlbase + + 0x274); value &= ~(1 << 6); - __raw_writel(value, pDevContext->sysctrlbase + 0x274); + __raw_writel(value, pDevContext->sysctrlbase + + 0x274); } if (DSP_FAILED(status)) { DBG_Trace(DBG_LEVEL7, @@ -590,14 +594,18 @@ DSP_STATUS DSP_PeripheralClocks_Enable(struct WMD_DEV_CONTEXT *pDevContext, int_clk_status = CLK_Enable(BPWR_Clks[clkIdx].intClk); if (BPWR_CLKID[clkIdx] == BPWR_MCBSP1) { /* set MCBSP1_CLKS, on McBSP1 ON */ - value = __raw_readl(pDevContext->sysctrlbase + 0x274); + value = __raw_readl(pDevContext->sysctrlbase + + 0x274); value |= 1 << 2; - __raw_writel(value, pDevContext->sysctrlbase + 0x274); + __raw_writel(value, pDevContext->sysctrlbase + + 0x274); } else if (BPWR_CLKID[clkIdx] == BPWR_MCBSP2) { /* set MCBSP2_CLKS, on McBSP2 ON */ - value = __raw_readl(pDevContext->sysctrlbase + 0x274); + value = __raw_readl(pDevContext->sysctrlbase + + 0x274); value |= 1 << 6; - __raw_writel(value, pDevContext->sysctrlbase + 0x274); + __raw_writel(value, pDevContext->sysctrlbase + + 0x274); } /* Enable the functional clock of the periphearl */ fun_clk_status = CLK_Enable(BPWR_Clks[clkIdx].funClk); diff --git a/drivers/dsp/bridge/wmd/tiomap_sm.c b/drivers/dsp/bridge/wmd/tiomap_sm.c index fb0b661..b74ce68 100644 --- a/drivers/dsp/bridge/wmd/tiomap_sm.c +++ b/drivers/dsp/bridge/wmd/tiomap_sm.c @@ -65,9 +65,9 @@ DSP_STATUS CHNLSM_EnableInterrupt(struct WMD_DEV_CONTEXT *pDevContext) numMbxMsg--; udelay(10); - HW_MBOX_EventAck(pDevContext->dwMailBoxBase, MBOX_ARM2DSP, - HW_MBOX_U1_DSP1, - HW_MBOX_INT_NEW_MSG); + HW_MBOX_EventAck(pDevContext->dwMailBoxBase, + MBOX_ARM2DSP, HW_MBOX_U1_DSP1, + HW_MBOX_INT_NEW_MSG); } /* Enable the new message events on this IRQ line */ HW_MBOX_EventEnable(pDevContext->dwMailBoxBase, @@ -158,10 +158,11 @@ bool CHNLSM_ISR(struct WMD_DEV_CONTEXT *pDevContext, bool *pfSchedDPC, HW_MBOX_NumMsgGet(pDevContext->dwMailBoxBase, MBOX_DSP2ARM, &numMbxMsg); if (numMbxMsg > 0) { - HW_MBOX_MsgRead(pDevContext->dwMailBoxBase, MBOX_DSP2ARM, &mbxValue); + HW_MBOX_MsgRead(pDevContext->dwMailBoxBase, MBOX_DSP2ARM, + &mbxValue); HW_MBOX_EventAck(pDevContext->dwMailBoxBase, MBOX_DSP2ARM, - HW_MBOX_U0_ARM, HW_MBOX_INT_NEW_MSG); + HW_MBOX_U0_ARM, HW_MBOX_INT_NEW_MSG); DBG_Trace(DBG_LEVEL3, "Read %x from Mailbox\n", mbxValue); *pwIntrVal = (u16) mbxValue; diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c index c2020a1..6d6c76b 100644 --- a/drivers/dsp/bridge/wmd/ue_deh.c +++ b/drivers/dsp/bridge/wmd/ue_deh.c @@ -248,14 +248,16 @@ DBG_Trace(DBG_LEVEL6, "WMD_DEH_Notify: DSP_MMUFAULT, " "PA: 0x%x\n", pDevContext-> numTLBEntries, faultAddr, memPhysical); if (DSP_SUCCEEDED(status)) { - hwStatus = HW_MMU_TLBAdd(pDevContext->dwDSPMmuBase, - memPhysical, faultAddr, - HW_PAGE_SIZE_4KB, 1, &mapAttrs, - HW_SET, HW_SET); + hwStatus = + HW_MMU_TLBAdd(pDevContext->dwDSPMmuBase, + memPhysical, faultAddr, + HW_PAGE_SIZE_4KB, 1, &mapAttrs, + HW_SET, HW_SET); } /* send an interrupt to DSP */ - HW_MBOX_MsgWrite(pDevContext->dwMailBoxBase, MBOX_ARM2DSP, - MBX_DEH_CLASS | MBX_DEH_EMMU); + HW_MBOX_MsgWrite(pDevContext->dwMailBoxBase, + MBOX_ARM2DSP, + MBX_DEH_CLASS | MBX_DEH_EMMU); /* Clear MMU interrupt */ HW_MMU_EventAck(pDevContext->dwDSPMmuBase, HW_MMU_TRANSLATION_FAULT); -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level 2009-11-30 21:54 ` [PATCH v2 08/20] DSPBRIDGE: Checkpatch - line over 80 characters Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 10/20] DSPBRIDGE: checkpatch - braces not necessary for single statement blocks Omar Ramirez Luna 2009-12-01 3:57 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Menon, Nishanth 0 siblings, 2 replies; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon WARNING: printk() should include KERN_ facility level Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- arch/arm/plat-omap/include/dspbridge/dbc.h | 2 +- arch/arm/plat-omap/include/dspbridge/gt.h | 2 +- drivers/dsp/bridge/gen/_gt_para.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/dbc.h b/arch/arm/plat-omap/include/dspbridge/dbc.h index e9cb548..13b1ff6 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbc.h +++ b/arch/arm/plat-omap/include/dspbridge/dbc.h @@ -36,7 +36,7 @@ #define DBC_Assert(exp) \ if (!(exp)) \ - printk("%s, line %d: Assertion (" #exp ") failed.\n", \ + printk(KERN_ERR "%s, line %d: Assertion (" #exp ") failed.\n", \ __FILE__, __LINE__) #define DBC_Require DBC_Assert /* Function Precondition. */ #define DBC_Ensure DBC_Assert /* Function Postcondition. */ diff --git a/arch/arm/plat-omap/include/dspbridge/gt.h b/arch/arm/plat-omap/include/dspbridge/gt.h index b43b1e7..c110234 100644 --- a/arch/arm/plat-omap/include/dspbridge/gt.h +++ b/arch/arm/plat-omap/include/dspbridge/gt.h @@ -232,7 +232,7 @@ extern struct GT_Config _GT_params; #define GT_assert(mask, expr) \ (!(expr) ? \ - printk("assertion violation: %s, line %d\n", \ + printk(KERN_ERR "assertion violation: %s, line %d\n", \ __FILE__, __LINE__), NULL : NULL) #define GT_config(config) (_GT_params = *(config)) diff --git a/drivers/dsp/bridge/gen/_gt_para.c b/drivers/dsp/bridge/gen/_gt_para.c index 9f8246b..dd22f77 100644 --- a/drivers/dsp/bridge/gen/_gt_para.c +++ b/drivers/dsp/bridge/gen/_gt_para.c @@ -77,7 +77,7 @@ static void error(char *fmt, ...) va_end(va); - printk("ERROR: "); + printk(KERN_ERR "ERROR: "); printk(fmt, arg1, arg2, arg3, arg4, arg5, arg6); #if defined(DEBUG) || defined(DDSP_DEBUG_PRODUCT) -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 10/20] DSPBRIDGE: checkpatch - braces not necessary for single statement blocks 2009-11-30 21:54 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 11/20] DSPBRIDGE: checkpatch - struct file_operations should normally be const Omar Ramirez Luna 2009-12-01 3:57 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Menon, Nishanth 1 sibling, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon WARNING: braces {} are not necessary for single statement blocks Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- drivers/dsp/bridge/gen/gs.c | 3 +-- drivers/dsp/bridge/pmgr/cmm.c | 5 ++--- drivers/dsp/bridge/rmgr/node.c | 4 ++-- drivers/dsp/bridge/services/cfg.c | 10 +++++----- drivers/dsp/bridge/wmd/io_sm.c | 3 +-- 5 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/dsp/bridge/gen/gs.c b/drivers/dsp/bridge/gen/gs.c index 5a5684c..7d6c278 100644 --- a/drivers/dsp/bridge/gen/gs.c +++ b/drivers/dsp/bridge/gen/gs.c @@ -87,7 +87,6 @@ void GS_init(void) { static bool curInit; - if (curInit == false) { + if (curInit == false) curInit = MEM_Init(); /* which can't fail currently. */ - } } diff --git a/drivers/dsp/bridge/pmgr/cmm.c b/drivers/dsp/bridge/pmgr/cmm.c index 556749f..63d1dec 100644 --- a/drivers/dsp/bridge/pmgr/cmm.c +++ b/drivers/dsp/bridge/pmgr/cmm.c @@ -1044,11 +1044,10 @@ DSP_STATUS CMM_XlatorDelete(struct CMM_XLATOROBJECT *hXlator, bool bForce) DBC_Require(cRefs > 0); - if (MEM_IsValidHandle(pXlator, CMMXLATESIGNATURE)) { + if (MEM_IsValidHandle(pXlator, CMMXLATESIGNATURE)) MEM_FreeObject(pXlator); - } else { + else status = DSP_EHANDLE; - } return status; } diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c index 19e12b3..006a079 100644 --- a/drivers/dsp/bridge/rmgr/node.c +++ b/drivers/dsp/bridge/rmgr/node.c @@ -2116,9 +2116,9 @@ bool NODE_Init(void) */ void NODE_OnExit(struct NODE_OBJECT *hNode, s32 nStatus) { - if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) { + if (!MEM_IsValidHandle(hNode, NODE_SIGNATURE)) return; - } + /* Set node state to done */ NODE_SetState(hNode, NODE_DONE); hNode->nExitStatus = nStatus; diff --git a/drivers/dsp/bridge/services/cfg.c b/drivers/dsp/bridge/services/cfg.c index 892577a..fcdf682 100644 --- a/drivers/dsp/bridge/services/cfg.c +++ b/drivers/dsp/bridge/services/cfg.c @@ -152,13 +152,13 @@ DSP_STATUS CFG_GetDSPResources(struct CFG_DEVNODE *hDevNode, "Entered CFG_GetDSPResources, args: " "\n\thDevNode: 0x%x\n\tpDSPResTable: 0x%x\n", hDevNode, pDSPResTable); - if (!hDevNode) { + if (!hDevNode) status = CFG_E_INVALIDHDEVNODE; - } else if (!pDSPResTable) { + else if (!pDSPResTable) status = CFG_E_INVALIDPOINTER; - } else { - status = REG_GetValue(DSPRESOURCES, (u8 *)pDSPResTable, &dwResSize); - } + else + status = REG_GetValue(DSPRESOURCES, (u8 *)pDSPResTable, + &dwResSize); if (DSP_SUCCEEDED(status)) { GT_0trace(CFG_debugMask, GT_1CLASS, "CFG_GetDSPResources SUCCESS\n"); diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index c541400..af31831 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -596,9 +596,8 @@ func_cont1: aEProc[ndx].ulGppVa, aEProc[ndx].ulDspVa * hIOMgr->uWordSize, pgSize[i]); - if (DSP_FAILED(status)) { + if (DSP_FAILED(status)) goto func_end; - } } paCurr += pgSize[i]; vaCurr += pgSize[i]; -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 11/20] DSPBRIDGE: checkpatch - struct file_operations should normally be const 2009-11-30 21:54 ` [PATCH v2 10/20] DSPBRIDGE: checkpatch - braces not necessary for single statement blocks Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 12/20] DSPBRIDGE: checkpatch foo-should-be for pointers Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon WARNING: struct file_operations should normally be const Signed-off-by: Omar Ramirez Lua <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- drivers/dsp/bridge/rmgr/drv_interface.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c index f480d22..94f35d1 100644 --- a/drivers/dsp/bridge/rmgr/drv_interface.c +++ b/drivers/dsp/bridge/rmgr/drv_interface.c @@ -166,7 +166,7 @@ static char *driver_name = DRIVER_NAME; static struct GT_Mask driverTrace; #endif /* CONFIG_BRIDGE_DEBUG */ -static struct file_operations bridge_fops = { +static const struct file_operations bridge_fops = { .open = bridge_open, .release = bridge_release, .unlocked_ioctl = bridge_ioctl, -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 12/20] DSPBRIDGE: checkpatch foo-should-be for pointers 2009-11-30 21:54 ` [PATCH v2 11/20] DSPBRIDGE: checkpatch - struct file_operations should normally be const Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 13/20] DSPBRIDGE: Fix multiline macros to use do while Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon ERROR: "foo *__user * bar" should be "foo *__user *bar" Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h index b213b82..397361c 100644 --- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h +++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h @@ -54,7 +54,7 @@ union Trapped_Args { } ARGS_MGR_UNREGISTEROBJECT; struct { - struct DSP_NOTIFICATION __user*__user *aNotifications; + struct DSP_NOTIFICATION __user *__user *aNotifications; u32 uCount; u32 __user *puIndex; u32 uTimeout; @@ -111,7 +111,7 @@ union Trapped_Args { struct { DSP_HPROCESSOR hProcessor; s32 iArgc; - char __user*__user *aArgv; + char __user *__user *aArgv; char *__user *aEnvp; } ARGS_PROC_LOAD; -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 13/20] DSPBRIDGE: Fix multiline macros to use do while 2009-11-30 21:54 ` [PATCH v2 12/20] DSPBRIDGE: checkpatch foo-should-be for pointers Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 14/20] DSPBRIDGE: Use _IOxx macro to define ioctls Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon Fixed multiline macros that break under if statements * Also minor indentation for complex defines Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- arch/arm/plat-omap/include/dspbridge/dbc.h | 10 +- arch/arm/plat-omap/include/dspbridge/mem.h | 24 +- drivers/dsp/bridge/hw/MLBRegAcM.h | 319 ++++---- drivers/dsp/bridge/hw/MMURegAcM.h | 415 +++++----- drivers/dsp/bridge/hw/PRCMRegAcM.h | 1197 +++++++++++++--------------- drivers/dsp/bridge/wmd/_tiomap.h | 6 +- 6 files changed, 929 insertions(+), 1042 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/dbc.h b/arch/arm/plat-omap/include/dspbridge/dbc.h index 13b1ff6..a1a0b97 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbc.h +++ b/arch/arm/plat-omap/include/dspbridge/dbc.h @@ -34,10 +34,12 @@ #include <dspbridge/gt.h> -#define DBC_Assert(exp) \ - if (!(exp)) \ - printk(KERN_ERR "%s, line %d: Assertion (" #exp ") failed.\n", \ - __FILE__, __LINE__) +#define DBC_Assert(exp) \ +do { \ + if (!(exp)) \ + printk(KERN_ERR "%s, line %d: Assertion (" #exp ") failed.\n", \ + __FILE__, __LINE__); \ +} while (0) #define DBC_Require DBC_Assert /* Function Precondition. */ #define DBC_Ensure DBC_Assert /* Function Postcondition. */ diff --git a/arch/arm/plat-omap/include/dspbridge/mem.h b/arch/arm/plat-omap/include/dspbridge/mem.h index 276128c..d0db079 100644 --- a/arch/arm/plat-omap/include/dspbridge/mem.h +++ b/arch/arm/plat-omap/include/dspbridge/mem.h @@ -60,13 +60,13 @@ * Ensures: * A subsequent call to MEM_IsValidHandle() will succeed for this object. */ -#define MEM_AllocObject(pObj, Obj, Signature) \ -{ \ - pObj = MEM_Calloc(sizeof(Obj), MEM_NONPAGED); \ - if (pObj) { \ - pObj->dwSignature = Signature; \ - } \ -} +#define MEM_AllocObject(pObj, Obj, Signature) \ +do { \ + pObj = MEM_Calloc(sizeof(Obj), MEM_NONPAGED); \ + if (pObj) { \ + pObj->dwSignature = Signature; \ + } \ +} while (0) /* ======== MEM_AllocPhysMem ======== * Purpose: @@ -204,11 +204,11 @@ * Ensures: * A subsequent call to MEM_IsValidHandle() will fail for this object. */ -#define MEM_FreeObject(pObj) \ -{ \ - pObj->dwSignature = 0x00; \ - MEM_Free(pObj); \ -} +#define MEM_FreeObject(pObj) \ +do { \ + pObj->dwSignature = 0x00; \ + MEM_Free(pObj); \ +} while (0) /* * ======== MEM_GetNumPages ======== diff --git a/drivers/dsp/bridge/hw/MLBRegAcM.h b/drivers/dsp/bridge/hw/MLBRegAcM.h index 29f6de3..7f9accb 100644 --- a/drivers/dsp/bridge/hw/MLBRegAcM.h +++ b/drivers/dsp/bridge/hw/MLBRegAcM.h @@ -24,177 +24,158 @@ #if defined(USE_LEVEL_1_MACROS) -#define MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\ - __raw_readl(((baseAddress))+ \ - MLB_MAILBOX_SYSCONFIG_OFFSET)) - - -#define MLBMAILBOX_SYSCONFIGWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\ - __raw_writel(newValue, ((baseAddress))+offset);\ -} - - -#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ - MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ - MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) - - -#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(baseAddress, value)\ -{\ - const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ - register u32 data = __raw_readl(((u32)(baseAddress)) +\ - offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\ - data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ - newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ - newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(baseAddress, value)\ -{\ - const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ - register u32 data =\ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\ - data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ - newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ - newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ - MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ - MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) - - -#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(baseAddress, value)\ -{\ - const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ - register u32 data =\ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\ - data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ - newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ - newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - +#define MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32), \ + __raw_readl(((baseAddress)) + MLB_MAILBOX_SYSCONFIG_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET; \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\ + __raw_writel(newValue, ((baseAddress)) + offset); \ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (MLB_MAILBOX_SYSCONFIG_OFFSET)))) & \ + MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >> \ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(baseAddress, value) \ +do { \ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32); \ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK); \ + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET; \ + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(baseAddress, value) \ +do { \ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32); \ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK); \ + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET; \ + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (MLB_MAILBOX_SYSCONFIG_OFFSET)))) & \ + MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >> \ + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(baseAddress, value) \ +do { \ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32); \ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK); \ + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET; \ + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress)+offset); \ +} while (0) #define MLBMAILBOX_SYSSTATUSResetDoneRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ - MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ - MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) - - -#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress, bank)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\ - __raw_readl(((baseAddress))+\ - (MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ - MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\ - (bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) - - -#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(baseAddress, bank, value)\ -{\ - const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ - MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ - ((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\ - __raw_writel(newValue, ((baseAddress))+offset);\ -} - - -#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(baseAddress, bank)\ - (_DEBUG_LEVEL_1_EASI(\ - EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\ - __raw_readl(((u32)(baseAddress))+\ - (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ - MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\ - ((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) - - -#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress, bank)\ - (_DEBUG_LEVEL_1_EASI(\ - EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\ - (((__raw_readl(((baseAddress))+\ - (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ - MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\ - ((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\ - MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\ - MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) - - -#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress, bank)\ - (_DEBUG_LEVEL_1_EASI(\ - EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\ - (((__raw_readl(((baseAddress))+\ - (MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ - MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\ - ((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\ - MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\ - MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) - - -#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(baseAddress, bank)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\ - __raw_readl(((baseAddress))+\ - (MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ - MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ - ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) - - -#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, bank, value)\ -{\ - const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ - MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ - ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\ - __raw_writel(newValue, ((baseAddress))+offset);\ -} - - -#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress, bank)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\ - __raw_readl(((baseAddress))+\ - (MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ - MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\ - ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) - - -#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, bank, value)\ -{\ - const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ - MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ - ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\ - __raw_writel(newValue, ((baseAddress))+offset);\ -} - + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (MLB_MAILBOX_SYSSTATUS_OFFSET)))) & \ + MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >> \ + MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress, bank) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32), \ + __raw_readl(((baseAddress)) + \ + (MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET + \ + MLB_MAILBOX_MESSAGE___0_15_OFFSET + \ + ((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(baseAddress, bank, value) \ +do { \ + const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET + \ + MLB_MAILBOX_MESSAGE___0_15_OFFSET + \ + ((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32); \ + __raw_writel(newValue, ((baseAddress)) + offset); \ +} while (0) + +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(baseAddress, bank) \ + (_DEBUG_LEVEL_1_EASI \ + (EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + \ + (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET + \ + MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET + \ + ((bank) * MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress, bank) \ + (_DEBUG_LEVEL_1_EASI( \ + EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32), \ + (((__raw_readl(((baseAddress)) + \ + (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET + \ + MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET + \ + ((bank) * MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) & \ + MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >> \ + MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress, bank) \ + (_DEBUG_LEVEL_1_EASI( \ + EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32), \ + (((__raw_readl(((baseAddress)) + \ + (MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET + \ + MLB_MAILBOX_MSGSTATUS___0_15_OFFSET + \ + ((bank) * MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) & \ + MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >> \ + MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(baseAddress, bank) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32), \ + __raw_readl(((baseAddress)) + \ + (MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET + \ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET + \ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) + +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, bank, value) \ +do { \ + const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET + \ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET + \ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32); \ + __raw_writel(newValue, ((baseAddress)) + offset); \ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress, bank) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32), \ + __raw_readl(((baseAddress)) + \ + (MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET + \ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET + \ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) + + +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, bank, value) \ +do { \ + const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET + \ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET + \ + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32); \ + __raw_writel(newValue, ((baseAddress)) + offset); \ +} while (0) #endif /* USE_LEVEL_1_MACROS */ diff --git a/drivers/dsp/bridge/hw/MMURegAcM.h b/drivers/dsp/bridge/hw/MMURegAcM.h index 52a3d99..00ef881 100644 --- a/drivers/dsp/bridge/hw/MMURegAcM.h +++ b/drivers/dsp/bridge/hw/MMURegAcM.h @@ -25,227 +25,200 @@ #if defined(USE_LEVEL_1_MACROS) - -#define MMUMMU_SYSCONFIGReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET)) - - -#define MMUMMU_SYSCONFIGIdleModeWrite32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32);\ - data &= ~(MMU_MMU_SYSCONFIG_IdleMode_MASK);\ - newValue <<= MMU_MMU_SYSCONFIG_IdleMode_OFFSET;\ - newValue &= MMU_MMU_SYSCONFIG_IdleMode_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - - -#define MMUMMU_SYSCONFIGAutoIdleWrite32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32);\ - data &= ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK);\ - newValue <<= MMU_MMU_SYSCONFIG_AutoIdle_OFFSET;\ - newValue &= MMU_MMU_SYSCONFIG_AutoIdle_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - - -#define MMUMMU_IRQSTATUSReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET)) - - -#define MMUMMU_IRQSTATUSWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_IRQENABLEReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_IRQENABLE_OFFSET)) - - -#define MMUMMU_IRQENABLEWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_WALKING_STTWLRunningRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_WALKING_STTWLRunningRead32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\ - & MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\ - MMU_MMU_WALKING_ST_TWLRunning_OFFSET)) - - -#define MMUMMU_CNTLTWLEnableRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableRead32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\ - MMU_MMU_CNTL_TWLEnable_MASK) >>\ - MMU_MMU_CNTL_TWLEnable_OFFSET)) - - -#define MMUMMU_CNTLTWLEnableWrite32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_CNTL_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableWrite32);\ - data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\ - newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\ - newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - - -#define MMUMMU_CNTLMMUEnableWrite32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_CNTL_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLMMUEnableWrite32);\ - data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\ - newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\ - newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - - -#define MMUMMU_FAULT_ADReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FAULT_ADReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_FAULT_AD_OFFSET)) - - -#define MMUMMU_TTBWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_TTB_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_TTBWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_LOCKReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_LOCK_OFFSET)) - - -#define MMUMMU_LOCKWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_LOCKBaseValueRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueRead32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\ - MMU_MMU_LOCK_BaseValue_MASK) >>\ - MMU_MMU_LOCK_BaseValue_OFFSET)) - - -#define MMUMMU_LOCKBaseValueWrite32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\ - data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\ - newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\ - newValue &= MMU_MMU_LOCK_BaseValue_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - - -#define MMUMMU_LOCKCurrentVictimRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimRead32),\ - (((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\ - MMU_MMU_LOCK_CurrentVictim_MASK) >>\ - MMU_MMU_LOCK_CurrentVictim_OFFSET)) - - -#define MMUMMU_LOCKCurrentVictimWrite32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LOCK_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimWrite32);\ - data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\ - newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\ - newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\ - newValue |= data;\ - __raw_writel(newValue, baseAddress+offset);\ -} - - -#define MMUMMU_LOCKCurrentVictimSet32(var, value)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimSet32),\ - (((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\ - (((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\ - MMU_MMU_LOCK_CurrentVictim_MASK))) - - -#define MMUMMU_LD_TLBReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBReadRegister32),\ - __raw_readl((baseAddress)+MMU_MMU_LD_TLB_OFFSET)) - - -#define MMUMMU_LD_TLBWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_LD_TLB_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_CAMWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_CAM_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CAMWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_RAMWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_RAM_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_RAMWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define MMUMMU_FLUSH_ENTRYWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\ - register u32 newValue = (value);\ - _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32);\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - +#define MMUMMU_SYSCONFIGReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGReadRegister32), \ + __raw_readl((baseAddress) + MMU_MMU_SYSCONFIG_OFFSET)) + +#define MMUMMU_SYSCONFIGIdleModeWrite32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32); \ + data &= ~(MMU_MMU_SYSCONFIG_IdleMode_MASK); \ + newValue <<= MMU_MMU_SYSCONFIG_IdleMode_OFFSET; \ + newValue &= MMU_MMU_SYSCONFIG_IdleMode_MASK; \ + newValue |= data; \ + __raw_writel(newValue, baseAddress + offset); \ +} while (0) + +#define MMUMMU_SYSCONFIGAutoIdleWrite32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32); \ + data &= ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK); \ + newValue <<= MMU_MMU_SYSCONFIG_AutoIdle_OFFSET; \ + newValue &= MMU_MMU_SYSCONFIG_AutoIdle_MASK; \ + newValue |= data; \ + __raw_writel(newValue, baseAddress + offset); \ +} while (0) + +#define MMUMMU_IRQSTATUSReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32), \ + __raw_readl((baseAddress) + MMU_MMU_IRQSTATUS_OFFSET)) + +#define MMUMMU_IRQSTATUSWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_IRQSTATUS_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_IRQENABLEReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEReadRegister32), \ + __raw_readl((baseAddress) + MMU_MMU_IRQENABLE_OFFSET)) + +#define MMUMMU_IRQENABLEWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_WALKING_STTWLRunningRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_WALKING_STTWLRunningRead32), \ + (((__raw_readl(((baseAddress) + (MMU_MMU_WALKING_ST_OFFSET)))) \ + & MMU_MMU_WALKING_ST_TWLRunning_MASK) >> \ + MMU_MMU_WALKING_ST_TWLRunning_OFFSET)) + +#define MMUMMU_CNTLTWLEnableRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableRead32), \ + (((__raw_readl(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) & \ + MMU_MMU_CNTL_TWLEnable_MASK) >> \ + MMU_MMU_CNTL_TWLEnable_OFFSET)) + +#define MMUMMU_CNTLTWLEnableWrite32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_CNTL_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableWrite32); \ + data &= ~(MMU_MMU_CNTL_TWLEnable_MASK); \ + newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET; \ + newValue &= MMU_MMU_CNTL_TWLEnable_MASK; \ + newValue |= data; \ + __raw_writel(newValue, baseAddress+offset); \ +} while (0) + +#define MMUMMU_CNTLMMUEnableWrite32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_CNTL_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLMMUEnableWrite32); \ + data &= ~(MMU_MMU_CNTL_MMUEnable_MASK); \ + newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET; \ + newValue &= MMU_MMU_CNTL_MMUEnable_MASK; \ + newValue |= data; \ + __raw_writel(newValue, baseAddress + offset); \ +} while (0) + +#define MMUMMU_FAULT_ADReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FAULT_ADReadRegister32), \ + __raw_readl((baseAddress) + MMU_MMU_FAULT_AD_OFFSET)) + +#define MMUMMU_TTBWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_TTB_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_TTBWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_LOCKReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKReadRegister32), \ + __raw_readl((baseAddress) + MMU_MMU_LOCK_OFFSET)) + +#define MMUMMU_LOCKWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_LOCK_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_LOCKBaseValueRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueRead32), \ + (((__raw_readl(((baseAddress) + (MMU_MMU_LOCK_OFFSET)))) & \ + MMU_MMU_LOCK_BaseValue_MASK) >> MMU_MMU_LOCK_BaseValue_OFFSET)) \ + +#define MMUMMU_LOCKBaseValueWrite32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_LOCK_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32); \ + data &= ~(MMU_MMU_LOCK_BaseValue_MASK); \ + newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET; \ + newValue &= MMU_MMU_LOCK_BaseValue_MASK; \ + newValue |= data; \ + __raw_writel(newValue, baseAddress+offset); \ +} while (0) + +#define MMUMMU_LOCKCurrentVictimRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimRead32), \ + (((__raw_readl(((baseAddress) + (MMU_MMU_LOCK_OFFSET)))) & \ + MMU_MMU_LOCK_CurrentVictim_MASK) >> \ + MMU_MMU_LOCK_CurrentVictim_OFFSET)) + +#define MMUMMU_LOCKCurrentVictimWrite32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_LOCK_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimWrite32); \ + data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK); \ + newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET; \ + newValue &= MMU_MMU_LOCK_CurrentVictim_MASK; \ + newValue |= data; \ + __raw_writel(newValue, baseAddress + offset); \ +} while (0) + +#define MMUMMU_LOCKCurrentVictimSet32(var, value) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimSet32), \ + (((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) | \ + (((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) & \ + MMU_MMU_LOCK_CurrentVictim_MASK))) + +#define MMUMMU_LD_TLBReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBReadRegister32), \ + __raw_readl((baseAddress) + MMU_MMU_LD_TLB_OFFSET)) + +#define MMUMMU_LD_TLBWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_LD_TLB_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_CAMWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_CAM_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CAMWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_RAMWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_RAM_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_RAMWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define MMUMMU_FLUSH_ENTRYWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET; \ + register u32 newValue = (value); \ + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32); \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) #endif /* USE_LEVEL_1_MACROS */ diff --git a/drivers/dsp/bridge/hw/PRCMRegAcM.h b/drivers/dsp/bridge/hw/PRCMRegAcM.h index 4c9d732..080a998 100644 --- a/drivers/dsp/bridge/hw/PRCMRegAcM.h +++ b/drivers/dsp/bridge/hw/PRCMRegAcM.h @@ -26,644 +26,575 @@ #if defined(USE_LEVEL_1_MACROS) -#define PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32(baseAddress)\ -{\ - const u32 offset = PRCM_PRCM_CLKCFG_CTRL_OFFSET;\ - const u32 newValue = \ - (u32)PRCMPRCM_CLKCFG_CTRLValid_configClk_valid <<\ - PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(\ - EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32);\ - data &= ~(PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define CM_FCLKEN_PERReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\ - __raw_readl(((u32)(baseAddress))+CM_FCLKEN_PER_OFFSET)) - - -#define CM_ICLKEN_PERReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\ - __raw_readl(((u32)(baseAddress))+CM_ICLKEN_PER_OFFSET)) - - -#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress, value)\ -{\ - const u32 offset = CM_FCLKEN_PER_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\ - data &= ~(CM_FCLKEN_PER_GPT5_MASK);\ - newValue <<= CM_FCLKEN_PER_GPT5_OFFSET;\ - newValue &= CM_FCLKEN_PER_GPT5_MASK;\ - newValue |= data;\ - __raw_writel(newValue, ((u32)(baseAddress))+offset);\ -} - - -#define CM_FCLKEN_PER_GPT6WriteRegister32(baseAddress, value)\ -{\ - const u32 offset = CM_FCLKEN_PER_OFFSET;\ - register u32 data =\ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\ - data &= ~(CM_FCLKEN_PER_GPT6_MASK);\ - newValue <<= CM_FCLKEN_PER_GPT6_OFFSET;\ - newValue &= CM_FCLKEN_PER_GPT6_MASK;\ - newValue |= data;\ - __raw_writel(newValue, ((u32)(baseAddress))+offset);\ -} - - -#define CM_ICLKEN_PER_GPT5WriteRegister32(baseAddress, value)\ -{\ - const u32 offset = CM_ICLKEN_PER_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\ - data &= ~(CM_ICLKEN_PER_GPT5_MASK);\ - newValue <<= CM_ICLKEN_PER_GPT5_OFFSET;\ - newValue &= CM_ICLKEN_PER_GPT5_MASK;\ - newValue |= data;\ - __raw_writel(newValue, ((u32)(baseAddress))+offset);\ -} - - -#define CM_ICLKEN_PER_GPT6WriteRegister32(baseAddress, value)\ -{\ - const u32 offset = CM_ICLKEN_PER_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\ - data &= ~(CM_ICLKEN_PER_GPT6_MASK);\ - newValue <<= CM_ICLKEN_PER_GPT6_OFFSET;\ - newValue &= CM_ICLKEN_PER_GPT6_MASK;\ - newValue |= data;\ - __raw_writel(newValue, ((u32)(baseAddress))+offset);\ -} - - -#define CM_FCLKEN1_COREReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\ - __raw_readl(((u32)(baseAddress))+CM_FCLKEN1_CORE_OFFSET)) - - -#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32);\ - data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK);\ - newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET;\ - newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_FCLKEN1_COREEN_GPT7Write32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32);\ - data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK);\ - newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET;\ - newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define CM_ICLKEN1_COREReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREReadRegister32),\ - __raw_readl(((u32)(baseAddress))+CM_ICLKEN1_CORE_OFFSET)) - - -#define CM_ICLKEN1_COREEN_MAILBOXESWrite32(baseAddress, value)\ -{\ - const u32 offset = CM_ICLKEN1_CORE_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32);\ - data &= ~(CM_ICLKEN1_CORE_EN_MAILBOXES_MASK);\ - newValue <<= CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET;\ - newValue &= CM_ICLKEN1_CORE_EN_MAILBOXES_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_ICLKEN1_COREEN_GPT8Write32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32);\ - data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK);\ - newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET;\ - newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_ICLKEN1_COREEN_GPT7Write32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\ - register u32 data =\ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32);\ - data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK);\ - newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET;\ - newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT832k <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT732k <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define CM_CLKSEL_PER_GPT5Write32k32(baseAddress)\ -{\ - const u32 offset = CM_CLKSEL_PER_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\ - CM_CLKSEL_PER_GPT5_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT5Write32k32);\ - data &= ~(CM_CLKSEL_PER_GPT5_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define CM_CLKSEL_PER_GPT6Write32k32(baseAddress)\ -{\ - const u32 offset = CM_CLKSEL_PER_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\ - CM_CLKSEL_PER_GPT6_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT6Write32k32);\ - data &= ~(CM_CLKSEL_PER_GPT6_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32(baseAddress)\ -{\ - const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\ - const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext <<\ - PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\ - register u32 data = __raw_readl((u32)(baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32);\ - data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\ - data |= newValue;\ - __raw_writel(data, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (PRCM_CM_CLKSEL1_PLL_OFFSET)))) &\ - PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK) >>\ - PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET)) - - -#define CM_FCLKEN_IVA2EN_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = CM_FCLKEN_IVA2_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32);\ - data &= ~(CM_FCLKEN_IVA2_EN_MASK);\ - newValue <<= CM_FCLKEN_IVA2_EN_OFFSET;\ - newValue &= CM_FCLKEN_IVA2_EN_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_ICLKEN_DSP_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32);\ - data &= ~(PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK);\ - newValue <<= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET;\ - newValue &= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_IDLEST_DSPReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPReadRegister32),\ - __raw_readl(((u32)(baseAddress))+PRCM_CM_IDLEST_DSP_OFFSET)) - - -#define PRCMCM_IDLEST_DSPST_IPIRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (PRCM_CM_IDLEST_DSP_OFFSET)))) &\ - PRCM_CM_IDLEST_DSP_ST_IPI_MASK) >>\ - PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET)) +#define PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32(baseAddress) \ +do { \ + const u32 offset = PRCM_PRCM_CLKCFG_CTRL_OFFSET; \ + const u32 newValue = (u32)PRCMPRCM_CLKCFG_CTRLValid_configClk_valid << \ + PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI( \ + EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32); \ + data &= ~(PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define CM_FCLKEN_PERReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + CM_FCLKEN_PER_OFFSET)) + +#define CM_ICLKEN_PERReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + CM_ICLKEN_PER_OFFSET)) + +#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = CM_FCLKEN_PER_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32); \ + data &= ~(CM_FCLKEN_PER_GPT5_MASK); \ + newValue <<= CM_FCLKEN_PER_GPT5_OFFSET; \ + newValue &= CM_FCLKEN_PER_GPT5_MASK; \ + newValue |= data; \ + __raw_writel(newValue, ((u32)(baseAddress)) + offset); \ +} while (0) + +#define CM_FCLKEN_PER_GPT6WriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = CM_FCLKEN_PER_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32); \ + data &= ~(CM_FCLKEN_PER_GPT6_MASK); \ + newValue <<= CM_FCLKEN_PER_GPT6_OFFSET; \ + newValue &= CM_FCLKEN_PER_GPT6_MASK; \ + newValue |= data; \ + __raw_writel(newValue, ((u32)(baseAddress)) + offset); \ +} while (0) + +#define CM_ICLKEN_PER_GPT5WriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = CM_ICLKEN_PER_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32); \ + data &= ~(CM_ICLKEN_PER_GPT5_MASK); \ + newValue <<= CM_ICLKEN_PER_GPT5_OFFSET; \ + newValue &= CM_ICLKEN_PER_GPT5_MASK; \ + newValue |= data; \ + __raw_writel(newValue, ((u32)(baseAddress)) + offset); \ +} while (0) + +#define CM_ICLKEN_PER_GPT6WriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = CM_ICLKEN_PER_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32); \ + data &= ~(CM_ICLKEN_PER_GPT6_MASK); \ + newValue <<= CM_ICLKEN_PER_GPT6_OFFSET; \ + newValue &= CM_ICLKEN_PER_GPT6_MASK; \ + newValue |= data; \ + __raw_writel(newValue, ((u32)(baseAddress)) + offset); \ +} while (0) + +#define CM_FCLKEN1_COREReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + CM_FCLKEN1_CORE_OFFSET)) + + +#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32); \ + data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK); \ + newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET; \ + newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_FCLKEN1_COREEN_GPT7Write32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32); \ + data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK); \ + newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET; \ + newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define CM_ICLKEN1_COREReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + CM_ICLKEN1_CORE_OFFSET)) + +#define CM_ICLKEN1_COREEN_MAILBOXESWrite32(baseAddress, value) \ +do { \ + const u32 offset = CM_ICLKEN1_CORE_OFFSET; \ + register u32 data = \ + __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32); \ + data &= ~(CM_ICLKEN1_CORE_EN_MAILBOXES_MASK); \ + newValue <<= CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET; \ + newValue &= CM_ICLKEN1_CORE_EN_MAILBOXES_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_ICLKEN1_COREEN_GPT8Write32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32); \ + data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK); \ + newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET; \ + newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_ICLKEN1_COREEN_GPT7Write32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32); \ + data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK); \ + newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET; \ + newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT832k << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT732k << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define CM_CLKSEL_PER_GPT5Write32k32(baseAddress) \ +do { \ + const u32 offset = CM_CLKSEL_PER_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k << \ + CM_CLKSEL_PER_GPT5_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT5Write32k32); \ + data &= ~(CM_CLKSEL_PER_GPT5_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define CM_CLKSEL_PER_GPT6Write32k32(baseAddress) \ +do { \ + const u32 offset = CM_CLKSEL_PER_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k << \ + CM_CLKSEL_PER_GPT6_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT6Write32k32); \ + data &= ~(CM_CLKSEL_PER_GPT6_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0); + +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32(baseAddress) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET; \ + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext << \ + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET; \ + register u32 data = __raw_readl((u32)(baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32); \ + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK); \ + data |= newValue; \ + __raw_writel(data, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (PRCM_CM_CLKSEL1_PLL_OFFSET)))) & \ + PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK) >> \ + PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET)) + +#define CM_FCLKEN_IVA2EN_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = CM_FCLKEN_IVA2_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32); \ + data &= ~(CM_FCLKEN_IVA2_EN_MASK); \ + newValue <<= CM_FCLKEN_IVA2_EN_OFFSET; \ + newValue &= CM_FCLKEN_IVA2_EN_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_ICLKEN_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32); \ + data &= ~(PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK); \ + newValue <<= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET; \ + newValue &= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_IDLEST_DSPReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + PRCM_CM_IDLEST_DSP_OFFSET)) + + +#define PRCMCM_IDLEST_DSPST_IPIRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (PRCM_CM_IDLEST_DSP_OFFSET)))) & \ + PRCM_CM_IDLEST_DSP_ST_IPI_MASK) >> \ + PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET)) #define PRM_IDLEST_IVA2ST_IVA2Read32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (CM_IDLEST_IVA2_OFFSET)))) &\ - CM_IDLEST_IVA2_ST_IVA2_MASK) >>\ - CM_IDLEST_IVA2_ST_IVA2_OFFSET)) - - -#define PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_AUTOIDLE_DSP_OFFSET;\ - register u32 data =\ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32);\ - data &= ~(PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK);\ - newValue <<= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET;\ - newValue &= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL_DSPSYNC_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32);\ - data &= ~(PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK);\ - newValue <<= PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET;\ - newValue &= PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32);\ - data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK);\ - newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET;\ - newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32);\ - data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK);\ - newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET;\ - newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSTCTRL_IVA2WriteRegister32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_CLKSTCTRL_IVA2_OFFSET;\ - register u32 data = \ - __raw_readl(((baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32);\ - data &= ~(CM_CLKSTCTRL_IVA2_MASK);\ - newValue <<= CM_CLKSTCTRL_IVA2_OFFSET;\ - newValue &= CM_CLKSTCTRL_IVA2_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (PRCM_CM_CLKSTCTRL_DSP_OFFSET)))) &\ - PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK) >>\ - PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET)) - - -#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_CM_CLKSTCTRL_DSP_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32);\ - data &= ~(PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK);\ - newValue <<= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET;\ - newValue &= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32),\ - __raw_readl(((baseAddress))+PRCM_RM_RSTCTRL_DSP_OFFSET)) - - -#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\ - register u32 data =\ - __raw_readl(((baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\ - data &= ~(PRM_RSTCTRL_IVA2_RST1_MASK);\ - newValue <<= PRM_RSTCTRL_IVA2_RST1_OFFSET;\ - newValue &= PRM_RSTCTRL_IVA2_RST1_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\ - register u32 data =\ - __raw_readl(((baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\ - data &= ~(PRM_RSTCTRL_IVA2_RST2_MASK);\ - newValue <<= PRM_RSTCTRL_IVA2_RST2_OFFSET;\ - newValue &= PRM_RSTCTRL_IVA2_RST2_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, value)\ -{\ - const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\ - register u32 data =\ - __raw_readl(((baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\ - data &= ~(PRM_RSTCTRL_IVA2_RST3_MASK);\ - newValue <<= PRM_RSTCTRL_IVA2_RST3_OFFSET;\ - newValue &= PRM_RSTCTRL_IVA2_RST3_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (baseAddress)+offset);\ -} - - -#define PRCMRM_RSTST_DSPReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPReadRegister32),\ - __raw_readl(((baseAddress))+PRCM_RM_RSTST_DSP_OFFSET)) - - -#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress, value)\ -{\ - const u32 offset = PRCM_RM_RSTST_DSP_OFFSET;\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPWriteRegister32);\ - __raw_writel(newValue, ((u32)(baseAddress))+offset);\ -} - - -#define PRCMPM_PWSTCTRL_DSPForceStateWrite32(baseAddress, value)\ -{\ - const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\ - register u32 data = \ - __raw_readl(((u32)(baseAddress))+offset);\ - register u32 newValue = ((u32)(value));\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32);\ - data &= ~(PRCM_PM_PWSTCTRL_DSP_ForceState_MASK);\ - newValue <<= PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET;\ - newValue &= PRCM_PM_PWSTCTRL_DSP_ForceState_MASK;\ - newValue |= data;\ - __raw_writel(newValue, (u32)(baseAddress)+offset);\ -} - - -#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32(baseAddress)\ -{\ - const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\ - const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateON <<\ - PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32);\ - data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\ - data |= newValue;\ - __raw_writel(data, (baseAddress)+offset);\ -} - - -#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32(baseAddress)\ -{\ - const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\ - const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateOFF <<\ - PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32);\ - data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\ - data |= newValue;\ - __raw_writel(data, (baseAddress)+offset);\ -} - - -#define PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32(baseAddress)\ -{\ - const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\ - const u32 newValue = (u32)PRCMPM_PWSTCTRL_DSPPowerStateRET <<\ - PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET;\ - register u32 data = __raw_readl((baseAddress)+offset);\ - _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32);\ - data &= ~(PRCM_PM_PWSTCTRL_DSP_PowerState_MASK);\ - data |= newValue;\ - __raw_writel(data, (baseAddress)+offset);\ -} - - -#define PRCMPM_PWSTST_DSPReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPReadRegister32),\ - __raw_readl(((u32)(baseAddress))+PRCM_PM_PWSTST_DSP_OFFSET)) - - -#define PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32),\ - __raw_readl((baseAddress) + PRCM_PM_PWSTST_IVA2_OFFSET)) - - -#define PRCMPM_PWSTST_DSPInTransitionRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32),\ - (((__raw_readl((((u32)(baseAddress))+\ - (PRCM_PM_PWSTST_DSP_OFFSET)))) &\ - PRCM_PM_PWSTST_DSP_InTransition_MASK) >>\ - PRCM_PM_PWSTST_DSP_InTransition_OFFSET)) - - -#define PRCMPM_PWSTST_IVA2InTransitionRead32(baseAddress)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32),\ - (((__raw_readl((((baseAddress))+\ - (PRCM_PM_PWSTST_IVA2_OFFSET)))) &\ - PRCM_PM_PWSTST_IVA2_InTransition_MASK) >>\ - PRCM_PM_PWSTST_IVA2_InTransition_OFFSET)) - - -#define PRCMPM_PWSTST_DSPPowerStateStGet32(var)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPPowerStateStGet32),\ - (u32)((((u32)(var)) & PRCM_PM_PWSTST_DSP_PowerStateSt_MASK) >>\ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32), \ + (((__raw_readl((((u32)(baseAddress)) + (CM_IDLEST_IVA2_OFFSET)))) & \ + CM_IDLEST_IVA2_ST_IVA2_MASK) >> CM_IDLEST_IVA2_ST_IVA2_OFFSET)) + +#define PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_AUTOIDLE_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32); \ + data &= ~(PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK); \ + newValue <<= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET; \ + newValue &= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + + +#define PRCMCM_CLKSEL_DSPSYNC_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32); \ + data &= ~(PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK); \ + newValue <<= PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET; \ + newValue &= PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + + +#define PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32); \ + data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK); \ + newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET; \ + newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32); \ + data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK); \ + newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET; \ + newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMCM_CLKSTCTRL_IVA2WriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_CLKSTCTRL_IVA2_OFFSET; \ + register u32 data = __raw_readl(((baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32); \ + data &= ~(CM_CLKSTCTRL_IVA2_MASK); \ + newValue <<= CM_CLKSTCTRL_IVA2_OFFSET; \ + newValue &= CM_CLKSTCTRL_IVA2_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + + +#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (PRCM_CM_CLKSTCTRL_DSP_OFFSET)))) & \ + PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK) >> \ + PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET)) + +#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_CM_CLKSTCTRL_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32); \ + data &= ~(PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK); \ + newValue <<= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET; \ + newValue &= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32), \ + __raw_readl(((baseAddress)) + PRCM_RM_RSTCTRL_DSP_OFFSET)) + +#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET; \ + register u32 data = __raw_readl(((baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32); \ + data &= ~(PRM_RSTCTRL_IVA2_RST1_MASK); \ + newValue <<= PRM_RSTCTRL_IVA2_RST1_OFFSET; \ + newValue &= PRM_RSTCTRL_IVA2_RST1_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET; \ + register u32 data = __raw_readl(((baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32); \ + data &= ~(PRM_RSTCTRL_IVA2_RST2_MASK); \ + newValue <<= PRM_RSTCTRL_IVA2_RST2_OFFSET; \ + newValue &= PRM_RSTCTRL_IVA2_RST2_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET; \ + register u32 data = __raw_readl(((baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32); \ + data &= ~(PRM_RSTCTRL_IVA2_RST3_MASK); \ + newValue <<= PRM_RSTCTRL_IVA2_RST3_OFFSET; \ + newValue &= PRM_RSTCTRL_IVA2_RST3_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (baseAddress) + offset); \ +} while (0) + +#define PRCMRM_RSTST_DSPReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPReadRegister32), \ + __raw_readl(((baseAddress)) + PRCM_RM_RSTST_DSP_OFFSET)) + +#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_RM_RSTST_DSP_OFFSET; \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPWriteRegister32); \ + __raw_writel(newValue, ((u32)(baseAddress)) + offset); \ +} while (0) + +#define PRCMPM_PWSTCTRL_DSPForceStateWrite32(baseAddress, value) \ +do { \ + const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET; \ + register u32 data = __raw_readl(((u32)(baseAddress)) + offset); \ + register u32 newValue = ((u32)(value)); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32); \ + data &= ~(PRCM_PM_PWSTCTRL_DSP_ForceState_MASK); \ + newValue <<= PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET; \ + newValue &= PRCM_PM_PWSTCTRL_DSP_ForceState_MASK; \ + newValue |= data; \ + __raw_writel(newValue, (u32)(baseAddress) + offset); \ +} while (0) + +#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32(baseAddress) \ +do { \ + const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET; \ + const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateON << \ + PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32); \ + data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK); \ + data |= newValue; \ + __raw_writel(data, (baseAddress) + offset); \ +} while (0) + +#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32(baseAddress) \ +do { \ + const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET; \ + const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateOFF << \ + PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32); \ + data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK); \ + data |= newValue; \ + __raw_writel(data, (baseAddress) + offset); \ +} while (0) + +#define PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32(baseAddress) \ +do { \ + const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET; \ + const u32 newValue = (u32)PRCMPM_PWSTCTRL_DSPPowerStateRET << \ + PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET; \ + register u32 data = __raw_readl((baseAddress) + offset); \ + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32); \ + data &= ~(PRCM_PM_PWSTCTRL_DSP_PowerState_MASK); \ + data |= newValue; \ + __raw_writel(data, (baseAddress) + offset); \ +} while (0) + +#define PRCMPM_PWSTST_DSPReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPReadRegister32), \ + __raw_readl(((u32)(baseAddress)) + PRCM_PM_PWSTST_DSP_OFFSET)) + + +#define PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32), \ + __raw_readl((baseAddress) + PRCM_PM_PWSTST_IVA2_OFFSET)) + + +#define PRCMPM_PWSTST_DSPInTransitionRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32), \ + (((__raw_readl((((u32)(baseAddress)) + \ + (PRCM_PM_PWSTST_DSP_OFFSET)))) & \ + PRCM_PM_PWSTST_DSP_InTransition_MASK) >> \ + PRCM_PM_PWSTST_DSP_InTransition_OFFSET)) + +#define PRCMPM_PWSTST_IVA2InTransitionRead32(baseAddress) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32), \ + (((__raw_readl((((baseAddress)) + \ + (PRCM_PM_PWSTST_IVA2_OFFSET)))) & \ + PRCM_PM_PWSTST_IVA2_InTransition_MASK) >> \ + PRCM_PM_PWSTST_IVA2_InTransition_OFFSET)) + +#define PRCMPM_PWSTST_DSPPowerStateStGet32(var) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPPowerStateStGet32), \ + (u32)((((u32)(var)) & PRCM_PM_PWSTST_DSP_PowerStateSt_MASK) >> \ PRCM_PM_PWSTST_DSP_PowerStateSt_OFFSET)) - -#define PRCMPM_PWSTST_IVA2PowerStateStGet32(var)\ - (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2PowerStateStGet32),\ - (u32)((((u32)(var)) & PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK) >>\ - PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET)) - +#define PRCMPM_PWSTST_IVA2PowerStateStGet32(var) \ + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2PowerStateStGet32), \ + (u32)((((u32)(var)) & PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK) >> \ + PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET)) #endif /* USE_LEVEL_1_MACROS */ diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h index 5c613b4..d5399bd 100644 --- a/drivers/dsp/bridge/wmd/_tiomap.h +++ b/drivers/dsp/bridge/wmd/_tiomap.h @@ -317,9 +317,9 @@ enum INTH_SensitiveEdge_t { #define ClearBit(reg, mask) (reg &= ~mask) #define SetBit(reg, mask) (reg |= mask) -#define SetGroupBits16(reg, position, width, value) \ - do {\ - reg &= ~((0xFFFF >> (16 - (width))) << (position)) ; \ +#define SetGroupBits16(reg, position, width, value) \ + do { \ + reg &= ~((0xFFFF >> (16 - (width))) << (position)); \ reg |= ((value & (0xFFFF >> (16 - (width)))) << (position)); \ } while (0); -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 14/20] DSPBRIDGE: Use _IOxx macro to define ioctls 2009-11-30 21:54 ` [PATCH v2 13/20] DSPBRIDGE: Fix multiline macros to use do while Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Nishant Menon - Use standard convention to define ioctls. - Removed runtime check for ioctl matching table number. - Added __deprectaed marker to functions that are not used anymore. Currently 'DB' is used as identifier for dspbridge. Added TODOs for removing the function table and, deprecated and not implemented ioctls, this can be done when all the ioctls are accessed through a switch instead of a pointer to function. *** NOTE: An update in api ioctl definitions is required. *** Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Nishant Menon <nm@ti.com> --- arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 144 ++++++++++------------- drivers/dsp/bridge/pmgr/wcd.c | 131 ++++++++++----------- 2 files changed, 128 insertions(+), 147 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h index 397361c..f2fb408 100644 --- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h +++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h @@ -391,83 +391,69 @@ union Trapped_Args { } ARGS_UTIL_TESTDLL; } ; -#define CMD_BASE 101 - -/* MGR module offsets */ -#define CMD_MGR_BASE_OFFSET CMD_BASE -#define CMD_MGR_ENUMNODE_INFO_OFFSET (CMD_MGR_BASE_OFFSET + 0) -#define CMD_MGR_ENUMPROC_INFO_OFFSET (CMD_MGR_BASE_OFFSET + 1) -#define CMD_MGR_REGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 2) -#define CMD_MGR_UNREGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 3) -#define CMD_MGR_WAIT_OFFSET (CMD_MGR_BASE_OFFSET + 4) - -#ifndef RES_CLEANUP_DISABLE -#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5) -#define CMD_MGR_END_OFFSET CMD_MGR_RESOUCES_OFFSET -#else -#define CMD_MGR_END_OFFSET CMD_MGR_WAIT_OFFSET -#endif - -#define CMD_PROC_BASE_OFFSET (CMD_MGR_END_OFFSET + 1) -#define CMD_PROC_ATTACH_OFFSET (CMD_PROC_BASE_OFFSET + 0) -#define CMD_PROC_CTRL_OFFSET (CMD_PROC_BASE_OFFSET + 1) -#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2) -#define CMD_PROC_ENUMNODE_OFFSET (CMD_PROC_BASE_OFFSET + 3) -#define CMD_PROC_ENUMRESOURCES_OFFSET (CMD_PROC_BASE_OFFSET + 4) -#define CMD_PROC_GETSTATE_OFFSET (CMD_PROC_BASE_OFFSET + 5) -#define CMD_PROC_GETTRACE_OFFSET (CMD_PROC_BASE_OFFSET + 6) -#define CMD_PROC_LOAD_OFFSET (CMD_PROC_BASE_OFFSET + 7) -#define CMD_PROC_REGISTERNOTIFY_OFFSET (CMD_PROC_BASE_OFFSET + 8) -#define CMD_PROC_START_OFFSET (CMD_PROC_BASE_OFFSET + 9) -#define CMD_PROC_RSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 10) -#define CMD_PROC_UNRSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 11) -#define CMD_PROC_MAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 12) -#define CMD_PROC_UNMAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 13) -#define CMD_PROC_FLUSHMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 14) -#define CMD_PROC_STOP_OFFSET (CMD_PROC_BASE_OFFSET + 15) -#define CMD_PROC_INVALIDATEMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 16) -#define CMD_PROC_END_OFFSET CMD_PROC_INVALIDATEMEMORY_OFFSET - - -#define CMD_NODE_BASE_OFFSET (CMD_PROC_END_OFFSET + 1) -#define CMD_NODE_ALLOCATE_OFFSET (CMD_NODE_BASE_OFFSET + 0) -#define CMD_NODE_ALLOCMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 1) -#define CMD_NODE_CHANGEPRIORITY_OFFSET (CMD_NODE_BASE_OFFSET + 2) -#define CMD_NODE_CONNECT_OFFSET (CMD_NODE_BASE_OFFSET + 3) -#define CMD_NODE_CREATE_OFFSET (CMD_NODE_BASE_OFFSET + 4) -#define CMD_NODE_DELETE_OFFSET (CMD_NODE_BASE_OFFSET + 5) -#define CMD_NODE_FREEMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 6) -#define CMD_NODE_GETATTR_OFFSET (CMD_NODE_BASE_OFFSET + 7) -#define CMD_NODE_GETMESSAGE_OFFSET (CMD_NODE_BASE_OFFSET + 8) -#define CMD_NODE_PAUSE_OFFSET (CMD_NODE_BASE_OFFSET + 9) -#define CMD_NODE_PUTMESSAGE_OFFSET (CMD_NODE_BASE_OFFSET + 10) -#define CMD_NODE_REGISTERNOTIFY_OFFSET (CMD_NODE_BASE_OFFSET + 11) -#define CMD_NODE_RUN_OFFSET (CMD_NODE_BASE_OFFSET + 12) -#define CMD_NODE_TERMINATE_OFFSET (CMD_NODE_BASE_OFFSET + 13) -#define CMD_NODE_GETUUIDPROPS_OFFSET (CMD_NODE_BASE_OFFSET + 14) -#define CMD_NODE_END_OFFSET CMD_NODE_GETUUIDPROPS_OFFSET - -#define CMD_STRM_BASE_OFFSET (CMD_NODE_END_OFFSET + 1) -#define CMD_STRM_ALLOCATEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 0) -#define CMD_STRM_CLOSE_OFFSET (CMD_STRM_BASE_OFFSET + 1) -#define CMD_STRM_FREEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 2) -#define CMD_STRM_GETEVENTHANDLE_OFFSET (CMD_STRM_BASE_OFFSET + 3) -#define CMD_STRM_GETINFO_OFFSET (CMD_STRM_BASE_OFFSET + 4) -#define CMD_STRM_IDLE_OFFSET (CMD_STRM_BASE_OFFSET + 5) -#define CMD_STRM_ISSUE_OFFSET (CMD_STRM_BASE_OFFSET + 6) -#define CMD_STRM_OPEN_OFFSET (CMD_STRM_BASE_OFFSET + 7) -#define CMD_STRM_RECLAIM_OFFSET (CMD_STRM_BASE_OFFSET + 8) -#define CMD_STRM_REGISTERNOTIFY_OFFSET (CMD_STRM_BASE_OFFSET + 9) -#define CMD_STRM_SELECT_OFFSET (CMD_STRM_BASE_OFFSET + 10) -#define CMD_STRM_END_OFFSET CMD_STRM_SELECT_OFFSET - -/* Communication Memory Manager (UCMM) */ -#define CMD_CMM_BASE_OFFSET (CMD_STRM_END_OFFSET + 1) -#define CMD_CMM_ALLOCBUF_OFFSET (CMD_CMM_BASE_OFFSET + 0) -#define CMD_CMM_FREEBUF_OFFSET (CMD_CMM_BASE_OFFSET + 1) -#define CMD_CMM_GETHANDLE_OFFSET (CMD_CMM_BASE_OFFSET + 2) -#define CMD_CMM_GETINFO_OFFSET (CMD_CMM_BASE_OFFSET + 3) -#define CMD_CMM_END_OFFSET CMD_CMM_GETINFO_OFFSET - -#define CMD_BASE_END_OFFSET CMD_CMM_END_OFFSET +/* TODO: Remove deprecated and not implemented */ + +/* MGR module */ +#define MGR_ENUMNODE_INFO _IOWR('DB', 0, unsigned long) +#define MGR_ENUMPROC_INFO _IOWR('DB', 1, unsigned long) +#define MGR_REGISTEROBJECT _IOWR('DB', 2, unsigned long) +#define MGR_UNREGISTEROBJECT _IOWR('DB', 3, unsigned long) /* Deprecated */ +#define MGR_WAIT _IOWR('DB', 4, unsigned long) +#define MGR_GET_PROC_RES _IOR('DB', 5, unsigned long) /* Deprecated */ + +/* PROC Module */ +#define PROC_ATTACH _IOWR('DB', 6, unsigned long) +#define PROC_CTRL _IOR('DB', 7, unsigned long) +#define PROC_DETACH _IOR('DB', 8, unsigned long) /* Deprecated */ +#define PROC_ENUMNODE _IOWR('DB', 9, unsigned long) +#define PROC_ENUMRESOURCES _IOWR('DB', 10, unsigned long) +#define PROC_GET_STATE _IOWR('DB', 11, unsigned long) +#define PROC_GET_TRACE _IOWR('DB', 12, unsigned long) +#define PROC_LOAD _IOW('DB', 13, unsigned long) +#define PROC_REGISTERNOTIFY _IOWR('DB', 14, unsigned long) +#define PROC_START _IOW('DB', 15, unsigned long) +#define PROC_RSVMEM _IOWR('DB', 16, unsigned long) +#define PROC_UNRSVMEM _IOW('DB', 17, unsigned long) +#define PROC_MAPMEM _IOWR('DB', 18, unsigned long) +#define PROC_UNMAPMEM _IOR('DB', 19, unsigned long) +#define PROC_FLUSHMEMORY _IOW('DB', 20, unsigned long) +#define PROC_STOP _IOWR('DB', 21, unsigned long) +#define PROC_INVALIDATEMEMORY _IOW('DB', 22, unsigned long) + +/* NODE Module */ +#define NODE_ALLOCATE _IOWR('DB', 23, unsigned long) +#define NODE_ALLOCMSGBUF _IOWR('DB', 24, unsigned long) +#define NODE_CHANGEPRIORITY _IOW('DB', 25, unsigned long) +#define NODE_CONNECT _IOW('DB', 26, unsigned long) +#define NODE_CREATE _IOW('DB', 27, unsigned long) +#define NODE_DELETE _IOW('DB', 28, unsigned long) +#define NODE_FREEMSGBUF _IOW('DB', 29, unsigned long) +#define NODE_GETATTR _IOWR('DB', 30, unsigned long) +#define NODE_GETMESSAGE _IOWR('DB', 31, unsigned long) +#define NODE_PAUSE _IOW('DB', 32, unsigned long) +#define NODE_PUTMESSAGE _IOW('DB', 33, unsigned long) +#define NODE_REGISTERNOTIFY _IOWR('DB', 34, unsigned long) +#define NODE_RUN _IOW('DB', 35, unsigned long) +#define NODE_TERMINATE _IOWR('DB', 36, unsigned long) +#define NODE_GETUUIDPROPS _IOWR('DB', 37, unsigned long) + +/* STRM Module */ +#define STRM_ALLOCATEBUFFER _IOWR('DB', 38, unsigned long) +#define STRM_CLOSE _IOW('DB', 39, unsigned long) +#define STRM_FREEBUFFER _IOWR('DB', 40, unsigned long) +#define STRM_GETEVENTHANDLE _IO('DB', 41) /* Not Impl'd */ +#define STRM_GETINFO _IOWR('DB', 42, unsigned long) +#define STRM_IDLE _IOW('DB', 43, unsigned long) +#define STRM_ISSUE _IOW('DB', 44, unsigned long) +#define STRM_OPEN _IOWR('DB', 45, unsigned long) +#define STRM_RECLAIM _IOWR('DB', 46, unsigned long) +#define STRM_REGISTERNOTIFY _IOWR('DB', 47, unsigned long) +#define STRM_SELECT _IOWR('DB', 48, unsigned long) + +/* CMM Module */ +#define CMM_ALLOCBUF _IO('DB', 49) /* Not Impl'd */ +#define CMM_FREEBUF _IO('DB', 50) /* Not Impl'd */ +#define CMM_GETHANDLE _IOR('DB', 51, unsigned long) +#define CMM_GETINFO _IOR('DB', 52, unsigned long) + #endif /* WCDIOCTL_ */ diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c index dd0dcdc..fb83da9 100644 --- a/drivers/dsp/bridge/pmgr/wcd.c +++ b/drivers/dsp/bridge/pmgr/wcd.c @@ -88,6 +88,7 @@ static struct GT_Mask WCD_debugMask = { NULL, NULL }; /* Core VxD Mask */ #endif static u32 WCD_cRefs; +/* TODO: Remove function table */ /* * Function table. * The order of these functions MUST be the same as the order of the command @@ -96,65 +97,65 @@ static u32 WCD_cRefs; */ static struct WCD_Cmd WCD_cmdTable[] = { /* MGR module */ - {MGRWRAP_EnumNode_Info, CMD_MGR_ENUMNODE_INFO_OFFSET}, - {MGRWRAP_EnumProc_Info, CMD_MGR_ENUMPROC_INFO_OFFSET}, - {MGRWRAP_RegisterObject, CMD_MGR_REGISTEROBJECT_OFFSET}, - {MGRWRAP_UnregisterObject, CMD_MGR_UNREGISTEROBJECT_OFFSET}, - {MGRWRAP_WaitForBridgeEvents, CMD_MGR_WAIT_OFFSET}, + {MGRWRAP_EnumNode_Info}, /* MGR_ENUMNODE_INFO */ + {MGRWRAP_EnumProc_Info}, /* MGR_ENUMPROC_INFO */ + {MGRWRAP_RegisterObject}, /* MGR_REGISTEROBJECT */ + {MGRWRAP_UnregisterObject}, /* MGR_UNREGISTEROBJECT */ + {MGRWRAP_WaitForBridgeEvents}, /* MGR_WAIT */ #ifndef RES_CLEANUP_DISABLE - {MGRWRAP_GetProcessResourcesInfo, CMD_MGR_RESOUCES_OFFSET}, + {MGRWRAP_GetProcessResourcesInfo}, /* MGR_GET_PROC_RES */ #endif /* PROC Module */ - {PROCWRAP_Attach, CMD_PROC_ATTACH_OFFSET}, - {PROCWRAP_Ctrl, CMD_PROC_CTRL_OFFSET}, - {PROCWRAP_Detach, CMD_PROC_DETACH_OFFSET}, - {PROCWRAP_EnumNode_Info, CMD_PROC_ENUMNODE_OFFSET}, - {PROCWRAP_EnumResources, CMD_PROC_ENUMRESOURCES_OFFSET}, - {PROCWRAP_GetState, CMD_PROC_GETSTATE_OFFSET}, - {PROCWRAP_GetTrace, CMD_PROC_GETTRACE_OFFSET}, - {PROCWRAP_Load, CMD_PROC_LOAD_OFFSET}, - {PROCWRAP_RegisterNotify, CMD_PROC_REGISTERNOTIFY_OFFSET}, - {PROCWRAP_Start, CMD_PROC_START_OFFSET}, - {PROCWRAP_ReserveMemory, CMD_PROC_RSVMEM_OFFSET}, - {PROCWRAP_UnReserveMemory, CMD_PROC_UNRSVMEM_OFFSET}, - {PROCWRAP_Map, CMD_PROC_MAPMEM_OFFSET}, - {PROCWRAP_UnMap, CMD_PROC_UNMAPMEM_OFFSET}, - {PROCWRAP_FlushMemory, CMD_PROC_FLUSHMEMORY_OFFSET}, - {PROCWRAP_Stop, CMD_PROC_STOP_OFFSET}, - {PROCWRAP_InvalidateMemory, CMD_PROC_INVALIDATEMEMORY_OFFSET}, + {PROCWRAP_Attach}, /* PROC_ATTACH */ + {PROCWRAP_Ctrl}, /* PROC_CTRL */ + {PROCWRAP_Detach}, /* PROC_DETACH */ + {PROCWRAP_EnumNode_Info}, /* PROC_ENUMNODE */ + {PROCWRAP_EnumResources}, /* PROC_ENUMRESOURCES */ + {PROCWRAP_GetState}, /* PROC_GET_STATE */ + {PROCWRAP_GetTrace}, /* PROC_GET_TRACE */ + {PROCWRAP_Load}, /* PROC_LOAD */ + {PROCWRAP_RegisterNotify}, /* PROC_REGISTERNOTIFY */ + {PROCWRAP_Start}, /* PROC_START */ + {PROCWRAP_ReserveMemory}, /* PROC_RSVMEM */ + {PROCWRAP_UnReserveMemory}, /* PROC_UNRSVMEM */ + {PROCWRAP_Map}, /* PROC_MAPMEM */ + {PROCWRAP_UnMap}, /* PROC_UNMAPMEM */ + {PROCWRAP_FlushMemory}, /* PROC_FLUSHMEMORY */ + {PROCWRAP_Stop}, /* PROC_STOP */ + {PROCWRAP_InvalidateMemory}, /* PROC_INVALIDATEMEMORY */ /* NODE Module */ - {NODEWRAP_Allocate, CMD_NODE_ALLOCATE_OFFSET}, - {NODEWRAP_AllocMsgBuf, CMD_NODE_ALLOCMSGBUF_OFFSET}, - {NODEWRAP_ChangePriority, CMD_NODE_CHANGEPRIORITY_OFFSET}, - {NODEWRAP_Connect, CMD_NODE_CONNECT_OFFSET}, - {NODEWRAP_Create, CMD_NODE_CREATE_OFFSET}, - {NODEWRAP_Delete, CMD_NODE_DELETE_OFFSET}, - {NODEWRAP_FreeMsgBuf, CMD_NODE_FREEMSGBUF_OFFSET}, - {NODEWRAP_GetAttr, CMD_NODE_GETATTR_OFFSET}, - {NODEWRAP_GetMessage, CMD_NODE_GETMESSAGE_OFFSET}, - {NODEWRAP_Pause, CMD_NODE_PAUSE_OFFSET}, - {NODEWRAP_PutMessage, CMD_NODE_PUTMESSAGE_OFFSET}, - {NODEWRAP_RegisterNotify, CMD_NODE_REGISTERNOTIFY_OFFSET}, - {NODEWRAP_Run, CMD_NODE_RUN_OFFSET}, - {NODEWRAP_Terminate, CMD_NODE_TERMINATE_OFFSET}, - {NODEWRAP_GetUUIDProps, CMD_NODE_GETUUIDPROPS_OFFSET}, + {NODEWRAP_Allocate}, /* NODE_ALLOCATE */ + {NODEWRAP_AllocMsgBuf}, /* NODE_ALLOCMSGBUF */ + {NODEWRAP_ChangePriority}, /* NODE_CHANGEPRIORITY */ + {NODEWRAP_Connect}, /* NODE_CONNECT */ + {NODEWRAP_Create}, /* NODE_CREATE */ + {NODEWRAP_Delete}, /* NODE_DELETE */ + {NODEWRAP_FreeMsgBuf}, /* NODE_FREEMSGBUF */ + {NODEWRAP_GetAttr}, /* NODE_GETATTR */ + {NODEWRAP_GetMessage}, /* NODE_GETMESSAGE */ + {NODEWRAP_Pause}, /* NODE_PAUSE */ + {NODEWRAP_PutMessage}, /* NODE_PUTMESSAGE */ + {NODEWRAP_RegisterNotify}, /* NODE_REGISTERNOTIFY */ + {NODEWRAP_Run}, /* NODE_RUN */ + {NODEWRAP_Terminate}, /* NODE_TERMINATE */ + {NODEWRAP_GetUUIDProps}, /* NODE_GETUUIDPROPS */ /* STRM wrapper functions */ - {STRMWRAP_AllocateBuffer, CMD_STRM_ALLOCATEBUFFER_OFFSET}, - {STRMWRAP_Close, CMD_STRM_CLOSE_OFFSET}, - {STRMWRAP_FreeBuffer, CMD_STRM_FREEBUFFER_OFFSET}, - {STRMWRAP_GetEventHandle, CMD_STRM_GETEVENTHANDLE_OFFSET}, - {STRMWRAP_GetInfo, CMD_STRM_GETINFO_OFFSET}, - {STRMWRAP_Idle, CMD_STRM_IDLE_OFFSET}, - {STRMWRAP_Issue, CMD_STRM_ISSUE_OFFSET}, - {STRMWRAP_Open, CMD_STRM_OPEN_OFFSET}, - {STRMWRAP_Reclaim, CMD_STRM_RECLAIM_OFFSET}, - {STRMWRAP_RegisterNotify, CMD_STRM_REGISTERNOTIFY_OFFSET}, - {STRMWRAP_Select, CMD_STRM_SELECT_OFFSET}, + {STRMWRAP_AllocateBuffer}, /* STRM_ALLOCATEBUFFER */ + {STRMWRAP_Close}, /* STRM_CLOSE */ + {STRMWRAP_FreeBuffer}, /* STRM_FREEBUFFER */ + {STRMWRAP_GetEventHandle}, /* STRM_GETEVENTHANDLE */ + {STRMWRAP_GetInfo}, /* STRM_GETINFO */ + {STRMWRAP_Idle}, /* STRM_IDLE */ + {STRMWRAP_Issue}, /* STRM_ISSUE */ + {STRMWRAP_Open}, /* STRM_OPEN */ + {STRMWRAP_Reclaim}, /* STRM_RECLAIM */ + {STRMWRAP_RegisterNotify}, /* STRM_REGISTERNOTIFY */ + {STRMWRAP_Select}, /* STRM_SELECT */ /* CMM module */ - {CMMWRAP_CallocBuf, CMD_CMM_ALLOCBUF_OFFSET}, - {CMMWRAP_FreeBuf, CMD_CMM_FREEBUF_OFFSET}, - {CMMWRAP_GetHandle, CMD_CMM_GETHANDLE_OFFSET}, - {CMMWRAP_GetInfo, CMD_CMM_GETINFO_OFFSET} + {CMMWRAP_CallocBuf}, /* CMM_ALLOCBUF */ + {CMMWRAP_FreeBuf}, /* CMM_FREEBUF */ + {CMMWRAP_GetHandle}, /* CMM_GETHANDLE */ + {CMMWRAP_GetInfo}, /* CMM_GETINFO */ }; static inline void __cp_fm_usr(void *to, const void __user *from, @@ -237,8 +238,7 @@ static int memory_check_vma(void *start_addr, u32 len) inline DSP_STATUS WCD_CallDevIOCtl(u32 cmd, union Trapped_Args *args, u32 *pResult, void *pr_ctxt) { - cmd -= CMD_BASE; - + cmd = _IOC_NR(cmd); if (cmd < ARRAY_SIZE(WCD_cmdTable)) { /* make the fxn call via the cmd table */ *pResult = (*WCD_cmdTable[cmd].fxn) (args, pr_ctxt); @@ -287,14 +287,7 @@ bool WCD_Init(void) bool fInit = true; bool fDRV, fDEV, fCOD, fSERVICES, fCHNL, fMSG, fIO; bool fMGR, fPROC, fNODE, fDISP, fNTFY, fSTRM, fRMM; -#ifdef DEBUG - /* runtime check of Device IOCtl array. */ - u32 i; - int cmdtable = ARRAY_SIZE(WCD_cmdTable); - for (i = 0; i < cmdtable; i++) - DBC_Assert(WCD_cmdTable[i].dwIndex == i + CMD_BASE); -#endif if (WCD_cRefs == 0) { /* initialize all SERVICES modules */ fSERVICES = SERVICES_Init(); @@ -423,6 +416,8 @@ DSP_STATUS WCD_InitComplete2(void) return status; } +/* TODO: Remove deprecated and not implemented ioctl wrappers */ + /* * ======== MGRWRAP_EnumNode_Info ======== */ @@ -574,7 +569,7 @@ func_end: /* * ======== MGRWRAP_UnregisterObject ======== */ -u32 MGRWRAP_UnregisterObject(union Trapped_Args *args, void *pr_ctxt) +u32 __deprecated MGRWRAP_UnregisterObject(union Trapped_Args *args, void *pr_ctxt) { /* This API is deprecated */ return DSP_SOK; @@ -625,7 +620,7 @@ u32 MGRWRAP_WaitForBridgeEvents(union Trapped_Args *args, void *pr_ctxt) /* * ======== MGRWRAP_GetProcessResourceInfo ======== */ -u32 MGRWRAP_GetProcessResourcesInfo(union Trapped_Args *args, void *pr_ctxt) +u32 __deprecated MGRWRAP_GetProcessResourcesInfo(union Trapped_Args *args, void *pr_ctxt) { DSP_STATUS status = DSP_SOK; u32 uSize = 0; @@ -728,7 +723,7 @@ func_end: /* * ======== PROCWRAP_Detach ======== */ -u32 PROCWRAP_Detach(union Trapped_Args *args, void *pr_ctxt) +u32 __deprecated PROCWRAP_Detach(union Trapped_Args *args, void *pr_ctxt) { GT_1trace(WCD_debugMask, GT_ENTER, "PROCWRAP_Detach: entered args\n0x%x " @@ -1648,7 +1643,7 @@ u32 STRMWRAP_FreeBuffer(union Trapped_Args *args, void *pr_ctxt) /* * ======== STRMWRAP_GetEventHandle ======== */ -u32 STRMWRAP_GetEventHandle(union Trapped_Args *args, void *pr_ctxt) +u32 __deprecated STRMWRAP_GetEventHandle(union Trapped_Args *args, void *pr_ctxt) { return DSP_ENOTIMPL; } @@ -1846,7 +1841,7 @@ u32 STRMWRAP_Select(union Trapped_Args *args, void *pr_ctxt) /* * ======== CMMWRAP_CallocBuf ======== */ -u32 CMMWRAP_CallocBuf(union Trapped_Args *args, void *pr_ctxt) +u32 __deprecated CMMWRAP_CallocBuf(union Trapped_Args *args, void *pr_ctxt) { /* This operation is done in kernel */ return DSP_ENOTIMPL; @@ -1855,7 +1850,7 @@ u32 CMMWRAP_CallocBuf(union Trapped_Args *args, void *pr_ctxt) /* * ======== CMMWRAP_FreeBuf ======== */ -u32 CMMWRAP_FreeBuf(union Trapped_Args *args, void *pr_ctxt) +u32 __deprecated CMMWRAP_FreeBuf(union Trapped_Args *args, void *pr_ctxt) { /* This operation is done in kernel */ return DSP_ENOTIMPL; -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm 2009-11-30 21:54 ` [PATCH v2 14/20] DSPBRIDGE: Use _IOxx macro to define ioctls Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 16/20] DSPBRIDGE: trivial fix for multiline comments on io_sm Omar Ramirez Luna 2009-12-01 6:43 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Andy Shevchenko 0 siblings, 2 replies; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna Remove duplicate set of braces from if statement and reduce indentation. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- drivers/dsp/bridge/wmd/io_sm.c | 96 +++++++++++++++++----------------------- 1 files changed, 40 insertions(+), 56 deletions(-) diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index af31831..96a5aa6 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -115,7 +115,7 @@ struct IO_MGR { /* private extnd proc info; mmu setup */ struct MGR_PROCESSOREXTINFO extProcInfo; struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ - struct work_struct io_workq; /*workqueue */ + struct work_struct io_workq; /*workqueue */ u32 dQuePowerMbxVal[MAX_PM_REQS]; u32 iQuePowerHead; u32 iQuePowerTail; @@ -185,7 +185,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, struct CFG_HOSTRES hostRes; struct CFG_DEVNODE *hDevNode; struct CHNL_MGR *hChnlMgr; - static int ref_count; + static int ref_count; u32 devType; /* Check requirements: */ if (!phIOMgr || !pMgrAttrs || pMgrAttrs->uWordSize == 0) { @@ -197,9 +197,10 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = DSP_EHANDLE; goto func_end; } - /* Message manager will be created when a file is loaded, since + /* Message manager will be created when a file is loaded, since * size of message buffer in shared memory is configurable in - * the base image. */ + * the base image. + */ DEV_GetWMDContext(hDevObject, &hWmdContext); if (!hWmdContext) { status = DSP_EHANDLE; @@ -209,7 +210,8 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, /* DSP shared memory area will get set properly when * a program is loaded. They are unknown until a COFF file is * loaded. I chose the value -1 because it was less likely to be - * a valid address than 0. */ + * a valid address than 0. + */ pSharedMem = (struct SHM *) -1; if (DSP_FAILED(status)) goto func_cont; @@ -230,7 +232,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = DSP_EMEMORY; goto func_cont; } - /*Intializing Work Element*/ + /* Intializing Work Element */ if (ref_count == 0) { INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM); ref_count = 1; @@ -319,7 +321,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) SYNC_DeleteCS(hIOMgr->hCSObj); /* Leak Fix. */ /* Free this IO manager object: */ MEM_FreeObject(hIOMgr); - } else + } else status = DSP_EHANDLE; return status; @@ -445,19 +447,16 @@ func_cont1: #endif if (DSP_FAILED(status)) status = CHNL_E_NOMEMMAP; - } if (DSP_SUCCEEDED(status)) { status = COD_GetSymValue(hCodMan, DYNEXTBASE, &ulDynExtBase); if (DSP_FAILED(status)) status = CHNL_E_NOMEMMAP; - } if (DSP_SUCCEEDED(status)) { status = COD_GetSymValue(hCodMan, EXTEND, &ulExtEnd); if (DSP_FAILED(status)) status = CHNL_E_NOMEMMAP; - } if (DSP_SUCCEEDED(status)) { /* Get memory reserved in host resources */ @@ -609,7 +608,7 @@ func_cont1: } } - /* Copy remaining entries from CDB. All entries are 1 MB and should not + /* Copy remaining entries from CDB. All entries are 1 MB and should not * conflict with SHM entries on MPU or DSP side */ for (i = 3; i < 7 && ndx < WMDIOCTL_NUMOFMMUTLB && DSP_SUCCEEDED(status); i++) { @@ -726,9 +725,9 @@ func_cont: } DBC_Assert(ulShmBase != 0); if (DSP_SUCCEEDED(status)) { + /* Register SM */ status = registerSHMSegs(hIOMgr, hCodMan, aEProc[0].ulGppPa); - /* Register SM */ } } } @@ -780,7 +779,6 @@ func_cont: &hIOMgr->ulTraceBufferBegin); if (DSP_FAILED(status)) status = CHNL_E_NOMEMMAP; - } hIOMgr->ulGPPReadPointer = hIOMgr->ulTraceBufferBegin = (ulGppVa + ulSeg1Size + ulPadSize) + @@ -791,7 +789,6 @@ func_cont: &hIOMgr->ulTraceBufferEnd); if (DSP_FAILED(status)) status = CHNL_E_NOMEMMAP; - } hIOMgr->ulTraceBufferEnd = (ulGppVa + ulSeg1Size + ulPadSize) + (hIOMgr->ulTraceBufferEnd - ulDspVa); @@ -802,7 +799,6 @@ func_cont: &hIOMgr->ulTraceBufferCurrent); if (DSP_FAILED(status)) status = CHNL_E_NOMEMMAP; - } hIOMgr->ulTraceBufferCurrent = (ulGppVa + ulSeg1Size + ulPadSize) + (hIOMgr-> @@ -957,9 +953,7 @@ static void IO_DispatchPM(struct work_struct *work) pIOMgr->iQuePowerTail++; if (pIOMgr->iQuePowerTail >= MAX_PM_REQS) pIOMgr->iQuePowerTail = 0; - } - } /* @@ -988,7 +982,6 @@ void IO_DPC(IN OUT void *pRefData) /* notify DSP/BIOS exception */ if (hDehMgr) WMD_DEH_Notify(hDehMgr, DSP_SYSERROR, pIOMgr->wIntrVal); - } IO_DispatchChnl(pIOMgr, NULL, IO_SERVICE); #ifdef CHNL_MESSAGES @@ -1002,15 +995,10 @@ void IO_DPC(IN OUT void *pRefData) PrintDSPDebugTrace(pIOMgr); } #endif - -#ifndef DSP_TRACEBUF_DISABLED - PrintDSPDebugTrace(pIOMgr); -#endif func_end: return; } - /* * ======== IO_ISR ======== * Main interrupt handler for the shared memory IO manager. @@ -1028,29 +1016,28 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) /* Call WMD's CHNLSM_ISR() to see if interrupt is ours, and process. */ if (IO_CALLISR(hIOMgr->hWmdContext, &fSchedDPC, &hIOMgr->wIntrVal)) { - { - DBG_Trace(DBG_LEVEL3, "IO_ISR %x\n", hIOMgr->wIntrVal); - if (hIOMgr->wIntrVal & MBX_PM_CLASS) { - hIOMgr->dQuePowerMbxVal[hIOMgr->iQuePowerHead] = - hIOMgr->wIntrVal; - hIOMgr->iQuePowerHead++; - if (hIOMgr->iQuePowerHead >= MAX_PM_REQS) - hIOMgr->iQuePowerHead = 0; - - queue_work(bridge_workqueue, &hIOMgr->io_workq); - } - if (hIOMgr->wIntrVal == MBX_DEH_RESET) { - DBG_Trace(DBG_LEVEL6, "*** DSP RESET ***\n"); - hIOMgr->wIntrVal = 0; - } else if (fSchedDPC) { - /* PROC-COPY defer i/o */ - DPC_Schedule(hIOMgr->hDPC); - } + DBG_Trace(DBG_LEVEL3, "IO_ISR %x\n", hIOMgr->wIntrVal); + if (hIOMgr->wIntrVal & MBX_PM_CLASS) { + hIOMgr->dQuePowerMbxVal[hIOMgr->iQuePowerHead] = + hIOMgr->wIntrVal; + hIOMgr->iQuePowerHead++; + if (hIOMgr->iQuePowerHead >= MAX_PM_REQS) + hIOMgr->iQuePowerHead = 0; + + queue_work(bridge_workqueue, &hIOMgr->io_workq); + } + if (hIOMgr->wIntrVal == MBX_DEH_RESET) { + DBG_Trace(DBG_LEVEL6, "*** DSP RESET ***\n"); + hIOMgr->wIntrVal = 0; + } else if (fSchedDPC) { + /* PROC-COPY defer i/o */ + DPC_Schedule(hIOMgr->hDPC); } - } else + } else /* Ensure that, if WMD didn't claim it, the IRQ is shared. */ DBC_Ensure(hIOMgr->fSharedIRQ); - return IRQ_HANDLED; + + return IRQ_HANDLED; } /* @@ -1131,7 +1118,6 @@ static u32 FindReadyOutput(struct CHNL_MGR *pChnlMgr, uRetval = id; if (pChnl == NULL) pChnlMgr->dwLastOutput = id; - break; } id = id + 1; @@ -1362,8 +1348,7 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) CHNLSM_InterruptDSP2(pIOMgr->hWmdContext, MBX_PCPY_CLASS); } func_end: - return; - + return; } /* @@ -1380,10 +1365,10 @@ static void NotifyChnlComplete(struct CHNL_OBJECT *pChnl, !pChnl->pIOCompletions || !pChirp) goto func_end; - /* Note: we signal the channel event only if the queue of IO - * completions is empty. If it is not empty, the event is sure to be - * signalled by the only IO completion list consumer: - * WMD_CHNL_GetIOC(). */ + /* Note: we signal the channel event only if the queue of IO + * completions is empty. If it is not empty, the event is sure to be + * signalled by the only IO completion list consumer: + * WMD_CHNL_GetIOC(). */ fSignalEvent = LST_IsEmpty(pChnl->pIOCompletions); /* Enqueue the IO completion info for the client: */ LST_PutTail(pChnl->pIOCompletions, (struct LST_ELEM *) pChirp); @@ -1434,7 +1419,7 @@ static void OutputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, goto func_end; pChnl = pChnlMgr->apChannel[chnlId]; - if (!pChnl || !pChnl->pIORequests) { + if (!pChnl || !pChnl->pIORequests) { /* Shouldn't get here: */ goto func_end; } @@ -1570,8 +1555,7 @@ static void OutputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) } } func_end: - return; - + return; } /* @@ -1711,7 +1695,7 @@ static u32 ReadData(struct WMD_DEV_CONTEXT *hDevContext, void *pDest, * Copies buffers from the host side buffer to the shared memory. */ static u32 WriteData(struct WMD_DEV_CONTEXT *hDevContext, void *pDest, - void *pSrc, u32 uSize) + void *pSrc, u32 uSize) { memcpy(pDest, pSrc, uSize); return uSize; @@ -1814,7 +1798,7 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) { u32 ulNewMessageLength = 0, ulGPPCurPointer; - GT_0trace(dsp_trace_mask, GT_ENTER, "Entering PrintDSPDebugTrace\n"); + GT_0trace(dsp_trace_mask, GT_ENTER, "Entering PrintDSPDebugTrace\n"); while (true) { /* Get the DSP current pointer */ @@ -1832,7 +1816,7 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) ulGPPReadPointer; memcpy(hIOMgr->pMsg, (char *)hIOMgr->ulGPPReadPointer, - ulNewMessageLength); + ulNewMessageLength); hIOMgr->pMsg[ulNewMessageLength] = '\0'; /* Advance the GPP trace pointer to DSP current * pointer */ -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 16/20] DSPBRIDGE: trivial fix for multiline comments on io_sm 2009-11-30 21:54 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 17/20] DSPBRIDGE: Remove DPC, create, destroy and schedule wrappers Omar Ramirez Luna 2009-12-01 6:43 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Andy Shevchenko 1 sibling, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna, Artem Bityutskiy, Felipe Balbi This patch corrects current style for comments on io_sm.c - Fix multiline comments according to Documentation/CodingStyle Functions comments will be addressed in a different patch. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> CC: Artem Bityutskiy <dedekind1@gmail.com> CC: Felipe Balbi <felipe.balbi@nokia.com> --- drivers/dsp/bridge/wmd/io_sm.c | 409 +++++++++++++++++++++++----------------- 1 files changed, 237 insertions(+), 172 deletions(-) diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index 96a5aa6..8fcf150 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -17,14 +17,14 @@ */ /* - * Channel Invariant: - * There is an important invariant condition which must be maintained per - * channel outside of WMD_CHNL_GetIOC() and IO_Dispatch(), violation of - * which may cause timeouts and/or failure of the SYNC_WaitOnEvent - * function. + * Channel Invariant: + * There is an important invariant condition which must be maintained per + * channel outside of WMD_CHNL_GetIOC() and IO_Dispatch(), violation of + * which may cause timeouts and/or failure of the SYNC_WaitOnEvent + * function. */ -/* ----------------------------------- Host OS */ +/* Host OS */ #include <dspbridge/host_os.h> #include <linux/workqueue.h> @@ -32,16 +32,16 @@ #include <mach/omap-pm.h> #endif -/* ----------------------------------- DSP/BIOS Bridge */ +/* DSP/BIOS Bridge */ #include <dspbridge/std.h> #include <dspbridge/dbdefs.h> #include <dspbridge/errbase.h> -/* ----------------------------------- Trace & Debug */ +/* Trace & Debug */ #include <dspbridge/dbc.h> #include <dspbridge/dbg.h> -/* ----------------------------------- OS Adaptation Layer */ +/* Services Layer */ #include <dspbridge/cfg.h> #include <dspbridge/dpc.h> #include <dspbridge/mem.h> @@ -49,11 +49,11 @@ #include <dspbridge/sync.h> #include <dspbridge/reg.h> -/* ------------------------------------ Hardware Abstraction Layer */ +/* Hardware Abstraction Layer */ #include <hw_defs.h> #include <hw_mmu.h> -/* ----------------------------------- Mini Driver */ +/* Mini Driver */ #include <dspbridge/wmddeh.h> #include <dspbridge/wmdio.h> #include <dspbridge/wmdioctl.h> @@ -61,25 +61,25 @@ #include <tiomap_io.h> #include <_tiomap_pwr.h> -/* ----------------------------------- Platform Manager */ +/* Platform Manager */ #include <dspbridge/cod.h> #include <dspbridge/dev.h> #include <dspbridge/chnl_sm.h> -/* ----------------------------------- Others */ +/* Others */ #include <dspbridge/rms_sh.h> #include <dspbridge/mgr.h> #include <dspbridge/drv.h> #include "_cmm.h" -/* ----------------------------------- This */ +/* This */ #include <dspbridge/io_sm.h> #include "_msg_sm.h" #include <dspbridge/gt.h> -/* ----------------------------------- Defines, Data Structures, Typedefs */ +/* Defines, Data Structures, Typedefs */ #define OUTPUTNOTREADY 0xffff -#define NOTENABLED 0xffff /* channel(s) not enabled */ +#define NOTENABLED 0xffff /* Channel(s) not enabled */ #define EXTEND "_EXT_END" @@ -88,34 +88,34 @@ #define MAX_PM_REQS 32 -/* IO Manager: only one created per board: */ +/* IO Manager: only one created per board */ struct IO_MGR { - /* These four fields must be the first fields in a IO_MGR_ struct: */ - u32 dwSignature; /* Used for object validation */ - struct WMD_DEV_CONTEXT *hWmdContext; /* WMD device context */ + /* These four fields must be the first fields in a IO_MGR_ struct */ + u32 dwSignature; /* Used for object validation */ + struct WMD_DEV_CONTEXT *hWmdContext; /* WMD device context */ struct WMD_DRV_INTERFACE *pIntfFxns; /* Function interface to WMD */ struct DEV_OBJECT *hDevObject; /* Device this board represents */ - /* These fields initialized in WMD_IO_Create(): */ + /* These fields initialized in WMD_IO_Create() */ struct CHNL_MGR *hChnlMgr; - struct SHM *pSharedMem; /* Shared Memory control */ - u8 *pInput; /* Address of input channel */ - u8 *pOutput; /* Address of output channel */ + struct SHM *pSharedMem; /* Shared Memory control */ + u8 *pInput; /* Address of input channel */ + u8 *pOutput; /* Address of output channel */ struct MSG_MGR *hMsgMgr; /* Message manager */ struct MSG *pMsgInputCtrl; /* Msg control for from DSP messages */ struct MSG *pMsgOutputCtrl; /* Msg control for to DSP messages */ - u8 *pMsgInput; /* Address of input messages */ - u8 *pMsgOutput; /* Address of output messages */ + u8 *pMsgInput; /* Address of input messages */ + u8 *pMsgOutput; /* Address of output messages */ u32 uSMBufSize; /* Size of a shared memory I/O channel */ - bool fSharedIRQ; /* Is this IRQ shared? */ - struct DPC_OBJECT *hDPC; /* DPC object handle */ + bool fSharedIRQ; /* Is this IRQ shared? */ + struct DPC_OBJECT *hDPC; /* DPC object handle */ struct SYNC_CSOBJECT *hCSObj; /* Critical section object handle */ - u32 uWordSize; /* Size in bytes of DSP word */ - u16 wIntrVal; /* interrupt value */ - /* private extnd proc info; mmu setup */ + u32 uWordSize; /* Size in bytes of DSP word */ + u16 wIntrVal; /* Interrupt value */ + /* Private extnd proc info; mmu setup */ struct MGR_PROCESSOREXTINFO extProcInfo; - struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ - struct work_struct io_workq; /*workqueue */ + struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ + struct work_struct io_workq; /* workqueue */ u32 dQuePowerMbxVal[MAX_PM_REQS]; u32 iQuePowerHead; u32 iQuePowerTail; @@ -130,7 +130,7 @@ struct IO_MGR { #endif } ; -/* ----------------------------------- Function Prototypes */ +/* Function Prototypes */ static void IO_DispatchChnl(IN struct IO_MGR *pIOMgr, IN OUT struct CHNL_OBJECT *pChnl, u32 iMode); static void IO_DispatchMsg(IN struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr); @@ -154,7 +154,7 @@ static struct workqueue_struct *bridge_workqueue; void PrintDSPDebugTrace(struct IO_MGR *hIOMgr); #endif -/* Bus Addr (cached kernel)*/ +/* Bus Addr (cached kernel) */ static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr, struct COD_MANAGER *hCodMan, u32 dwGPPBasePA); @@ -187,7 +187,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, struct CHNL_MGR *hChnlMgr; static int ref_count; u32 devType; - /* Check requirements: */ + /* Check requirements */ if (!phIOMgr || !pMgrAttrs || pMgrAttrs->uWordSize == 0) { status = DSP_EHANDLE; goto func_end; @@ -197,9 +197,10 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = DSP_EHANDLE; goto func_end; } - /* Message manager will be created when a file is loaded, since - * size of message buffer in shared memory is configurable in - * the base image. + /* + * Message manager will be created when a file is loaded, since + * size of message buffer in shared memory is configurable in + * the base image. */ DEV_GetWMDContext(hDevObject, &hWmdContext); if (!hWmdContext) { @@ -207,18 +208,17 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, goto func_end; } DEV_GetDevType(hDevObject, &devType); - /* DSP shared memory area will get set properly when - * a program is loaded. They are unknown until a COFF file is - * loaded. I chose the value -1 because it was less likely to be - * a valid address than 0. + /* + * DSP shared memory area will get set properly when + * a program is loaded. They are unknown until a COFF file is + * loaded. I chose the value -1 because it was less likely to be + * a valid address than 0. */ pSharedMem = (struct SHM *) -1; if (DSP_FAILED(status)) goto func_cont; - /* - * Create a Single Threaded Work Queue - */ + /* Create a Single Threaded Work Queue */ if (ref_count == 0) bridge_workqueue = create_workqueue("bridge_work-queue"); @@ -226,7 +226,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, DBG_Trace(DBG_LEVEL1, "Workque Create failed 0x%d \n", bridge_workqueue); - /* Allocate IO manager object: */ + /* Allocate IO manager object */ MEM_AllocObject(pIOMgr, struct IO_MGR, IO_MGRSIGNATURE); if (pIOMgr == NULL) { status = DSP_EMEMORY; @@ -239,7 +239,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, } else PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM); - /* Initialize CHNL_MGR object: */ + /* Initialize CHNL_MGR object */ #ifndef DSP_TRACEBUF_DISABLED pIOMgr->pMsg = NULL; #endif @@ -250,7 +250,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = SYNC_InitializeCS(&pIOMgr->hCSObj); if (devType == DSP_UNIT) { - /* Create a DPC object: */ + /* Create a DPC object */ status = DPC_Create(&pIOMgr->hDPC, IO_DPC, (void *)pIOMgr); if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -281,7 +281,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = CHNL_E_ISR; func_cont: if (DSP_FAILED(status)) { - /* Cleanup: */ + /* Cleanup */ WMD_IO_Destroy(pIOMgr); *phIOMgr = NULL; } else { @@ -303,8 +303,8 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) DSP_STATUS status = DSP_SOK; struct WMD_DEV_CONTEXT *hWmdContext; if (MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE)) { - /* Unplug IRQ: */ - /* Disable interrupts from the board: */ + /* Unplug IRQ */ + /* Disable interrupts from the board */ status = DEV_GetWMDContext(hIOMgr->hDevObject, &hWmdContext); if (DSP_SUCCEEDED(status)) (void)CHNLSM_DisableInterrupt(hWmdContext); @@ -319,7 +319,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) MEM_Free(hIOMgr->pMsg); #endif SYNC_DeleteCS(hIOMgr->hCSObj); /* Leak Fix. */ - /* Free this IO manager object: */ + /* Free this IO manager object */ MEM_FreeObject(hIOMgr); } else status = DSP_EHANDLE; @@ -376,7 +376,7 @@ DSP_STATUS WMD_IO_OnLoaded(struct IO_MGR *hIOMgr) if (DSP_FAILED(status)) goto func_end; hChnlMgr = hIOMgr->hChnlMgr; - /* The message manager is destroyed when the board is stopped. */ + /* The message manager is destroyed when the board is stopped. */ DEV_GetMsgMgr(hIOMgr->hDevObject, &hIOMgr->hMsgMgr); hMsgMgr = hIOMgr->hMsgMgr; if (!MEM_IsValidHandle(hChnlMgr, CHNL_MGRSIGNATURE) || @@ -403,7 +403,7 @@ DSP_STATUS WMD_IO_OnLoaded(struct IO_MGR *hIOMgr) if (ulShmLimit <= ulShmBase) { status = CHNL_E_INVALIDMEMBASE; } else { - /* get total length in bytes */ + /* Get total length in bytes */ ulShmLength = (ulShmLimit - ulShmBase + 1) * hIOMgr->uWordSize; /* Calculate size of a PROCCOPY shared memory region */ DBG_Trace(DBG_LEVEL7, @@ -423,12 +423,16 @@ func_cont1: if (ulMsgLimit <= ulMsgBase) { status = CHNL_E_INVALIDMEMBASE; } else { - /* Length (bytes) of messaging part of shared - * memory */ + /* + * Length (bytes) of messaging part of shared + * memory. + */ ulMsgLength = (ulMsgLimit - ulMsgBase + 1) * hIOMgr->uWordSize; - /* Total length (bytes) of shared memory: - * chnl + msg */ + /* + * Total length (bytes) of shared memory: + * chnl + msg. + */ ulMemLength = ulShmLength + ulMsgLength; } } else { @@ -470,7 +474,7 @@ func_cont1: ndx = 0; ulGppPa = hostRes.dwMemPhys[1]; ulGppVa = hostRes.dwMemBase[1]; - /* THIS IS THE VIRTUAL UNCACHED IOREMAPPED ADDRESS !!! */ + /* This is the virtual uncached ioremapped address!!! */ /* Why can't we directly take the DSPVA from the symbols? */ ulDspVa = hIOMgr->extProcInfo.tyTlb[0].ulDspVirt; ulSegSize = (ulShm0End - ulDspVa) * hIOMgr->uWordSize; @@ -522,8 +526,10 @@ func_cont1: mapAttrs |= DSP_MAPDONOTLOCK; while (numBytes && DSP_SUCCEEDED(status)) { - /* To find the max. page size with which both PA & VA are - * aligned */ + /* + * To find the max. page size with which both PA & VA are + * aligned. + */ allBits = paCurr | vaCurr; DBG_Trace(DBG_LEVEL1, "allBits %x, paCurr %x, vaCurr %x, " "numBytes %x\n", allBits, paCurr, vaCurr, numBytes); @@ -539,9 +545,11 @@ func_cont1: vaCurr += pgSize[i]; gppVaCurr += pgSize[i]; numBytes -= pgSize[i]; - /* Don't try smaller sizes. Hopefully we have + /* + * Don't try smaller sizes. Hopefully we have * reached an address aligned to a bigger page - * size*/ + * size. + */ break; } } @@ -550,13 +558,15 @@ func_cont1: vaCurr += ulPadSize; gppVaCurr += ulPadSize; - /* configure the TLB entries for the next cacheable segment */ + /* Configure the TLB entries for the next cacheable segment */ numBytes = ulSegSize; vaCurr = ulDspVa * hIOMgr->uWordSize; allBits = 0x0; while (numBytes && DSP_SUCCEEDED(status)) { - /* To find the max. page size with which both PA & VA are - * aligned*/ + /* + * To find the max. page size with which both PA & VA are + * aligned. + */ allBits = paCurr | vaCurr; DBG_Trace(DBG_LEVEL1, "allBits for Seg1 %x, paCurr %x, " "vaCurr %x, numBytes %x\n", allBits, paCurr, vaCurr, @@ -566,11 +576,15 @@ func_cont1: !((allBits & (pgSize[i]-1)) == 0)) continue; if (ndx < MAX_LOCK_TLB_ENTRIES) { - /* This is the physical address written to - * DSP MMU */ + /* + * This is the physical address written to + * DSP MMU. + */ aEProc[ndx].ulGppPa = paCurr; - /* THIS IS THE VIRTUAL UNCACHED IOREMAPPED - * ADDRESS!!! */ + /* + * This is the virtual uncached ioremapped + * address!!! + */ aEProc[ndx].ulGppVa = gppVaCurr; aEProc[ndx].ulDspVa = vaCurr / hIOMgr-> uWordSize; @@ -602,14 +616,18 @@ func_cont1: vaCurr += pgSize[i]; gppVaCurr += pgSize[i]; numBytes -= pgSize[i]; - /* Don't try smaller sizes. Hopefully we have reached - an address aligned to a bigger page size*/ + /* + * Don't try smaller sizes. Hopefully we have reached + * an address aligned to a bigger page size. + */ break; } } - /* Copy remaining entries from CDB. All entries are 1 MB and should not - * conflict with SHM entries on MPU or DSP side */ + /* + * Copy remaining entries from CDB. All entries are 1 MB and + * should not conflict with SHM entries on MPU or DSP side. + */ for (i = 3; i < 7 && ndx < WMDIOCTL_NUMOFMMUTLB && DSP_SUCCEEDED(status); i++) { if (hIOMgr->extProcInfo.tyTlb[i].ulGppPhys == 0) @@ -636,8 +654,8 @@ func_cont1: aEProc[ndx].ulGppPa = hIOMgr->extProcInfo. tyTlb[i].ulGppPhys; aEProc[ndx].ulGppVa = 0; - /* Can't convert, so set to zero*/ - aEProc[ndx].ulSize = 0x100000; /* 1 MB*/ + /* Can't convert, so set to zero */ + aEProc[ndx].ulSize = 0x100000; /* 1 MB */ DBG_Trace(DBG_LEVEL1, "SHM MMU entry PA %x " "DSP_VA 0x%x\n", aEProc[ndx].ulGppPa, aEProc[ndx].ulDspVa); @@ -652,7 +670,7 @@ func_cont1: } } if (i < 7 && DSP_SUCCEEDED(status)) { - /* All CDB entries could not be made*/ + /* All CDB entries could not be made */ status = DSP_EFAIL; } func_cont: @@ -681,15 +699,19 @@ func_cont: aEProc[i].ulGppVa = 0; aEProc[i].ulSize = 0; } - /* Set the SHM physical address entry (grayed out in CDB file) + /* + * Set the SHM physical address entry (grayed out in CDB file) * to the virtual uncached ioremapped address of SHM reserved - * on MPU */ + * on MPU. + */ hIOMgr->extProcInfo.tyTlb[0].ulGppPhys = (ulGppVa + ulSeg1Size + ulPadSize); DBG_Trace(DBG_LEVEL1, "*********extProcInfo *********%x \n", hIOMgr->extProcInfo.tyTlb[0].ulGppPhys); - /* Need SHM Phys addr. IO supports only one DSP for now: - * uNumProcs=1 */ + /* + * Need SHM Phys addr. IO supports only one DSP for now: + * uNumProcs=1. + */ if ((hIOMgr->extProcInfo.tyTlb[0].ulGppPhys == 0) || (uNumProcs != 1)) { status = CHNL_E_NOMEMMAP; @@ -702,10 +724,12 @@ func_cont: /* ulShmBase may not be at ulDspVa address */ ulShmBaseOffset = (ulShmBase - aEProc[0].ulDspVa) * hIOMgr->uWordSize; - /* WMD_BRD_Ctrl() will set dev context dsp-mmu info. In - * _BRD_Start() the MMU will be re-programed with MMU - * DSPVa-GPPPa pair info while DSP is in a known - * (reset) state. */ + /* + * WMD_BRD_Ctrl() will set dev context dsp-mmu info. In + * _BRD_Start() the MMU will be re-programed with MMU + * DSPVa-GPPPa pair info while DSP is in a known + * (reset) state. + */ if (!hIOMgr->pIntfFxns || !hIOMgr->hWmdContext) { status = DSP_EHANDLE; goto func_end; @@ -745,7 +769,7 @@ func_cont: "pSharedMem %p uSMBufSize %x sizeof(SHM) %x\n", hIOMgr->pSharedMem, hIOMgr->uSMBufSize, sizeof(struct SHM)); - /* Set up Shared memory addresses for messaging. */ + /* Set up Shared memory addresses for messaging. */ hIOMgr->pMsgInputCtrl = (struct MSG *)((u8 *) hIOMgr->pSharedMem + ulShmLength); @@ -847,7 +871,7 @@ void IO_CancelChnl(struct IO_MGR *hIOMgr, u32 ulChnl) goto func_end; sm = hIOMgr->pSharedMem; - /* Inform DSP that we have no more buffers on this channel: */ + /* Inform DSP that we have no more buffers on this channel */ IO_AndValue(pIOMgr->hWmdContext, struct SHM, sm, hostFreeMask, (~(1 << ulChnl))); @@ -868,11 +892,11 @@ static void IO_DispatchChnl(IN struct IO_MGR *pIOMgr, DBG_Trace(DBG_LEVEL3, "Entering IO_DispatchChnl \n"); - /* See if there is any data available for transfer: */ + /* See if there is any data available for transfer */ if (iMode != IO_SERVICE) goto func_end; - /* Any channel will do for this mode: */ + /* Any channel will do for this mode */ InputChnl(pIOMgr, pChnl, iMode); OutputChnl(pIOMgr, pChnl, iMode); func_end: @@ -890,7 +914,7 @@ static void IO_DispatchMsg(IN struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) DBG_Trace(DBG_LEVEL3, "Entering IO_DispatchMsg \n"); - /* We are performing both input and output processing. */ + /* We are performing both input and output processing. */ InputMsg(pIOMgr, hMsgMgr); OutputMsg(pIOMgr, hMsgMgr); func_end: @@ -949,7 +973,7 @@ static void IO_DispatchPM(struct work_struct *work) *pArg); } } - /* increment the tail count here */ + /* Increment the tail count here */ pIOMgr->iQuePowerTail++; if (pIOMgr->iQuePowerTail >= MAX_PM_REQS) pIOMgr->iQuePowerTail = 0; @@ -979,7 +1003,7 @@ void IO_DPC(IN OUT void *pRefData) DBG_Trace(DBG_LEVEL7, "Entering IO_DPC(0x%x)\n", pRefData); /* Check value of interrupt register to ensure it is a valid error */ if ((pIOMgr->wIntrVal > DEH_BASE) && (pIOMgr->wIntrVal < DEH_LIMIT)) { - /* notify DSP/BIOS exception */ + /* Notify DSP/BIOS exception */ if (hDehMgr) WMD_DEH_Notify(hDehMgr, DSP_SYSERROR, pIOMgr->wIntrVal); } @@ -990,7 +1014,7 @@ void IO_DPC(IN OUT void *pRefData) #endif #ifndef DSP_TRACEBUF_DISABLED if (pIOMgr->wIntrVal & MBX_DBG_CLASS) { - /* notify DSP Trace message */ + /* Notify DSP Trace message */ if (pIOMgr->wIntrVal & MBX_DBG_SYSPRINTF) PrintDSPDebugTrace(pIOMgr); } @@ -1030,7 +1054,7 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) DBG_Trace(DBG_LEVEL6, "*** DSP RESET ***\n"); hIOMgr->wIntrVal = 0; } else if (fSchedDPC) { - /* PROC-COPY defer i/o */ + /* PROC-COPY defer i/o */ DPC_Schedule(hIOMgr->hDPC); } } else @@ -1057,21 +1081,27 @@ void IO_RequestChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, pChnlMgr = pIOMgr->hChnlMgr; sm = pIOMgr->pSharedMem; if (iMode == IO_INPUT) { - /* Assertion fires if CHNL_AddIOReq() called on a stream - * which was cancelled, or attached to a dead board: */ + /* + * Assertion fires if CHNL_AddIOReq() called on a stream + * which was cancelled, or attached to a dead board. + */ DBC_Assert((pChnl->dwState == CHNL_STATEREADY) || (pChnl->dwState == CHNL_STATEEOS)); - /* Indicate to the DSP we have a buffer available for input: */ + /* Indicate to the DSP we have a buffer available for input */ IO_OrValue(pIOMgr->hWmdContext, struct SHM, sm, hostFreeMask, (1 << pChnl->uId)); *pwMbVal = MBX_PCPY_CLASS; } else if (iMode == IO_OUTPUT) { - /* This assertion fails if CHNL_AddIOReq() was called on a - * stream which was cancelled, or attached to a dead board: */ + /* + * This assertion fails if CHNL_AddIOReq() was called on a + * stream which was cancelled, or attached to a dead board. + */ DBC_Assert((pChnl->dwState & ~CHNL_STATEEOS) == CHNL_STATEREADY); - /* Record the fact that we have a buffer available for - * output: */ + /* + * Record the fact that we have a buffer available for + * output. + */ pChnlMgr->dwOutputMask |= (1 << pChnl->uId); } else { DBC_Assert(iMode); /* Shouldn't get here. */ @@ -1150,7 +1180,7 @@ static void InputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, DBG_Trace(DBG_LEVEL3, "> InputChnl\n"); - /* Attempt to perform input.... */ + /* Attempt to perform input */ if (!IO_GetValue(pIOMgr->hWmdContext, struct SHM, sm, inputFull)) goto func_end; @@ -1168,17 +1198,19 @@ static void InputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, if ((pChnl->dwState & ~CHNL_STATEEOS) == CHNL_STATEREADY) { if (!pChnl->pIORequests) goto func_end; - /* Get the I/O request, and attempt a transfer: */ + /* Get the I/O request, and attempt a transfer */ pChirp = (struct CHNL_IRP *)LST_GetHead(pChnl-> pIORequests); if (pChirp) { pChnl->cIOReqs--; if (pChnl->cIOReqs < 0) goto func_end; - /* Ensure we don't overflow the client's - * buffer: */ + /* + * Ensure we don't overflow the client's + * buffer. + */ uBytes = min(uBytes, pChirp->cBytes); - /* Transfer buffer from DSP side: */ + /* Transfer buffer from DSP side */ uBytes = ReadData(pIOMgr->hWmdContext, pChirp->pHostSysBuf, pIOMgr->pInput, uBytes); @@ -1190,24 +1222,30 @@ static void InputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, "\n", *((RMS_WORD *)(pChirp-> pHostSysBuf))); if (uBytes == 0) { - /* This assertion fails if the DSP + /* + * This assertion fails if the DSP * sends EOS more than once on this - * channel: */ + * channel. + */ if (pChnl->dwState & CHNL_STATEEOS) goto func_end; - /* Zero bytes indicates EOS. Update - * IOC status for this chirp, and also - * the channel state: */ + /* + * Zero bytes indicates EOS. Update + * IOC status for this chirp, and also + * the channel state. + */ pChirp->status |= CHNL_IOCSTATEOS; pChnl->dwState |= CHNL_STATEEOS; - /* Notify that end of stream has - * occurred */ + /* + * Notify that end of stream has + * occurred. + */ NTFY_Notify(pChnl->hNtfy, DSP_STREAMDONE); DBG_Trace(DBG_LEVEL7, "Input Chnl NTFY " "chnl = 0x%x\n", pChnl); } - /* Tell DSP if no more I/O buffers available: */ + /* Tell DSP if no more I/O buffers available */ if (!pChnl->pIORequests) goto func_end; if (LST_IsEmpty(pChnl->pIORequests)) { @@ -1218,27 +1256,29 @@ static void InputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, fClearChnl = true; fNotifyClient = true; } else { - /* Input full for this channel, but we have no + /* + * Input full for this channel, but we have no * buffers available. The channel must be * "idling". Clear out the physical input - * channel. */ + * channel. + */ fClearChnl = true; } } else { - /* Input channel cancelled: clear input channel. */ + /* Input channel cancelled: clear input channel */ fClearChnl = true; } } else { - /* DPC fired after host closed channel: clear input channel. */ + /* DPC fired after host closed channel: clear input channel */ fClearChnl = true; } if (fClearChnl) { - /* Indicate to the DSP we have read the input: */ + /* Indicate to the DSP we have read the input */ IO_SetValue(pIOMgr->hWmdContext, struct SHM, sm, inputFull, 0); CHNLSM_InterruptDSP2(pIOMgr->hWmdContext, MBX_PCPY_CLASS); } if (fNotifyClient) { - /* Notify client with IO completion record: */ + /* Notify client with IO completion record */ NotifyChnlComplete(pChnl, pChirp); } func_end: @@ -1262,7 +1302,7 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) u32 addr; pCtrl = pIOMgr->pMsgInputCtrl; - /* Get the number of input messages to be read. */ + /* Get the number of input messages to be read */ fInputEmpty = IO_GetValue(pIOMgr->hWmdContext, struct MSG, pCtrl, bufEmpty); uMsgs = IO_GetValue(pIOMgr->hWmdContext, struct MSG, pCtrl, size); @@ -1289,9 +1329,11 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) DBG_Trace(DBG_LEVEL7, "InputMsg RECVD: dwCmd=0x%x dwArg1=0x%x " "dwArg2=0x%x dwId=0x%x \n", msg.msg.dwCmd, msg.msg.dwArg1, msg.msg.dwArg2, msg.dwId); - /* Interrupt may occur before shared memory and message - * input locations have been set up. If all nodes were - * cleaned up, hMsgMgr->uMaxMsgs should be 0. */ + /* + * Interrupt may occur before shared memory and message + * input locations have been set up. If all nodes were + * cleaned up, hMsgMgr->uMaxMsgs should be 0. + */ if (hMsgQueue && uMsgs > hMsgMgr->uMaxMsgs) goto func_end; @@ -1299,15 +1341,18 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) if (msg.dwId == hMsgQueue->dwId) { /* Found it */ if (msg.msg.dwCmd == RMS_EXITACK) { - /* The exit message does not get - * queued */ - /* Call the node exit notification */ - /* Node handle */ /* status */ + /* + * Call the node exit notification. + * The exit message does not get + * queued. + */ (*hMsgMgr->onExit)((HANDLE)hMsgQueue-> hArg, msg.msg.dwArg1); } else { - /* Not an exit acknowledgement, queue - * the message */ + /* + * Not an exit acknowledgement, queue + * the message. + */ if (!hMsgQueue->msgFreeList) goto func_end; pMsg = (struct MSG_FRAME *)LST_GetHead @@ -1322,8 +1367,10 @@ static void InputMsg(struct IO_MGR *pIOMgr, struct MSG_MGR *hMsgMgr) SYNC_SetEvent(hMsgQueue-> hSyncEvent); } else { - /* No free frame to copy the - * message into */ + /* + * No free frame to copy the + * message into. + */ DBG_Trace(DBG_LEVEL7, "NO FREE " "MSG FRAMES, DISCARDING" " MESSAGE\n"); @@ -1365,18 +1412,20 @@ static void NotifyChnlComplete(struct CHNL_OBJECT *pChnl, !pChnl->pIOCompletions || !pChirp) goto func_end; - /* Note: we signal the channel event only if the queue of IO - * completions is empty. If it is not empty, the event is sure to be - * signalled by the only IO completion list consumer: - * WMD_CHNL_GetIOC(). */ + /* + * Note: we signal the channel event only if the queue of IO + * completions is empty. If it is not empty, the event is sure to be + * signalled by the only IO completion list consumer: + * WMD_CHNL_GetIOC(). + */ fSignalEvent = LST_IsEmpty(pChnl->pIOCompletions); - /* Enqueue the IO completion info for the client: */ + /* Enqueue the IO completion info for the client */ LST_PutTail(pChnl->pIOCompletions, (struct LST_ELEM *) pChirp); pChnl->cIOCs++; if (pChnl->cIOCs > pChnl->cChirps) goto func_end; - /* Signal the channel event (if not already set) that IO is complete: */ + /* Signal the channel event (if not already set) that IO is complete */ if (fSignalEvent) SYNC_SetEvent(pChnl->hSyncEvent); @@ -1403,14 +1452,14 @@ static void OutputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, pChnlMgr = pIOMgr->hChnlMgr; sm = pIOMgr->pSharedMem; DBG_Trace(DBG_LEVEL3, "> OutputChnl\n"); - /* Attempt to perform output: */ + /* Attempt to perform output */ if (IO_GetValue(pIOMgr->hWmdContext, struct SHM, sm, outputFull)) goto func_end; if (pChnl && !((pChnl->dwState & ~CHNL_STATEEOS) == CHNL_STATEREADY)) goto func_end; - /* Look to see if both a PC and DSP output channel are ready: */ + /* Look to see if both a PC and DSP output channel are ready */ dwDspFMask = IO_GetValue(pIOMgr->hWmdContext, struct SHM, sm, dspFreeMask); chnlId = FindReadyOutput(pChnlMgr, pChnl, (pChnlMgr->dwOutputMask & @@ -1420,10 +1469,10 @@ static void OutputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, pChnl = pChnlMgr->apChannel[chnlId]; if (!pChnl || !pChnl->pIORequests) { - /* Shouldn't get here: */ + /* Shouldn't get here */ goto func_end; } - /* Get the I/O request, and attempt a transfer: */ + /* Get the I/O request, and attempt a transfer */ pChirp = (struct CHNL_IRP *)LST_GetHead(pChnl->pIORequests); if (!pChirp) goto func_end; @@ -1432,11 +1481,11 @@ static void OutputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, if (pChnl->cIOReqs < 0 || !pChnl->pIORequests) goto func_end; - /* Record fact that no more I/O buffers available: */ + /* Record fact that no more I/O buffers available */ if (LST_IsEmpty(pChnl->pIORequests)) pChnlMgr->dwOutputMask &= ~(1 << chnlId); - /* Transfer buffer to DSP side: */ + /* Transfer buffer to DSP side */ pChirp->cBytes = WriteData(pIOMgr->hWmdContext, pIOMgr->pOutput, pChirp->pHostSysBuf, min(pIOMgr->uSMBufSize, pChirp-> cBytes)); @@ -1456,7 +1505,7 @@ static void OutputChnl(struct IO_MGR *pIOMgr, struct CHNL_OBJECT *pChnl, uWordSize); #endif IO_SetValue(pIOMgr->hWmdContext, struct SHM, sm, outputFull, 1); - /* Indicate to the DSP we have written the output: */ + /* Indicate to the DSP we have written the output */ CHNLSM_InterruptDSP2(pIOMgr->hWmdContext, MBX_PCPY_CLASS); /* Notify client with IO completion record (keep EOS) */ pChirp->status &= CHNL_IOCSTATEOS; @@ -1577,8 +1626,10 @@ static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr, u32 ulShmSegId0 = 0; u32 dwOffset, dwGPPBaseVA, ulDSPSize; - /* Read address and size info for first SM region.*/ - /* Get start of 1st SM Heap region */ + /* + * Read address and size info for first SM region. + * Get start of 1st SM Heap region. + */ status = COD_GetSymValue(hCodMan, SHM0_SHARED_BASE_SYM, &ulShm0_Base); if (ulShm0_Base == 0) { status = DSP_EFAIL; @@ -1594,7 +1645,7 @@ static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr, goto func_end; } } - /* start of Gpp reserved region */ + /* Start of Gpp reserved region */ if (DSP_SUCCEEDED(status)) { /* Get start and length of message part of shared memory */ status = COD_GetSymValue(hCodMan, SHM0_SHARED_RESERVED_BASE_SYM, @@ -1623,27 +1674,29 @@ static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr, } /* Register new SM region(s) */ if (DSP_SUCCEEDED(status) && (ulShm0_End - ulShm0_Base) > 0) { - /* calc size (bytes) of SM the GPP can alloc from */ + /* Calc size (bytes) of SM the GPP can alloc from */ ulRsrvdSize = (ulShm0_End - ulShm0_RsrvdStart + 1) * hIOMgr-> uWordSize; if (ulRsrvdSize <= 0) { status = DSP_EFAIL; goto func_end; } - /* calc size of SM DSP can alloc from */ + /* Calc size of SM DSP can alloc from */ ulDSPSize = (ulShm0_RsrvdStart - ulShm0_Base) * hIOMgr-> uWordSize; if (ulDSPSize <= 0) { status = DSP_EFAIL; goto func_end; } - /* First TLB entry reserved for Bridge SM use.*/ + /* First TLB entry reserved for Bridge SM use.*/ ulGppPhys = hIOMgr->extProcInfo.tyTlb[0].ulGppPhys; - /* get size in bytes */ + /* Get size in bytes */ ulDspVirt = hIOMgr->extProcInfo.tyTlb[0].ulDspVirt * hIOMgr-> uWordSize; - /* Calc byte offset used to convert GPP phys <-> DSP byte - * address.*/ + /* + * Calc byte offset used to convert GPP phys <-> DSP byte + * address. + */ if (dwGPPBasePA > ulDspVirt) dwOffset = dwGPPBasePA - ulDspVirt; else @@ -1653,15 +1706,19 @@ static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr, status = DSP_EFAIL; goto func_end; } - /* calc Gpp phys base of SM region */ - /* Linux - this is actually uncached kernel virtual address*/ + /* + * Calc Gpp phys base of SM region. + * This is actually uncached kernel virtual address. + */ dwGPPBaseVA = ulGppPhys + ulShm0_RsrvdStart * hIOMgr->uWordSize - ulDspVirt; - /* calc Gpp phys base of SM region */ - /* Linux - this is the physical address*/ + /* + * Calc Gpp phys base of SM region. + * This is the physical address. + */ dwGPPBasePA = dwGPPBasePA + ulShm0_RsrvdStart * hIOMgr-> uWordSize - ulDspVirt; - /* Register SM Segment 0.*/ + /* Register SM Segment 0.*/ status = CMM_RegisterGPPSMSeg(hIOMgr->hCmmMgr, dwGPPBasePA, ulRsrvdSize, dwOffset, (dwGPPBasePA > ulDspVirt) ? CMM_ADDTODSPPA : CMM_SUBFROMDSPPA, @@ -1671,7 +1728,7 @@ static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr, DBG_Trace(DBG_LEVEL7, "ERROR - Failed to register SM " "Seg 0 \n"); } - /* first SM region is segId = 1 */ + /* First SM region is segId = 1 */ if (ulShmSegId0 != 1) status = DSP_EFAIL; } @@ -1729,8 +1786,10 @@ DSP_STATUS IO_SHMsetting(IN struct IO_MGR *hIOMgr, IN enum SHM_DESCTYPE desc, return DSP_EFAIL; break; case SHM_OPPINFO: - /* Update the shared memory with the voltage, frequency, - min and max frequency values for an OPP */ + /* + * Update the shared memory with the voltage, frequency, + * min and max frequency values for an OPP. + */ for (i = 0; i <= dsp_max_opps; i++) { hIOMgr->pSharedMem->oppTableStruct.oppPoint[i].voltage = vdd1_dsp_freq[i][0]; @@ -1818,8 +1877,10 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) memcpy(hIOMgr->pMsg, (char *)hIOMgr->ulGPPReadPointer, ulNewMessageLength); hIOMgr->pMsg[ulNewMessageLength] = '\0'; - /* Advance the GPP trace pointer to DSP current - * pointer */ + /* + * Advance the GPP trace pointer to DSP current + * pointer. + */ hIOMgr->ulGPPReadPointer += ulNewMessageLength; /* Print the trace messages */ GT_0trace(dsp_trace_mask, GT_1CLASS, hIOMgr->pMsg); @@ -1838,8 +1899,10 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr) hIOMgr->pMsg[hIOMgr->ulTraceBufferEnd - hIOMgr->ulGPPReadPointer + ulNewMessageLength] = '\0'; - /* Advance the GPP trace pointer to DSP current - * pointer */ + /* + * Advance the GPP trace pointer to DSP current + * pointer. + */ hIOMgr->ulGPPReadPointer = hIOMgr->ulTraceBufferBegin + ulNewMessageLength; /* Print the trace messages */ @@ -1878,7 +1941,7 @@ static DSP_STATUS PackTraceBuffer(char *lpBuf, u32 nBytes, u32 ulNumWords) u32 nCnt; char thisChar; - /* tmp workspace, 1 KB longer than input buf */ + /* Tmp workspace, 1 KB longer than input buf */ lpTmpBuf = MEM_Calloc((nBytes + ulNumWords), MEM_PAGED); if (lpTmpBuf == NULL) { DBG_Trace(DBG_LEVEL7, "PackTrace buffer:OutofMemory \n"); @@ -1894,8 +1957,10 @@ static DSP_STATUS PackTraceBuffer(char *lpBuf, u32 nBytes, u32 ulNumWords) case '\0': /* Skip null bytes */ break; case '\n': /* Convert \n to \r\n */ - /* NOTE: do not reverse order; Some OS */ - /* editors control doesn't understand "\n\r" */ + /* + * NOTE: do not reverse order; Some OS + * editors control doesn't understand "\n\r" + */ *lpTmpBuf++ = '\r'; *lpTmpBuf++ = '\n'; break; @@ -1907,7 +1972,7 @@ static DSP_STATUS PackTraceBuffer(char *lpBuf, u32 nBytes, u32 ulNumWords) *lpTmpBuf = '\0'; /* Make sure tmp buf is null terminated */ /* Cut output down to input buf size */ strncpy(lpBufStart, lpTmpStart, nBytes); - /*Make sure output is null terminated */ + /* Make sure output is null terminated */ lpBufStart[nBytes - 1] = '\0'; MEM_Free(lpTmpStart); } @@ -1955,7 +2020,7 @@ DSP_STATUS PrintDspTraceBuffer(struct WMD_DEV_CONTEXT *hWmdContext) "PrintDspTraceBuffer: Failed on DEV_GetCodMgr.\n"); if (DSP_SUCCEEDED(status)) { - /* Look for SYS_PUTCBEG/SYS_PUTCEND: */ + /* Look for SYS_PUTCBEG/SYS_PUTCEND */ status = COD_GetSymValue(hCodMgr, COD_TRACEBEG, &ulTraceBegin); GT_1trace(dsp_trace_mask, GT_2CLASS, "PrintDspTraceBuffer: ulTraceBegin Value 0x%x\n", -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 17/20] DSPBRIDGE: Remove DPC, create, destroy and schedule wrappers 2009-11-30 21:54 ` [PATCH v2 16/20] DSPBRIDGE: trivial fix for multiline comments on io_sm Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 18/20] DSPBRIDGE: Remove main DPC wrapper for IO and MMUfault Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna Remove DPC wrappers and replace with direct Linux calls. These changes apply to IO DPC and MMUfault DPC Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- arch/arm/plat-omap/include/dspbridge/dpc.h | 90 +++-------------- drivers/dsp/bridge/services/dpc.c | 144 +--------------------------- drivers/dsp/bridge/wmd/io_sm.c | 72 +++++++++++++- drivers/dsp/bridge/wmd/mmu_fault.c | 24 ++++- drivers/dsp/bridge/wmd/ue_deh.c | 31 ++++++- 5 files changed, 131 insertions(+), 230 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/dpc.h b/arch/arm/plat-omap/include/dspbridge/dpc.h index 870a1b2..0c60342 100644 --- a/arch/arm/plat-omap/include/dspbridge/dpc.h +++ b/arch/arm/plat-omap/include/dspbridge/dpc.h @@ -19,8 +19,6 @@ #ifndef DPC_ #define DPC_ - struct DPC_OBJECT; - /* * ======== DPC_PROC ======== * Purpose: @@ -40,64 +38,22 @@ */ typedef void(*DPC_PROC) (void *pRefData); -/* - * ======== DPC_Cancel ======== - * Purpose: - * Cancel a DPC previously scheduled by DPC_Schedule. - * Parameters: - * hDPC: A DPC object handle created in DPC_Create(). - * Returns: - * DSP_SOK: Scheduled DPC, if any, is cancelled. - * DSP_SFALSE: No DPC is currently scheduled for execution. - * DSP_EHANDLE: Invalid hDPC. - * Requires: - * Ensures: - * If the DPC has already executed, is executing, or was not yet - * scheduled, this function will have no effect. - */ - extern DSP_STATUS DPC_Cancel(IN struct DPC_OBJECT *hDPC); +/* The DPC object, passed to our priority event callback routine: */ +struct DPC_OBJECT { + u32 dwSignature; /* Used for object validation. */ + void *pRefData; /* Argument for client's DPC. */ + DPC_PROC pfnDPC; /* Client's DPC. */ + u32 numRequested; /* Number of requested DPC's. */ + u32 numScheduled; /* Number of executed DPC's. */ + struct tasklet_struct dpc_tasklet; -/* - * ======== DPC_Create ======== - * Purpose: - * Create a DPC object, allowing a client's own DPC procedure to be - * scheduled for a call with client reference data. - * Parameters: - * phDPC: Pointer to location to store DPC object. - * pfnDPC: Client's DPC procedure. - * pRefData: Pointer to user-defined reference data. - * Returns: - * DSP_SOK: DPC object created. - * DSP_EPOINTER: phDPC == NULL or pfnDPC == NULL. - * DSP_EMEMORY: Insufficient memory. - * Requires: - * Must not be called at interrupt time. - * Ensures: - * DSP_SOK: DPC object is created; - * else: *phDPC is set to NULL. - */ - extern DSP_STATUS DPC_Create(OUT struct DPC_OBJECT **phDPC, - IN DPC_PROC pfnDPC, - IN void *pRefData); +#ifdef DEBUG + u32 cEntryCount; /* Number of times DPC reentered. */ + u32 numRequestedMax; /* Keep track of max pending DPC's. */ +#endif -/* - * ======== DPC_Destroy ======== - * Purpose: - * Cancel the last scheduled DPC, and deallocate a DPC object previously - * allocated with DPC_Create().Frees the Object only if the thread and - * the events are terminated successfuly. - * Parameters: - * hDPC: A DPC object handle created in DPC_Create(). - * Returns: - * DSP_SOK: Success. - * DSP_EHANDLE: Invalid hDPC. - * Requires: - * All DPC's scheduled for the DPC object must have completed their - * processing. - * Ensures: - * (SUCCESS && hDPC is NULL) or DSP_EFAILED status - */ - extern DSP_STATUS DPC_Destroy(IN struct DPC_OBJECT *hDPC); + spinlock_t dpc_lock; +}; /* * ======== DPC_Exit ======== @@ -125,21 +81,7 @@ */ extern bool DPC_Init(void); -/* - * ======== DPC_Schedule ======== - * Purpose: - * Schedule a deferred procedure call to be executed at a later time. - * Latency and order of DPC execution is platform specific. - * Parameters: - * hDPC: A DPC object handle created in DPC_Create(). - * Returns: - * DSP_SOK: An event is scheduled for deferred processing. - * DSP_EHANDLE: Invalid hDPC. - * Requires: - * See requirements for DPC_PROC. - * Ensures: - * DSP_SOK: The DPC will not be called before this function returns. - */ - extern DSP_STATUS DPC_Schedule(IN struct DPC_OBJECT *hDPC); +/* ----------------------------------- Function Prototypes */ + void DPC_DeferredProcedure(IN unsigned long pDeferredContext); #endif /* DPC_ */ diff --git a/drivers/dsp/bridge/services/dpc.c b/drivers/dsp/bridge/services/dpc.c index a6d453c..10bd792 100644 --- a/drivers/dsp/bridge/services/dpc.c +++ b/drivers/dsp/bridge/services/dpc.c @@ -37,111 +37,11 @@ /* ----------------------------------- Defines, Data Structures, Typedefs */ #define SIGNATURE 0x5f435044 /* "DPC_" (in reverse). */ -/* The DPC object, passed to our priority event callback routine: */ -struct DPC_OBJECT { - u32 dwSignature; /* Used for object validation. */ - void *pRefData; /* Argument for client's DPC. */ - DPC_PROC pfnDPC; /* Client's DPC. */ - u32 numRequested; /* Number of requested DPC's. */ - u32 numScheduled; /* Number of executed DPC's. */ - struct tasklet_struct dpc_tasklet; - -#ifdef DEBUG - u32 cEntryCount; /* Number of times DPC reentered. */ - u32 numRequestedMax; /* Keep track of max pending DPC's. */ -#endif - - spinlock_t dpc_lock; -}; - /* ----------------------------------- Globals */ #if GT_TRACE static struct GT_Mask DPC_DebugMask = { NULL, NULL }; /* DPC Debug Mask */ #endif -/* ----------------------------------- Function Prototypes */ -static void DPC_DeferredProcedure(IN unsigned long pDeferredContext); - -/* - * ======== DPC_Create ======== - * Purpose: - * Create a DPC object, allowing a client's own DPC procedure to be - * scheduled for a call with client reference data. - */ -DSP_STATUS DPC_Create(OUT struct DPC_OBJECT **phDPC, DPC_PROC pfnDPC, - void *pRefData) -{ - DSP_STATUS status = DSP_SOK; - struct DPC_OBJECT *pDPCObject = NULL; - - if ((phDPC != NULL) && (pfnDPC != NULL)) { - /* - * Allocate a DPC object to store information allowing our DPC - * callback to dispatch to the client's DPC. - */ - MEM_AllocObject(pDPCObject, struct DPC_OBJECT, SIGNATURE); - if (pDPCObject != NULL) { - tasklet_init(&pDPCObject->dpc_tasklet, - DPC_DeferredProcedure, - (u32) pDPCObject); - /* Fill out our DPC Object: */ - pDPCObject->pRefData = pRefData; - pDPCObject->pfnDPC = pfnDPC; - pDPCObject->numRequested = 0; - pDPCObject->numScheduled = 0; -#ifdef DEBUG - pDPCObject->numRequestedMax = 0; - pDPCObject->cEntryCount = 0; -#endif - spin_lock_init(&pDPCObject->dpc_lock); - *phDPC = pDPCObject; - } else { - GT_0trace(DPC_DebugMask, GT_6CLASS, - "DPC_Create: DSP_EMEMORY\n"); - status = DSP_EMEMORY; - } - } else { - GT_0trace(DPC_DebugMask, GT_6CLASS, - "DPC_Create: DSP_EPOINTER\n"); - status = DSP_EPOINTER; - } - DBC_Ensure((DSP_FAILED(status) && (!phDPC || (phDPC && *phDPC == NULL))) - || DSP_SUCCEEDED(status)); - return status; -} - -/* - * ======== DPC_Destroy ======== - * Purpose: - * Cancel the last scheduled DPC, and deallocate a DPC object previously - * allocated with DPC_Create(). Frees the Object only if the thread - * and the event terminated successfuly. - */ -DSP_STATUS DPC_Destroy(struct DPC_OBJECT *hDPC) -{ - DSP_STATUS status = DSP_SOK; - struct DPC_OBJECT *pDPCObject = (struct DPC_OBJECT *)hDPC; - - if (MEM_IsValidHandle(hDPC, SIGNATURE)) { - - /* Free our DPC object: */ - if (DSP_SUCCEEDED(status)) { - tasklet_kill(&pDPCObject->dpc_tasklet); - MEM_FreeObject(pDPCObject); - pDPCObject = NULL; - GT_0trace(DPC_DebugMask, GT_2CLASS, - "DPC_Destroy: SUCCESS\n"); - } - } else { - GT_0trace(DPC_DebugMask, GT_6CLASS, - "DPC_Destroy: DSP_EHANDLE\n"); - status = DSP_EHANDLE; - } - DBC_Ensure((DSP_SUCCEEDED(status) && pDPCObject == NULL) - || DSP_FAILED(status)); - return status; -} - /* * ======== DPC_Exit ======== * Purpose: @@ -167,54 +67,12 @@ bool DPC_Init(void) } /* - * ======== DPC_Schedule ======== - * Purpose: - * Schedule a deferred procedure call to be executed at a later time. - * Latency and order of DPC execution is platform specific. - */ -DSP_STATUS DPC_Schedule(struct DPC_OBJECT *hDPC) -{ - DSP_STATUS status = DSP_SOK; - struct DPC_OBJECT *pDPCObject = (struct DPC_OBJECT *)hDPC; - unsigned long flags; - - GT_1trace(DPC_DebugMask, GT_ENTER, "DPC_Schedule hDPC %x\n", hDPC); - if (MEM_IsValidHandle(hDPC, SIGNATURE)) { - /* Increment count of DPC's pending. Needs to be protected - * from ISRs since this function is called from process - * context also. */ - spin_lock_irqsave(&hDPC->dpc_lock, flags); - pDPCObject->numRequested++; - spin_unlock_irqrestore(&hDPC->dpc_lock, flags); - tasklet_schedule(&(hDPC->dpc_tasklet)); -#ifdef DEBUG - if (pDPCObject->numRequested > pDPCObject->numScheduled + - pDPCObject->numRequestedMax) { - pDPCObject->numRequestedMax = pDPCObject->numRequested - - pDPCObject->numScheduled; - } -#endif - /* If an interrupt occurs between incrementing numRequested and the - * assertion below, then DPC will get executed while returning from - * ISR, which will complete all requests and make numRequested equal - * to numScheduled, firing this assertion. This happens only when - * DPC is being scheduled in process context */ - } else { - GT_0trace(DPC_DebugMask, GT_6CLASS, - "DPC_Schedule: DSP_EHANDLE\n"); - status = DSP_EHANDLE; - } - GT_1trace(DPC_DebugMask, GT_ENTER, "DPC_Schedule status %x\n", status); - return status; -} - -/* * ======== DeferredProcedure ======== * Purpose: * Main DPC routine. This is called by host OS DPC callback * mechanism with interrupts enabled. */ -static void DPC_DeferredProcedure(IN unsigned long pDeferredContext) +void DPC_DeferredProcedure(IN unsigned long pDeferredContext) { struct DPC_OBJECT *pDPCObject = (struct DPC_OBJECT *)pDeferredContext; /* read numRequested in local variable */ diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index 8fcf150..d465763 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -251,7 +251,26 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, if (devType == DSP_UNIT) { /* Create a DPC object */ - status = DPC_Create(&pIOMgr->hDPC, IO_DPC, (void *)pIOMgr); + MEM_AllocObject(pIOMgr->hDPC, struct DPC_OBJECT, + IO_MGRSIGNATURE); + if (pIOMgr->hDPC) { + tasklet_init(&pIOMgr->hDPC->dpc_tasklet, + DPC_DeferredProcedure, (u32)pIOMgr->hDPC); + /* Fill out our DPC Object */ + pIOMgr->hDPC->pRefData = (void *)pIOMgr; + pIOMgr->hDPC->pfnDPC = IO_DPC; + pIOMgr->hDPC->numRequested = 0; + pIOMgr->hDPC->numScheduled = 0; +#ifdef DEBUG + pIOMgr->hDPC->numRequestedMax = 0; + pIOMgr->hDPC->cEntryCount = 0; +#endif + spin_lock_init(&pIOMgr->hDPC->dpc_lock); + } else { + DBG_Trace(GT_6CLASS, "IO DPC Create: DSP_EMEMORY\n"); + status = DSP_EMEMORY; + } + if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -312,8 +331,13 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) destroy_workqueue(bridge_workqueue); /* Linux function to uninstall ISR */ free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr); - if (hIOMgr->hDPC) - (void)DPC_Destroy(hIOMgr->hDPC); + + /* Free DPC object */ + tasklet_kill(&hIOMgr->hDPC->dpc_tasklet); + MEM_FreeObject(hIOMgr->hDPC); + hIOMgr->hDPC = NULL; + DBG_Trace(GT_2CLASS, "DPC_Destroy: SUCCESS\n"); + #ifndef DSP_TRACEBUF_DISABLED if (hIOMgr->pMsg) MEM_Free(hIOMgr->pMsg); @@ -1033,6 +1057,8 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) { struct IO_MGR *hIOMgr = (struct IO_MGR *)pRefData; bool fSchedDPC; + unsigned long flags; + if (irq != INT_MAIL_MPU_IRQ || !MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE)) return IRQ_NONE; @@ -1054,8 +1080,25 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) DBG_Trace(DBG_LEVEL6, "*** DSP RESET ***\n"); hIOMgr->wIntrVal = 0; } else if (fSchedDPC) { - /* PROC-COPY defer i/o */ - DPC_Schedule(hIOMgr->hDPC); + /* + * PROC-COPY defer i/o. + * Increment count of DPC's pending. + */ + spin_lock_irqsave(&hIOMgr->hDPC->dpc_lock, flags); + hIOMgr->hDPC->numRequested++; + spin_unlock_irqrestore(&hIOMgr->hDPC->dpc_lock, flags); + + /* Schedule DPC */ + tasklet_schedule(&hIOMgr->hDPC->dpc_tasklet); +#ifdef DEBUG + if (hIOMgr->hDPC->numRequested > + hIOMgr->hDPC->numScheduled + + hIOMgr->hDPC->numRequestedMax) { + hIOMgr->hDPC->numRequestedMax = + hIOMgr->hDPC->numRequested - + hIOMgr->hDPC->numScheduled; + } +#endif } } else /* Ensure that, if WMD didn't claim it, the IRQ is shared. */ @@ -1116,10 +1159,27 @@ func_end: */ void IO_Schedule(struct IO_MGR *pIOMgr) { + unsigned long flags; + if (!MEM_IsValidHandle(pIOMgr, IO_MGRSIGNATURE)) return; tiomap3430_bump_dsp_opp_level(); - DPC_Schedule(pIOMgr->hDPC); + + /* Increment count of DPC's pending. */ + spin_lock_irqsave(&pIOMgr->hDPC->dpc_lock, flags); + pIOMgr->hDPC->numRequested++; + spin_unlock_irqrestore(&pIOMgr->hDPC->dpc_lock, flags); + + /* Schedule DPC */ + tasklet_schedule(&pIOMgr->hDPC->dpc_tasklet); +#ifdef DEBUG + if (pIOMgr->hDPC->numRequested > pIOMgr->hDPC->numScheduled + + pIOMgr->hDPC->numRequestedMax) { + pIOMgr->hDPC->numRequestedMax = pIOMgr->hDPC->numRequested - + pIOMgr->hDPC->numScheduled; + } +#endif + } /* diff --git a/drivers/dsp/bridge/wmd/mmu_fault.c b/drivers/dsp/bridge/wmd/mmu_fault.c index bb98e56..0e03cd1 100644 --- a/drivers/dsp/bridge/wmd/mmu_fault.c +++ b/drivers/dsp/bridge/wmd/mmu_fault.c @@ -76,7 +76,7 @@ irqreturn_t MMU_FaultIsr(int irq, IN void *pRefData) struct DEH_MGR *pDehMgr = (struct DEH_MGR *)pRefData; struct WMD_DEV_CONTEXT *pDevContext; DSP_STATUS status = DSP_SOK; - + unsigned long flags; DBG_Trace(DBG_LEVEL1, "Entering DEH_DspMmuIsr: 0x%x\n", pRefData); DBC_Require(irq == INT_DSP_MMU_IRQ); @@ -94,14 +94,30 @@ irqreturn_t MMU_FaultIsr(int irq, IN void *pRefData) "0x%x\n", dmmuEventMask); printk(KERN_INFO "***** DSPMMU FAULT ***** faultAddr " "0x%x\n", faultAddr); - /* Disable the MMU events, else once we clear it will - * start to raise INTs again */ /* * Schedule a DPC directly. In the future, it may be * necessary to check if DSP MMU fault is intended for * Bridge. */ - DPC_Schedule(pDehMgr->hMmuFaultDpc); + /* Increment count of DPC's pending. */ + spin_lock_irqsave(&pDehMgr->hMmuFaultDpc->dpc_lock, + flags); + pDehMgr->hMmuFaultDpc->numRequested++; + spin_unlock_irqrestore(&pDehMgr->hMmuFaultDpc->dpc_lock, + flags); + + /* Schedule DPC */ + tasklet_schedule(&pDehMgr->hMmuFaultDpc->dpc_tasklet); +#ifdef DEBUG + if (pDehMgr->hMmuFaultDpc->numRequested > + pDehMgr->hMmuFaultDpc->numScheduled + + pDehMgr->hMmuFaultDpc->numRequestedMax) { + pDehMgr->hMmuFaultDpc->numRequestedMax = + pDehMgr->hMmuFaultDpc->numRequested - + pDehMgr->hMmuFaultDpc->numScheduled; + } +#endif + /* Reset errInfo structure before use. */ pDehMgr->errInfo.dwErrMask = DSP_MMUFAULT; pDehMgr->errInfo.dwVal1 = faultAddr >> 16; diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c index 6d6c76b..12f73e7 100644 --- a/drivers/dsp/bridge/wmd/ue_deh.c +++ b/drivers/dsp/bridge/wmd/ue_deh.c @@ -91,8 +91,27 @@ DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr, status = NTFY_Create(&pDehMgr->hNtfy); /* Create a DPC object. */ - status = DPC_Create(&pDehMgr->hMmuFaultDpc, MMU_FaultDpc, - (void *)pDehMgr); + MEM_AllocObject(pDehMgr->hMmuFaultDpc, struct DPC_OBJECT, + SIGNATURE); + if (pDehMgr->hMmuFaultDpc) { + tasklet_init(&pDehMgr->hMmuFaultDpc->dpc_tasklet, + DPC_DeferredProcedure, + (u32)pDehMgr->hMmuFaultDpc); + /* Fill out DPC Object */ + pDehMgr->hMmuFaultDpc->pRefData = (void *)pDehMgr; + pDehMgr->hMmuFaultDpc->pfnDPC = MMU_FaultDpc; + pDehMgr->hMmuFaultDpc->numRequested = 0; + pDehMgr->hMmuFaultDpc->numScheduled = 0; +#ifdef DEBUG + pDehMgr->hMmuFaultDpc->numRequestedMax = 0; + pDehMgr->hMmuFaultDpc->cEntryCount = 0; +#endif + spin_lock_init(&pDehMgr->hMmuFaultDpc->dpc_lock); + } else { + DBG_Trace(GT_6CLASS, "DEH DPC Create: DSP_EMEMORY\n"); + status = DSP_EMEMORY; + } + if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -144,7 +163,13 @@ DSP_STATUS WMD_DEH_Destroy(struct DEH_MGR *hDehMgr) (void)NTFY_Delete(pDehMgr->hNtfy); /* Disable DSP MMU fault */ free_irq(INT_DSP_MMU_IRQ, pDehMgr); - (void)DPC_Destroy(pDehMgr->hMmuFaultDpc); + + /* Free DPC object */ + tasklet_kill(&pDehMgr->hMmuFaultDpc->dpc_tasklet); + MEM_FreeObject(pDehMgr->hMmuFaultDpc); + pDehMgr->hMmuFaultDpc = NULL; + DBG_Trace(GT_2CLASS, "DPC_Destroy: SUCCESS\n"); + /* Deallocate the DEH manager object */ MEM_FreeObject(pDehMgr); } -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 18/20] DSPBRIDGE: Remove main DPC wrapper for IO and MMUfault 2009-11-30 21:54 ` [PATCH v2 17/20] DSPBRIDGE: Remove DPC, create, destroy and schedule wrappers Omar Ramirez Luna @ 2009-11-30 21:54 ` Omar Ramirez Luna 2009-11-30 21:55 ` [PATCH v2 19/20] DSPBRIDGE: Remove DPC module from SERVICES layer Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:54 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna Remove DeferredProcedure which is used as a wrapper to call either IO or MMUfault DPCs. This also removes a custom typedef. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- arch/arm/plat-omap/include/dspbridge/dpc.h | 23 ------------ arch/arm/plat-omap/include/dspbridge/io_sm.h | 2 +- drivers/dsp/bridge/services/dpc.c | 36 ------------------ drivers/dsp/bridge/wmd/io_sm.c | 50 ++++++++++++++++--------- drivers/dsp/bridge/wmd/mmu_fault.c | 2 +- drivers/dsp/bridge/wmd/mmu_fault.h | 2 +- drivers/dsp/bridge/wmd/ue_deh.c | 5 +-- 7 files changed, 36 insertions(+), 84 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/dpc.h b/arch/arm/plat-omap/include/dspbridge/dpc.h index 0c60342..b22140f 100644 --- a/arch/arm/plat-omap/include/dspbridge/dpc.h +++ b/arch/arm/plat-omap/include/dspbridge/dpc.h @@ -19,30 +19,10 @@ #ifndef DPC_ #define DPC_ -/* - * ======== DPC_PROC ======== - * Purpose: - * Deferred processing routine. Typically scheduled from an ISR to - * complete I/O processing. - * Parameters: - * pRefData: Ptr to user data: passed in via ISR_ScheduleDPC. - * Returns: - * Requires: - * The DPC should not block, or otherwise acquire resources. - * Interrupts to the processor are enabled. - * DPC_PROC executes in a critical section. - * Ensures: - * This DPC will not be reenterred on the same thread. - * However, the DPC may take hardware interrupts during execution. - * Interrupts to the processor are enabled. - */ - typedef void(*DPC_PROC) (void *pRefData); - /* The DPC object, passed to our priority event callback routine: */ struct DPC_OBJECT { u32 dwSignature; /* Used for object validation. */ void *pRefData; /* Argument for client's DPC. */ - DPC_PROC pfnDPC; /* Client's DPC. */ u32 numRequested; /* Number of requested DPC's. */ u32 numScheduled; /* Number of executed DPC's. */ struct tasklet_struct dpc_tasklet; @@ -81,7 +61,4 @@ struct DPC_OBJECT { */ extern bool DPC_Init(void); -/* ----------------------------------- Function Prototypes */ - void DPC_DeferredProcedure(IN unsigned long pDeferredContext); - #endif /* DPC_ */ diff --git a/arch/arm/plat-omap/include/dspbridge/io_sm.h b/arch/arm/plat-omap/include/dspbridge/io_sm.h index 77f9e25..67e3834 100644 --- a/arch/arm/plat-omap/include/dspbridge/io_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/io_sm.h @@ -77,7 +77,7 @@ * Ensures: * Non-preemptible (but interruptible). */ - extern void IO_DPC(IN OUT void *pRefData); + extern void IO_DPC(IN OUT unsigned long pRefData); /* * ======== IO_ISR ======== diff --git a/drivers/dsp/bridge/services/dpc.c b/drivers/dsp/bridge/services/dpc.c index 10bd792..bbb2d47 100644 --- a/drivers/dsp/bridge/services/dpc.c +++ b/drivers/dsp/bridge/services/dpc.c @@ -66,39 +66,3 @@ bool DPC_Init(void) return true; } -/* - * ======== DeferredProcedure ======== - * Purpose: - * Main DPC routine. This is called by host OS DPC callback - * mechanism with interrupts enabled. - */ -void DPC_DeferredProcedure(IN unsigned long pDeferredContext) -{ - struct DPC_OBJECT *pDPCObject = (struct DPC_OBJECT *)pDeferredContext; - /* read numRequested in local variable */ - u32 requested; - u32 serviced; - - DBC_Require(pDPCObject != NULL); - requested = pDPCObject->numRequested; - serviced = pDPCObject->numScheduled; - - GT_1trace(DPC_DebugMask, GT_ENTER, "> DPC_DeferredProcedure " - "pDeferredContext=%x\n", pDeferredContext); - /* Rollover taken care of using != instead of < */ - if (serviced != requested) { - if (pDPCObject->pfnDPC != NULL) { - /* Process pending DPC's: */ - do { - /* Call client's DPC: */ - (*(pDPCObject->pfnDPC))(pDPCObject->pRefData); - serviced++; - } while (serviced != requested); - } - pDPCObject->numScheduled = requested; - } - GT_2trace(DPC_DebugMask, GT_ENTER, - "< DPC_DeferredProcedure requested %d" - " serviced %d\n", requested, serviced); -} - diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index d465763..177dbbc 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -255,10 +255,8 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, IO_MGRSIGNATURE); if (pIOMgr->hDPC) { tasklet_init(&pIOMgr->hDPC->dpc_tasklet, - DPC_DeferredProcedure, (u32)pIOMgr->hDPC); + IO_DPC, (u32)pIOMgr); /* Fill out our DPC Object */ - pIOMgr->hDPC->pRefData = (void *)pIOMgr; - pIOMgr->hDPC->pfnDPC = IO_DPC; pIOMgr->hDPC->numRequested = 0; pIOMgr->hDPC->numScheduled = 0; #ifdef DEBUG @@ -1010,12 +1008,14 @@ static void IO_DispatchPM(struct work_struct *work) * out the dispatch of I/O as a non-preemptible event.It can only be * pre-empted by an ISR. */ -void IO_DPC(IN OUT void *pRefData) +void IO_DPC(IN OUT unsigned long pRefData) { struct IO_MGR *pIOMgr = (struct IO_MGR *)pRefData; struct CHNL_MGR *pChnlMgr; struct MSG_MGR *pMsgMgr; struct DEH_MGR *hDehMgr; + u32 requested; + u32 serviced; if (!MEM_IsValidHandle(pIOMgr, IO_MGRSIGNATURE)) goto func_end; @@ -1025,24 +1025,38 @@ void IO_DPC(IN OUT void *pRefData) if (!MEM_IsValidHandle(pChnlMgr, CHNL_MGRSIGNATURE)) goto func_end; DBG_Trace(DBG_LEVEL7, "Entering IO_DPC(0x%x)\n", pRefData); - /* Check value of interrupt register to ensure it is a valid error */ - if ((pIOMgr->wIntrVal > DEH_BASE) && (pIOMgr->wIntrVal < DEH_LIMIT)) { - /* Notify DSP/BIOS exception */ - if (hDehMgr) - WMD_DEH_Notify(hDehMgr, DSP_SYSERROR, pIOMgr->wIntrVal); - } - IO_DispatchChnl(pIOMgr, NULL, IO_SERVICE); + + requested = pIOMgr->hDPC->numRequested; + serviced = pIOMgr->hDPC->numScheduled; + + if (serviced == requested) + goto func_end; + + /* Process pending DPC's */ + do { + /* Check value of interrupt reg to ensure it's a valid error */ + if ((pIOMgr->wIntrVal > DEH_BASE) && + (pIOMgr->wIntrVal < DEH_LIMIT)) { + /* Notify DSP/BIOS exception */ + if (hDehMgr) + WMD_DEH_Notify(hDehMgr, DSP_SYSERROR, + pIOMgr->wIntrVal); + } + IO_DispatchChnl(pIOMgr, NULL, IO_SERVICE); #ifdef CHNL_MESSAGES - if (MEM_IsValidHandle(pMsgMgr, MSGMGR_SIGNATURE)) - IO_DispatchMsg(pIOMgr, pMsgMgr); + if (MEM_IsValidHandle(pMsgMgr, MSGMGR_SIGNATURE)) + IO_DispatchMsg(pIOMgr, pMsgMgr); #endif #ifndef DSP_TRACEBUF_DISABLED - if (pIOMgr->wIntrVal & MBX_DBG_CLASS) { - /* Notify DSP Trace message */ - if (pIOMgr->wIntrVal & MBX_DBG_SYSPRINTF) - PrintDSPDebugTrace(pIOMgr); - } + if (pIOMgr->wIntrVal & MBX_DBG_CLASS) { + /* Notify DSP Trace message */ + if (pIOMgr->wIntrVal & MBX_DBG_SYSPRINTF) + PrintDSPDebugTrace(pIOMgr); + } #endif + serviced++; + } while (serviced != requested); + pIOMgr->hDPC->numScheduled = requested; func_end: return; } diff --git a/drivers/dsp/bridge/wmd/mmu_fault.c b/drivers/dsp/bridge/wmd/mmu_fault.c index 0e03cd1..b3f0719 100644 --- a/drivers/dsp/bridge/wmd/mmu_fault.c +++ b/drivers/dsp/bridge/wmd/mmu_fault.c @@ -54,7 +54,7 @@ static bool MMU_CheckIfFault(struct WMD_DEV_CONTEXT *pDevContext); * ======== MMU_FaultDpc ======== * Deferred procedure call to handle DSP MMU fault. */ -void MMU_FaultDpc(IN void *pRefData) +void MMU_FaultDpc(IN unsigned long pRefData) { struct DEH_MGR *hDehMgr = (struct DEH_MGR *)pRefData; struct DEH_MGR *pDehMgr = (struct DEH_MGR *)hDehMgr; diff --git a/drivers/dsp/bridge/wmd/mmu_fault.h b/drivers/dsp/bridge/wmd/mmu_fault.h index bed466c..d3849b5 100644 --- a/drivers/dsp/bridge/wmd/mmu_fault.h +++ b/drivers/dsp/bridge/wmd/mmu_fault.h @@ -23,7 +23,7 @@ * ======== MMU_FaultDpc ======== * Deferred procedure call to handle DSP MMU fault. */ - void MMU_FaultDpc(IN void *pRefData); + void MMU_FaultDpc(IN unsigned long pRefData); /* * ======== MMU_FaultIsr ======== diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c index 12f73e7..4d0bcf2 100644 --- a/drivers/dsp/bridge/wmd/ue_deh.c +++ b/drivers/dsp/bridge/wmd/ue_deh.c @@ -95,11 +95,8 @@ DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr, SIGNATURE); if (pDehMgr->hMmuFaultDpc) { tasklet_init(&pDehMgr->hMmuFaultDpc->dpc_tasklet, - DPC_DeferredProcedure, - (u32)pDehMgr->hMmuFaultDpc); + MMU_FaultDpc, (u32)pDehMgr); /* Fill out DPC Object */ - pDehMgr->hMmuFaultDpc->pRefData = (void *)pDehMgr; - pDehMgr->hMmuFaultDpc->pfnDPC = MMU_FaultDpc; pDehMgr->hMmuFaultDpc->numRequested = 0; pDehMgr->hMmuFaultDpc->numScheduled = 0; #ifdef DEBUG -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 19/20] DSPBRIDGE: Remove DPC module from SERVICES layer 2009-11-30 21:54 ` [PATCH v2 18/20] DSPBRIDGE: Remove main DPC wrapper for IO and MMUfault Omar Ramirez Luna @ 2009-11-30 21:55 ` Omar Ramirez Luna 2009-11-30 21:55 ` [PATCH v2 20/20] DSPBRIDGE: Remove DPC object structure Omar Ramirez Luna 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:55 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna This patch removes init and exit functions for DPC module. It also deletes dpc source file and takes out the module from Makefile. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- arch/arm/plat-omap/include/dspbridge/dpc.h | 26 ----------- drivers/dsp/bridge/Makefile | 3 +- drivers/dsp/bridge/services/dpc.c | 68 ---------------------------- drivers/dsp/bridge/services/services.c | 9 +--- 4 files changed, 3 insertions(+), 103 deletions(-) delete mode 100644 drivers/dsp/bridge/services/dpc.c diff --git a/arch/arm/plat-omap/include/dspbridge/dpc.h b/arch/arm/plat-omap/include/dspbridge/dpc.h index b22140f..aee910d 100644 --- a/arch/arm/plat-omap/include/dspbridge/dpc.h +++ b/arch/arm/plat-omap/include/dspbridge/dpc.h @@ -35,30 +35,4 @@ struct DPC_OBJECT { spinlock_t dpc_lock; }; -/* - * ======== DPC_Exit ======== - * Purpose: - * Discontinue usage of the DPC module. - * Parameters: - * Returns: - * Requires: - * DPC_Init(void) was previously called. - * Ensures: - * Resources acquired in DPC_Init(void) are freed. - */ - extern void DPC_Exit(void); - -/* - * ======== DPC_Init ======== - * Purpose: - * Initialize the DPC module's private state. - * Parameters: - * Returns: - * TRUE if initialized; FALSE if error occured. - * Requires: - * Ensures: - * A requirement for each of the other public DPC functions. - */ - extern bool DPC_Init(void); - #endif /* DPC_ */ diff --git a/drivers/dsp/bridge/Makefile b/drivers/dsp/bridge/Makefile index cb6d1ce..df870c9 100644 --- a/drivers/dsp/bridge/Makefile +++ b/drivers/dsp/bridge/Makefile @@ -1,8 +1,7 @@ obj-$(CONFIG_MPU_BRIDGE) += bridgedriver.o libgen = gen/gb.o gen/gt.o gen/gs.o gen/gh.o gen/_gt_para.o gen/uuidutil.o -libservices = services/mem.o services/list.o services/dpc.o \ - services/sync.o \ +libservices = services/mem.o services/list.o services/sync.o \ services/clk.o services/cfg.o services/reg.o \ services/regsup.o services/ntfy.o \ services/dbg.o services/services.o diff --git a/drivers/dsp/bridge/services/dpc.c b/drivers/dsp/bridge/services/dpc.c deleted file mode 100644 index bbb2d47..0000000 --- a/drivers/dsp/bridge/services/dpc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * dpc.c - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Deferred Procedure Call(DPC) Services. - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* ----------------------------------- Host OS */ -#include <dspbridge/host_os.h> - -/* ----------------------------------- DSP/BIOS Bridge */ -#include <dspbridge/std.h> -#include <dspbridge/dbdefs.h> -#include <dspbridge/errbase.h> - -/* ----------------------------------- Trace & Debug */ -#include <dspbridge/dbc.h> -#include <dspbridge/gt.h> - -/* ----------------------------------- OS Adaptation Layer */ -#include <dspbridge/mem.h> - -/* ----------------------------------- This */ -#include <dspbridge/dpc.h> - -/* ----------------------------------- Defines, Data Structures, Typedefs */ -#define SIGNATURE 0x5f435044 /* "DPC_" (in reverse). */ - -/* ----------------------------------- Globals */ -#if GT_TRACE -static struct GT_Mask DPC_DebugMask = { NULL, NULL }; /* DPC Debug Mask */ -#endif - -/* - * ======== DPC_Exit ======== - * Purpose: - * Discontinue usage of the DPC module. - */ -void DPC_Exit(void) -{ - GT_0trace(DPC_DebugMask, GT_5CLASS, "Entered DPC_Exit\n"); -} - -/* - * ======== DPC_Init ======== - * Purpose: - * Initialize the DPC module's private state. - */ -bool DPC_Init(void) -{ - GT_create(&DPC_DebugMask, "DP"); - - GT_0trace(DPC_DebugMask, GT_5CLASS, "Entered DPC_Init\n"); - - return true; -} - diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c index dc9bfad..0b7d623 100644 --- a/drivers/dsp/bridge/services/services.c +++ b/drivers/dsp/bridge/services/services.c @@ -68,7 +68,6 @@ void SERVICES_Exit(void) CLK_Exit(); REG_Exit(); LST_Exit(); - DPC_Exit(); DBG_Exit(); CFG_Exit(); MEM_Exit(); @@ -87,7 +86,7 @@ void SERVICES_Exit(void) bool SERVICES_Init(void) { bool fInit = true; - bool fCFG, fDBG, fDPC, fLST, fMEM; + bool fCFG, fDBG, fLST, fMEM; bool fREG, fSYNC, fCLK, fNTFY; DBC_Require(cRefs >= 0); @@ -106,12 +105,11 @@ bool SERVICES_Init(void) fREG = REG_Init(); fCFG = CFG_Init(); fDBG = DBG_Init(); - fDPC = DPC_Init(); fLST = LST_Init(); fCLK = CLK_Init(); fNTFY = NTFY_Init(); - fInit = fCFG && fDBG && fDPC && + fInit = fCFG && fDBG && fLST && fMEM && fREG && fSYNC && fCLK; if (!fInit) { @@ -130,9 +128,6 @@ bool SERVICES_Init(void) if (fLST) LST_Exit(); - if (fDPC) - DPC_Exit(); - if (fDBG) DBG_Exit(); -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 20/20] DSPBRIDGE: Remove DPC object structure 2009-11-30 21:55 ` [PATCH v2 19/20] DSPBRIDGE: Remove DPC module from SERVICES layer Omar Ramirez Luna @ 2009-11-30 21:55 ` Omar Ramirez Luna 2009-11-30 22:52 ` [RESEND][PATCH " Ramirez Luna, Omar 0 siblings, 1 reply; 28+ messages in thread From: Omar Ramirez Luna @ 2009-11-30 21:55 UTC (permalink / raw) To: linux-omap; +Cc: Omar Ramirez Luna Remove DPC object structure and declare required members for each tasklet inside their correspondent modules. Remove dpc header file. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- arch/arm/plat-omap/include/dspbridge/_chnl_sm.h | 1 - arch/arm/plat-omap/include/dspbridge/dpc.h | 38 ------------ drivers/dsp/bridge/pmgr/chnl.c | 1 - drivers/dsp/bridge/services/services.c | 1 - drivers/dsp/bridge/wmd/_deh.h | 5 +- drivers/dsp/bridge/wmd/io_sm.c | 72 +++++++++------------- drivers/dsp/bridge/wmd/mmu_fault.c | 24 +------- drivers/dsp/bridge/wmd/ue_deh.c | 25 +------- 8 files changed, 38 insertions(+), 129 deletions(-) delete mode 100644 arch/arm/plat-omap/include/dspbridge/dpc.h diff --git a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h index f22b2cb..eb5adc2 100644 --- a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h @@ -25,7 +25,6 @@ #include <dspbridge/wcd.h> #include <dspbridge/wmd.h> -#include <dspbridge/dpc.h> #include <dspbridge/list.h> #include <dspbridge/ntfy.h> diff --git a/arch/arm/plat-omap/include/dspbridge/dpc.h b/arch/arm/plat-omap/include/dspbridge/dpc.h deleted file mode 100644 index aee910d..0000000 --- a/arch/arm/plat-omap/include/dspbridge/dpc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * dpc.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Deferred Procedure Call(DPC) Services. - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef DPC_ -#define DPC_ - -/* The DPC object, passed to our priority event callback routine: */ -struct DPC_OBJECT { - u32 dwSignature; /* Used for object validation. */ - void *pRefData; /* Argument for client's DPC. */ - u32 numRequested; /* Number of requested DPC's. */ - u32 numScheduled; /* Number of executed DPC's. */ - struct tasklet_struct dpc_tasklet; - -#ifdef DEBUG - u32 cEntryCount; /* Number of times DPC reentered. */ - u32 numRequestedMax; /* Keep track of max pending DPC's. */ -#endif - - spinlock_t dpc_lock; -}; - -#endif /* DPC_ */ diff --git a/drivers/dsp/bridge/pmgr/chnl.c b/drivers/dsp/bridge/pmgr/chnl.c index f4d0fc1..fd487f0 100644 --- a/drivers/dsp/bridge/pmgr/chnl.c +++ b/drivers/dsp/bridge/pmgr/chnl.c @@ -31,7 +31,6 @@ /* ----------------------------------- OS Adaptation Layer */ #include <dspbridge/cfg.h> -#include <dspbridge/dpc.h> #include <dspbridge/list.h> #include <dspbridge/mem.h> #include <dspbridge/sync.h> diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c index 0b7d623..5590634 100644 --- a/drivers/dsp/bridge/services/services.c +++ b/drivers/dsp/bridge/services/services.c @@ -29,7 +29,6 @@ /* ----------------------------------- OS Adaptation Layer */ #include <dspbridge/cfg.h> #include <dspbridge/dbg.h> -#include <dspbridge/dpc.h> #include <dspbridge/list.h> #include <dspbridge/mem.h> #include <dspbridge/ntfy.h> diff --git a/drivers/dsp/bridge/wmd/_deh.h b/drivers/dsp/bridge/wmd/_deh.h index 2b364b5..aadb9fa 100644 --- a/drivers/dsp/bridge/wmd/_deh.h +++ b/drivers/dsp/bridge/wmd/_deh.h @@ -19,7 +19,6 @@ #ifndef _DEH_ #define _DEH_ -#include <dspbridge/dpc.h> #include <dspbridge/ntfy.h> #include <dspbridge/wmd.h> @@ -30,8 +29,10 @@ struct DEH_MGR { u32 dwSignature; /* Used for object validation. */ struct WMD_DEV_CONTEXT *hWmdContext; /* WMD device context. */ struct NTFY_OBJECT *hNtfy; /* NTFY object */ - struct DPC_OBJECT *hMmuFaultDpc; /* DPC object handle. */ struct DSP_ERRORINFO errInfo; /* DSP exception info. */ + + /* MMU Fault DPC */ + struct tasklet_struct dpc_tasklet; } ; #endif /* _DEH_ */ diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index 177dbbc..a1c028a 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -43,7 +43,6 @@ /* Services Layer */ #include <dspbridge/cfg.h> -#include <dspbridge/dpc.h> #include <dspbridge/mem.h> #include <dspbridge/ntfy.h> #include <dspbridge/sync.h> @@ -108,7 +107,6 @@ struct IO_MGR { u8 *pMsgOutput; /* Address of output messages */ u32 uSMBufSize; /* Size of a shared memory I/O channel */ bool fSharedIRQ; /* Is this IRQ shared? */ - struct DPC_OBJECT *hDPC; /* DPC object handle */ struct SYNC_CSOBJECT *hCSObj; /* Critical section object handle */ u32 uWordSize; /* Size in bytes of DSP word */ u16 wIntrVal; /* Interrupt value */ @@ -128,6 +126,12 @@ struct IO_MGR { u32 ulGppVa; u32 ulDspVa; #endif + /* IO Dpc */ + u32 dpc_req; /* Number of requested DPC's. */ + u32 dpc_sched; /* Number of executed DPC's. */ + struct tasklet_struct dpc_tasklet; + spinlock_t dpc_lock; + } ; /* Function Prototypes */ @@ -250,24 +254,14 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = SYNC_InitializeCS(&pIOMgr->hCSObj); if (devType == DSP_UNIT) { - /* Create a DPC object */ - MEM_AllocObject(pIOMgr->hDPC, struct DPC_OBJECT, - IO_MGRSIGNATURE); - if (pIOMgr->hDPC) { - tasklet_init(&pIOMgr->hDPC->dpc_tasklet, - IO_DPC, (u32)pIOMgr); - /* Fill out our DPC Object */ - pIOMgr->hDPC->numRequested = 0; - pIOMgr->hDPC->numScheduled = 0; -#ifdef DEBUG - pIOMgr->hDPC->numRequestedMax = 0; - pIOMgr->hDPC->cEntryCount = 0; -#endif - spin_lock_init(&pIOMgr->hDPC->dpc_lock); - } else { - DBG_Trace(GT_6CLASS, "IO DPC Create: DSP_EMEMORY\n"); - status = DSP_EMEMORY; - } + /* Create an IO DPC */ + tasklet_init(&pIOMgr->dpc_tasklet, IO_DPC, (u32)pIOMgr); + + /* Initialize DPC counters */ + pIOMgr->dpc_req = 0; + pIOMgr->dpc_sched = 0; + + spin_lock_init(&pIOMgr->dpc_lock); if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -330,10 +324,8 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) /* Linux function to uninstall ISR */ free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr); - /* Free DPC object */ - tasklet_kill(&hIOMgr->hDPC->dpc_tasklet); - MEM_FreeObject(hIOMgr->hDPC); - hIOMgr->hDPC = NULL; + /* Free IO DPC object */ + tasklet_kill(&hIOMgr->dpc_tasklet); DBG_Trace(GT_2CLASS, "DPC_Destroy: SUCCESS\n"); #ifndef DSP_TRACEBUF_DISABLED @@ -1026,8 +1018,8 @@ void IO_DPC(IN OUT unsigned long pRefData) goto func_end; DBG_Trace(DBG_LEVEL7, "Entering IO_DPC(0x%x)\n", pRefData); - requested = pIOMgr->hDPC->numRequested; - serviced = pIOMgr->hDPC->numScheduled; + requested = pIOMgr->dpc_req; + serviced = pIOMgr->dpc_sched; if (serviced == requested) goto func_end; @@ -1056,7 +1048,7 @@ void IO_DPC(IN OUT unsigned long pRefData) #endif serviced++; } while (serviced != requested); - pIOMgr->hDPC->numScheduled = requested; + pIOMgr->dpc_sched = requested; func_end: return; } @@ -1098,11 +1090,12 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) * PROC-COPY defer i/o. * Increment count of DPC's pending. */ - spin_lock_irqsave(&hIOMgr->hDPC->dpc_lock, flags); - hIOMgr->hDPC->numRequested++; - spin_unlock_irqrestore(&hIOMgr->hDPC->dpc_lock, flags); + spin_lock_irqsave(&hIOMgr->dpc_lock, flags); + hIOMgr->dpc_req++; + spin_unlock_irqrestore(&hIOMgr->dpc_lock, flags); /* Schedule DPC */ +<<<<<<< HEAD:drivers/dsp/bridge/wmd/io_sm.c tasklet_schedule(&hIOMgr->hDPC->dpc_tasklet); #ifdef DEBUG if (hIOMgr->hDPC->numRequested > @@ -1113,6 +1106,9 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) hIOMgr->hDPC->numScheduled; } #endif +======= + tasklet_schedule(&hIOMgr->dpc_tasklet); +>>>>>>> b7df160... DSPBRIDGE: Remove DPC object structure:drivers/dsp/bridge/wmd/io_sm.c } } else /* Ensure that, if WMD didn't claim it, the IRQ is shared. */ @@ -1180,20 +1176,12 @@ void IO_Schedule(struct IO_MGR *pIOMgr) tiomap3430_bump_dsp_opp_level(); /* Increment count of DPC's pending. */ - spin_lock_irqsave(&pIOMgr->hDPC->dpc_lock, flags); - pIOMgr->hDPC->numRequested++; - spin_unlock_irqrestore(&pIOMgr->hDPC->dpc_lock, flags); + spin_lock_irqsave(&pIOMgr->dpc_lock, flags); + pIOMgr->dpc_req++; + spin_unlock_irqrestore(&pIOMgr->dpc_lock, flags); /* Schedule DPC */ - tasklet_schedule(&pIOMgr->hDPC->dpc_tasklet); -#ifdef DEBUG - if (pIOMgr->hDPC->numRequested > pIOMgr->hDPC->numScheduled + - pIOMgr->hDPC->numRequestedMax) { - pIOMgr->hDPC->numRequestedMax = pIOMgr->hDPC->numRequested - - pIOMgr->hDPC->numScheduled; - } -#endif - + tasklet_schedule(&pIOMgr->dpc_tasklet); } /* diff --git a/drivers/dsp/bridge/wmd/mmu_fault.c b/drivers/dsp/bridge/wmd/mmu_fault.c index b3f0719..b184250 100644 --- a/drivers/dsp/bridge/wmd/mmu_fault.c +++ b/drivers/dsp/bridge/wmd/mmu_fault.c @@ -27,7 +27,6 @@ #include <dspbridge/dbg.h> /* ----------------------------------- OS Adaptation Layer */ -#include <dspbridge/dpc.h> #include <dspbridge/mem.h> #include <dspbridge/drv.h> @@ -57,11 +56,10 @@ static bool MMU_CheckIfFault(struct WMD_DEV_CONTEXT *pDevContext); void MMU_FaultDpc(IN unsigned long pRefData) { struct DEH_MGR *hDehMgr = (struct DEH_MGR *)pRefData; - struct DEH_MGR *pDehMgr = (struct DEH_MGR *)hDehMgr; DBG_Trace(DBG_LEVEL1, "MMU_FaultDpc Enter: 0x%x\n", pRefData); - if (pDehMgr) + if (hDehMgr) WMD_DEH_Notify(hDehMgr, DSP_MMUFAULT, 0L); DBG_Trace(DBG_LEVEL1, "MMU_FaultDpc Exit: 0x%x\n", pRefData); @@ -76,7 +74,6 @@ irqreturn_t MMU_FaultIsr(int irq, IN void *pRefData) struct DEH_MGR *pDehMgr = (struct DEH_MGR *)pRefData; struct WMD_DEV_CONTEXT *pDevContext; DSP_STATUS status = DSP_SOK; - unsigned long flags; DBG_Trace(DBG_LEVEL1, "Entering DEH_DspMmuIsr: 0x%x\n", pRefData); DBC_Require(irq == INT_DSP_MMU_IRQ); @@ -99,24 +96,7 @@ irqreturn_t MMU_FaultIsr(int irq, IN void *pRefData) * necessary to check if DSP MMU fault is intended for * Bridge. */ - /* Increment count of DPC's pending. */ - spin_lock_irqsave(&pDehMgr->hMmuFaultDpc->dpc_lock, - flags); - pDehMgr->hMmuFaultDpc->numRequested++; - spin_unlock_irqrestore(&pDehMgr->hMmuFaultDpc->dpc_lock, - flags); - - /* Schedule DPC */ - tasklet_schedule(&pDehMgr->hMmuFaultDpc->dpc_tasklet); -#ifdef DEBUG - if (pDehMgr->hMmuFaultDpc->numRequested > - pDehMgr->hMmuFaultDpc->numScheduled + - pDehMgr->hMmuFaultDpc->numRequestedMax) { - pDehMgr->hMmuFaultDpc->numRequestedMax = - pDehMgr->hMmuFaultDpc->numRequested - - pDehMgr->hMmuFaultDpc->numScheduled; - } -#endif + tasklet_schedule(&pDehMgr->dpc_tasklet); /* Reset errInfo structure before use. */ pDehMgr->errInfo.dwErrMask = DSP_MMUFAULT; diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c index 4d0bcf2..6a1314f 100644 --- a/drivers/dsp/bridge/wmd/ue_deh.c +++ b/drivers/dsp/bridge/wmd/ue_deh.c @@ -30,7 +30,6 @@ /* ----------------------------------- OS Adaptation Layer */ #include <dspbridge/cfg.h> -#include <dspbridge/dpc.h> #include <dspbridge/mem.h> #include <dspbridge/ntfy.h> #include <dspbridge/drv.h> @@ -90,24 +89,8 @@ DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr, if (DSP_SUCCEEDED(status)) status = NTFY_Create(&pDehMgr->hNtfy); - /* Create a DPC object. */ - MEM_AllocObject(pDehMgr->hMmuFaultDpc, struct DPC_OBJECT, - SIGNATURE); - if (pDehMgr->hMmuFaultDpc) { - tasklet_init(&pDehMgr->hMmuFaultDpc->dpc_tasklet, - MMU_FaultDpc, (u32)pDehMgr); - /* Fill out DPC Object */ - pDehMgr->hMmuFaultDpc->numRequested = 0; - pDehMgr->hMmuFaultDpc->numScheduled = 0; -#ifdef DEBUG - pDehMgr->hMmuFaultDpc->numRequestedMax = 0; - pDehMgr->hMmuFaultDpc->cEntryCount = 0; -#endif - spin_lock_init(&pDehMgr->hMmuFaultDpc->dpc_lock); - } else { - DBG_Trace(GT_6CLASS, "DEH DPC Create: DSP_EMEMORY\n"); - status = DSP_EMEMORY; - } + /* Create a MMUfault DPC */ + tasklet_init(&pDehMgr->dpc_tasklet, MMU_FaultDpc, (u32)pDehMgr); if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -162,9 +145,7 @@ DSP_STATUS WMD_DEH_Destroy(struct DEH_MGR *hDehMgr) free_irq(INT_DSP_MMU_IRQ, pDehMgr); /* Free DPC object */ - tasklet_kill(&pDehMgr->hMmuFaultDpc->dpc_tasklet); - MEM_FreeObject(pDehMgr->hMmuFaultDpc); - pDehMgr->hMmuFaultDpc = NULL; + tasklet_kill(&pDehMgr->dpc_tasklet); DBG_Trace(GT_2CLASS, "DPC_Destroy: SUCCESS\n"); /* Deallocate the DEH manager object */ -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [RESEND][PATCH v2 20/20] DSPBRIDGE: Remove DPC object structure 2009-11-30 21:55 ` [PATCH v2 20/20] DSPBRIDGE: Remove DPC object structure Omar Ramirez Luna @ 2009-11-30 22:52 ` Ramirez Luna, Omar 0 siblings, 0 replies; 28+ messages in thread From: Ramirez Luna, Omar @ 2009-11-30 22:52 UTC (permalink / raw) To: linux-omap Remove DPC object structure and declare required members for each tasklet inside their correspondent modules. Remove dpc header file. Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> --- arch/arm/plat-omap/include/dspbridge/_chnl_sm.h | 1 - arch/arm/plat-omap/include/dspbridge/dpc.h | 38 ----------- drivers/dsp/bridge/pmgr/chnl.c | 1 - drivers/dsp/bridge/services/services.c | 1 - drivers/dsp/bridge/wmd/_deh.h | 5 +- drivers/dsp/bridge/wmd/io_sm.c | 79 ++++++++--------------- drivers/dsp/bridge/wmd/mmu_fault.c | 24 +------ drivers/dsp/bridge/wmd/ue_deh.c | 25 +------ 8 files changed, 35 insertions(+), 139 deletions(-) delete mode 100644 arch/arm/plat-omap/include/dspbridge/dpc.h diff --git a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h index f22b2cb..eb5adc2 100644 --- a/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h +++ b/arch/arm/plat-omap/include/dspbridge/_chnl_sm.h @@ -25,7 +25,6 @@ #include <dspbridge/wcd.h> #include <dspbridge/wmd.h> -#include <dspbridge/dpc.h> #include <dspbridge/list.h> #include <dspbridge/ntfy.h> diff --git a/arch/arm/plat-omap/include/dspbridge/dpc.h b/arch/arm/plat-omap/include/dspbridge/dpc.h deleted file mode 100644 index aee910d..0000000 --- a/arch/arm/plat-omap/include/dspbridge/dpc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * dpc.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Deferred Procedure Call(DPC) Services. - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef DPC_ -#define DPC_ - -/* The DPC object, passed to our priority event callback routine: */ -struct DPC_OBJECT { - u32 dwSignature; /* Used for object validation. */ - void *pRefData; /* Argument for client's DPC. */ - u32 numRequested; /* Number of requested DPC's. */ - u32 numScheduled; /* Number of executed DPC's. */ - struct tasklet_struct dpc_tasklet; - -#ifdef DEBUG - u32 cEntryCount; /* Number of times DPC reentered. */ - u32 numRequestedMax; /* Keep track of max pending DPC's. */ -#endif - - spinlock_t dpc_lock; -}; - -#endif /* DPC_ */ diff --git a/drivers/dsp/bridge/pmgr/chnl.c b/drivers/dsp/bridge/pmgr/chnl.c index f4d0fc1..fd487f0 100644 --- a/drivers/dsp/bridge/pmgr/chnl.c +++ b/drivers/dsp/bridge/pmgr/chnl.c @@ -31,7 +31,6 @@ /* ----------------------------------- OS Adaptation Layer */ #include <dspbridge/cfg.h> -#include <dspbridge/dpc.h> #include <dspbridge/list.h> #include <dspbridge/mem.h> #include <dspbridge/sync.h> diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c index 0b7d623..5590634 100644 --- a/drivers/dsp/bridge/services/services.c +++ b/drivers/dsp/bridge/services/services.c @@ -29,7 +29,6 @@ /* ----------------------------------- OS Adaptation Layer */ #include <dspbridge/cfg.h> #include <dspbridge/dbg.h> -#include <dspbridge/dpc.h> #include <dspbridge/list.h> #include <dspbridge/mem.h> #include <dspbridge/ntfy.h> diff --git a/drivers/dsp/bridge/wmd/_deh.h b/drivers/dsp/bridge/wmd/_deh.h index 2b364b5..aadb9fa 100644 --- a/drivers/dsp/bridge/wmd/_deh.h +++ b/drivers/dsp/bridge/wmd/_deh.h @@ -19,7 +19,6 @@ #ifndef _DEH_ #define _DEH_ -#include <dspbridge/dpc.h> #include <dspbridge/ntfy.h> #include <dspbridge/wmd.h> @@ -30,8 +29,10 @@ struct DEH_MGR { u32 dwSignature; /* Used for object validation. */ struct WMD_DEV_CONTEXT *hWmdContext; /* WMD device context. */ struct NTFY_OBJECT *hNtfy; /* NTFY object */ - struct DPC_OBJECT *hMmuFaultDpc; /* DPC object handle. */ struct DSP_ERRORINFO errInfo; /* DSP exception info. */ + + /* MMU Fault DPC */ + struct tasklet_struct dpc_tasklet; } ; #endif /* _DEH_ */ diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c index 177dbbc..5734e50 100644 --- a/drivers/dsp/bridge/wmd/io_sm.c +++ b/drivers/dsp/bridge/wmd/io_sm.c @@ -43,7 +43,6 @@ /* Services Layer */ #include <dspbridge/cfg.h> -#include <dspbridge/dpc.h> #include <dspbridge/mem.h> #include <dspbridge/ntfy.h> #include <dspbridge/sync.h> @@ -108,7 +107,6 @@ struct IO_MGR { u8 *pMsgOutput; /* Address of output messages */ u32 uSMBufSize; /* Size of a shared memory I/O channel */ bool fSharedIRQ; /* Is this IRQ shared? */ - struct DPC_OBJECT *hDPC; /* DPC object handle */ struct SYNC_CSOBJECT *hCSObj; /* Critical section object handle */ u32 uWordSize; /* Size in bytes of DSP word */ u16 wIntrVal; /* Interrupt value */ @@ -128,6 +126,12 @@ struct IO_MGR { u32 ulGppVa; u32 ulDspVa; #endif + /* IO Dpc */ + u32 dpc_req; /* Number of requested DPC's. */ + u32 dpc_sched; /* Number of executed DPC's. */ + struct tasklet_struct dpc_tasklet; + spinlock_t dpc_lock; + } ; /* Function Prototypes */ @@ -250,24 +254,14 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr, status = SYNC_InitializeCS(&pIOMgr->hCSObj); if (devType == DSP_UNIT) { - /* Create a DPC object */ - MEM_AllocObject(pIOMgr->hDPC, struct DPC_OBJECT, - IO_MGRSIGNATURE); - if (pIOMgr->hDPC) { - tasklet_init(&pIOMgr->hDPC->dpc_tasklet, - IO_DPC, (u32)pIOMgr); - /* Fill out our DPC Object */ - pIOMgr->hDPC->numRequested = 0; - pIOMgr->hDPC->numScheduled = 0; -#ifdef DEBUG - pIOMgr->hDPC->numRequestedMax = 0; - pIOMgr->hDPC->cEntryCount = 0; -#endif - spin_lock_init(&pIOMgr->hDPC->dpc_lock); - } else { - DBG_Trace(GT_6CLASS, "IO DPC Create: DSP_EMEMORY\n"); - status = DSP_EMEMORY; - } + /* Create an IO DPC */ + tasklet_init(&pIOMgr->dpc_tasklet, IO_DPC, (u32)pIOMgr); + + /* Initialize DPC counters */ + pIOMgr->dpc_req = 0; + pIOMgr->dpc_sched = 0; + + spin_lock_init(&pIOMgr->dpc_lock); if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -330,10 +324,8 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) /* Linux function to uninstall ISR */ free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr); - /* Free DPC object */ - tasklet_kill(&hIOMgr->hDPC->dpc_tasklet); - MEM_FreeObject(hIOMgr->hDPC); - hIOMgr->hDPC = NULL; + /* Free IO DPC object */ + tasklet_kill(&hIOMgr->dpc_tasklet); DBG_Trace(GT_2CLASS, "DPC_Destroy: SUCCESS\n"); #ifndef DSP_TRACEBUF_DISABLED @@ -1026,8 +1018,8 @@ void IO_DPC(IN OUT unsigned long pRefData) goto func_end; DBG_Trace(DBG_LEVEL7, "Entering IO_DPC(0x%x)\n", pRefData); - requested = pIOMgr->hDPC->numRequested; - serviced = pIOMgr->hDPC->numScheduled; + requested = pIOMgr->dpc_req; + serviced = pIOMgr->dpc_sched; if (serviced == requested) goto func_end; @@ -1056,7 +1048,7 @@ void IO_DPC(IN OUT unsigned long pRefData) #endif serviced++; } while (serviced != requested); - pIOMgr->hDPC->numScheduled = requested; + pIOMgr->dpc_sched = requested; func_end: return; } @@ -1098,21 +1090,12 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) * PROC-COPY defer i/o. * Increment count of DPC's pending. */ - spin_lock_irqsave(&hIOMgr->hDPC->dpc_lock, flags); - hIOMgr->hDPC->numRequested++; - spin_unlock_irqrestore(&hIOMgr->hDPC->dpc_lock, flags); + spin_lock_irqsave(&hIOMgr->dpc_lock, flags); + hIOMgr->dpc_req++; + spin_unlock_irqrestore(&hIOMgr->dpc_lock, flags); /* Schedule DPC */ - tasklet_schedule(&hIOMgr->hDPC->dpc_tasklet); -#ifdef DEBUG - if (hIOMgr->hDPC->numRequested > - hIOMgr->hDPC->numScheduled + - hIOMgr->hDPC->numRequestedMax) { - hIOMgr->hDPC->numRequestedMax = - hIOMgr->hDPC->numRequested - - hIOMgr->hDPC->numScheduled; - } -#endif + tasklet_schedule(&hIOMgr->dpc_tasklet); } } else /* Ensure that, if WMD didn't claim it, the IRQ is shared. */ @@ -1180,20 +1163,12 @@ void IO_Schedule(struct IO_MGR *pIOMgr) tiomap3430_bump_dsp_opp_level(); /* Increment count of DPC's pending. */ - spin_lock_irqsave(&pIOMgr->hDPC->dpc_lock, flags); - pIOMgr->hDPC->numRequested++; - spin_unlock_irqrestore(&pIOMgr->hDPC->dpc_lock, flags); + spin_lock_irqsave(&pIOMgr->dpc_lock, flags); + pIOMgr->dpc_req++; + spin_unlock_irqrestore(&pIOMgr->dpc_lock, flags); /* Schedule DPC */ - tasklet_schedule(&pIOMgr->hDPC->dpc_tasklet); -#ifdef DEBUG - if (pIOMgr->hDPC->numRequested > pIOMgr->hDPC->numScheduled + - pIOMgr->hDPC->numRequestedMax) { - pIOMgr->hDPC->numRequestedMax = pIOMgr->hDPC->numRequested - - pIOMgr->hDPC->numScheduled; - } -#endif - + tasklet_schedule(&pIOMgr->dpc_tasklet); } /* diff --git a/drivers/dsp/bridge/wmd/mmu_fault.c b/drivers/dsp/bridge/wmd/mmu_fault.c index b3f0719..b184250 100644 --- a/drivers/dsp/bridge/wmd/mmu_fault.c +++ b/drivers/dsp/bridge/wmd/mmu_fault.c @@ -27,7 +27,6 @@ #include <dspbridge/dbg.h> /* ----------------------------------- OS Adaptation Layer */ -#include <dspbridge/dpc.h> #include <dspbridge/mem.h> #include <dspbridge/drv.h> @@ -57,11 +56,10 @@ static bool MMU_CheckIfFault(struct WMD_DEV_CONTEXT *pDevContext); void MMU_FaultDpc(IN unsigned long pRefData) { struct DEH_MGR *hDehMgr = (struct DEH_MGR *)pRefData; - struct DEH_MGR *pDehMgr = (struct DEH_MGR *)hDehMgr; DBG_Trace(DBG_LEVEL1, "MMU_FaultDpc Enter: 0x%x\n", pRefData); - if (pDehMgr) + if (hDehMgr) WMD_DEH_Notify(hDehMgr, DSP_MMUFAULT, 0L); DBG_Trace(DBG_LEVEL1, "MMU_FaultDpc Exit: 0x%x\n", pRefData); @@ -76,7 +74,6 @@ irqreturn_t MMU_FaultIsr(int irq, IN void *pRefData) struct DEH_MGR *pDehMgr = (struct DEH_MGR *)pRefData; struct WMD_DEV_CONTEXT *pDevContext; DSP_STATUS status = DSP_SOK; - unsigned long flags; DBG_Trace(DBG_LEVEL1, "Entering DEH_DspMmuIsr: 0x%x\n", pRefData); DBC_Require(irq == INT_DSP_MMU_IRQ); @@ -99,24 +96,7 @@ irqreturn_t MMU_FaultIsr(int irq, IN void *pRefData) * necessary to check if DSP MMU fault is intended for * Bridge. */ - /* Increment count of DPC's pending. */ - spin_lock_irqsave(&pDehMgr->hMmuFaultDpc->dpc_lock, - flags); - pDehMgr->hMmuFaultDpc->numRequested++; - spin_unlock_irqrestore(&pDehMgr->hMmuFaultDpc->dpc_lock, - flags); - - /* Schedule DPC */ - tasklet_schedule(&pDehMgr->hMmuFaultDpc->dpc_tasklet); -#ifdef DEBUG - if (pDehMgr->hMmuFaultDpc->numRequested > - pDehMgr->hMmuFaultDpc->numScheduled + - pDehMgr->hMmuFaultDpc->numRequestedMax) { - pDehMgr->hMmuFaultDpc->numRequestedMax = - pDehMgr->hMmuFaultDpc->numRequested - - pDehMgr->hMmuFaultDpc->numScheduled; - } -#endif + tasklet_schedule(&pDehMgr->dpc_tasklet); /* Reset errInfo structure before use. */ pDehMgr->errInfo.dwErrMask = DSP_MMUFAULT; diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c index 4d0bcf2..6a1314f 100644 --- a/drivers/dsp/bridge/wmd/ue_deh.c +++ b/drivers/dsp/bridge/wmd/ue_deh.c @@ -30,7 +30,6 @@ /* ----------------------------------- OS Adaptation Layer */ #include <dspbridge/cfg.h> -#include <dspbridge/dpc.h> #include <dspbridge/mem.h> #include <dspbridge/ntfy.h> #include <dspbridge/drv.h> @@ -90,24 +89,8 @@ DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr, if (DSP_SUCCEEDED(status)) status = NTFY_Create(&pDehMgr->hNtfy); - /* Create a DPC object. */ - MEM_AllocObject(pDehMgr->hMmuFaultDpc, struct DPC_OBJECT, - SIGNATURE); - if (pDehMgr->hMmuFaultDpc) { - tasklet_init(&pDehMgr->hMmuFaultDpc->dpc_tasklet, - MMU_FaultDpc, (u32)pDehMgr); - /* Fill out DPC Object */ - pDehMgr->hMmuFaultDpc->numRequested = 0; - pDehMgr->hMmuFaultDpc->numScheduled = 0; -#ifdef DEBUG - pDehMgr->hMmuFaultDpc->numRequestedMax = 0; - pDehMgr->hMmuFaultDpc->cEntryCount = 0; -#endif - spin_lock_init(&pDehMgr->hMmuFaultDpc->dpc_lock); - } else { - DBG_Trace(GT_6CLASS, "DEH DPC Create: DSP_EMEMORY\n"); - status = DSP_EMEMORY; - } + /* Create a MMUfault DPC */ + tasklet_init(&pDehMgr->dpc_tasklet, MMU_FaultDpc, (u32)pDehMgr); if (DSP_SUCCEEDED(status)) status = DEV_GetDevNode(hDevObject, &hDevNode); @@ -162,9 +145,7 @@ DSP_STATUS WMD_DEH_Destroy(struct DEH_MGR *hDehMgr) free_irq(INT_DSP_MMU_IRQ, pDehMgr); /* Free DPC object */ - tasklet_kill(&pDehMgr->hMmuFaultDpc->dpc_tasklet); - MEM_FreeObject(pDehMgr->hMmuFaultDpc); - pDehMgr->hMmuFaultDpc = NULL; + tasklet_kill(&pDehMgr->dpc_tasklet); DBG_Trace(GT_2CLASS, "DPC_Destroy: SUCCESS\n"); /* Deallocate the DEH manager object */ -- 1.6.2.4 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm 2009-11-30 21:54 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 16/20] DSPBRIDGE: trivial fix for multiline comments on io_sm Omar Ramirez Luna @ 2009-12-01 6:43 ` Andy Shevchenko 2009-12-01 18:16 ` Ramirez Luna, Omar 1 sibling, 1 reply; 28+ messages in thread From: Andy Shevchenko @ 2009-12-01 6:43 UTC (permalink / raw) To: Omar Ramirez Luna; +Cc: linux-omap On Mon, Nov 30, 2009 at 11:54 PM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote: > Remove duplicate set of braces from if statement and reduce > indentation. > diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c > index af31831..96a5aa6 100644 > --- a/drivers/dsp/bridge/wmd/io_sm.c > +++ b/drivers/dsp/bridge/wmd/io_sm.c > @@ -115,7 +115,7 @@ struct IO_MGR { > /* private extnd proc info; mmu setup */ > struct MGR_PROCESSOREXTINFO extProcInfo; > struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ May be to fix commentary indentation? > - struct work_struct io_workq; /*workqueue */ > + struct work_struct io_workq; /*workqueue */ I didn't get why the space after /* still absent. > @@ -319,7 +321,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) > SYNC_DeleteCS(hIOMgr->hCSObj); /* Leak Fix. */ > /* Free this IO manager object: */ > MEM_FreeObject(hIOMgr); > - } else > + } else > status = DSP_EHANDLE; Probably } else { ... } would be better. (1) > @@ -609,7 +608,7 @@ func_cont1: > } > } > > - /* Copy remaining entries from CDB. All entries are 1 MB and should not > + /* Copy remaining entries from CDB. All entries are 1 MB and should not > * conflict with SHM entries on MPU or DSP side */ In previous hunks you fixed * ... */. Why not here? (2) > @@ -1002,15 +995,10 @@ void IO_DPC(IN OUT void *pRefData) > PrintDSPDebugTrace(pIOMgr); > } > #endif > - > -#ifndef DSP_TRACEBUF_DISABLED > - PrintDSPDebugTrace(pIOMgr); > -#endif > func_end: > return; No comments about this changes. (Intuitively I understand, but...) > @@ -1028,29 +1016,28 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) > } > - } else > + } else > /* Ensure that, if WMD didn't claim it, the IRQ is shared. */ > DBC_Ensure(hIOMgr->fSharedIRQ); The same as in (1). > @@ -1380,10 +1365,10 @@ static void NotifyChnlComplete(struct CHNL_OBJECT *pChnl, > !pChnl->pIOCompletions || !pChirp) > goto func_end; > > - /* Note: we signal the channel event only if the queue of IO > - * completions is empty. If it is not empty, the event is sure to be > - * signalled by the only IO completion list consumer: > - * WMD_CHNL_GetIOC(). */ > + /* Note: we signal the channel event only if the queue of IO > + * completions is empty. If it is not empty, the event is sure to be > + * signalled by the only IO completion list consumer: > + * WMD_CHNL_GetIOC(). */ The same as in (2). -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm 2009-12-01 6:43 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Andy Shevchenko @ 2009-12-01 18:16 ` Ramirez Luna, Omar 0 siblings, 0 replies; 28+ messages in thread From: Ramirez Luna, Omar @ 2009-12-01 18:16 UTC (permalink / raw) To: Andy Shevchenko; +Cc: linux-omap >From: Andy Shevchenko [mailto:andy.shevchenko@gmail.com] > >On Mon, Nov 30, 2009 at 11:54 PM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote: >> Remove duplicate set of braces from if statement and reduce >> indentation. > >> diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c >> index af31831..96a5aa6 100644 >> --- a/drivers/dsp/bridge/wmd/io_sm.c >> +++ b/drivers/dsp/bridge/wmd/io_sm.c >> @@ -115,7 +115,7 @@ struct IO_MGR { >> /* private extnd proc info; mmu setup */ >> struct MGR_PROCESSOREXTINFO extProcInfo; >> struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ >May be to fix commentary indentation? >> - struct work_struct io_workq; /*workqueue */ >> + struct work_struct io_workq; /*workqueue */ >I didn't get why the space after /* still absent. Removed on the next patch (trivial fix for multiline comments on io_sm) - struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ - struct work_struct io_workq; /*workqueue */ + struct CMM_OBJECT *hCmmMgr; /* Shared Mem Mngr */ + struct work_struct io_workq; /* workqueue */ > >> @@ -319,7 +321,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr) >> SYNC_DeleteCS(hIOMgr->hCSObj); /* Leak Fix. */ >> /* Free this IO manager object: */ >> MEM_FreeObject(hIOMgr); >> - } else >> + } else >> status = DSP_EHANDLE; >Probably } else { ... } would be better. (1) > Agree >> @@ -609,7 +608,7 @@ func_cont1: >> } >> } >> >> - /* Copy remaining entries from CDB. All entries are 1 MB and should not >> + /* Copy remaining entries from CDB. All entries are 1 MB and should not >> * conflict with SHM entries on MPU or DSP side */ >In previous hunks you fixed * ... */. Why not here? (2) trivial fix for multiline comments on io_sm, I tried to split the two patches because I thought there would be a lot of changes 0015-DSPBRIDGE-trivial-cleanup-and-indentation-for-io_sm.patch 0016-DSPBRIDGE-trivial-fix-for-multiline-comments-on-io_.patch But I guess I can join them into one patch and resend (btw fixed on patch 16) > >> @@ -1002,15 +995,10 @@ void IO_DPC(IN OUT void *pRefData) >> PrintDSPDebugTrace(pIOMgr); >> } >> #endif >> - >> -#ifndef DSP_TRACEBUF_DISABLED >> - PrintDSPDebugTrace(pIOMgr); >> -#endif >> func_end: >> return; >No comments about this changes. (Intuitively I understand, but...) > >> @@ -1028,29 +1016,28 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData) >> } >> - } else >> + } else >> /* Ensure that, if WMD didn't claim it, the IRQ is shared. */ >> DBC_Ensure(hIOMgr->fSharedIRQ); >The same as in (1). Agree > >> @@ -1380,10 +1365,10 @@ static void NotifyChnlComplete(struct CHNL_OBJECT *pChnl, >> !pChnl->pIOCompletions || !pChirp) >> goto func_end; >> >> - /* Note: we signal the channel event only if the queue of IO >> - * completions is empty. If it is not empty, the event is sure to be >> - * signalled by the only IO completion list consumer: >> - * WMD_CHNL_GetIOC(). */ >> + /* Note: we signal the channel event only if the queue of IO >> + * completions is empty. If it is not empty, the event is sure to be >> + * signalled by the only IO completion list consumer: >> + * WMD_CHNL_GetIOC(). */ >The same as in (2). > Fixed on patch 16, will join both of the patches and resend >-- >With Best Regards, >Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level 2009-11-30 21:54 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 10/20] DSPBRIDGE: checkpatch - braces not necessary for single statement blocks Omar Ramirez Luna @ 2009-12-01 3:57 ` Menon, Nishanth 1 sibling, 0 replies; 28+ messages in thread From: Menon, Nishanth @ 2009-12-01 3:57 UTC (permalink / raw) To: Ramirez Luna, Omar, linux-omap > From: Ramirez Luna, Omar > Sent: Monday, November 30, 2009 11:55 PM > To: linux-omap > Cc: Ramirez Luna, Omar; Menon, Nishanth > Subject: [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include > KERN_ facility level > > WARNING: printk() should include KERN_ facility level Any reason why we would like to stick with printk(KERN_ERR when we can use pr_err ? > > Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> > CC: Nishant Menon <nm@ti.com> > --- > arch/arm/plat-omap/include/dspbridge/dbc.h | 2 +- > arch/arm/plat-omap/include/dspbridge/gt.h | 2 +- > drivers/dsp/bridge/gen/_gt_para.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/plat-omap/include/dspbridge/dbc.h b/arch/arm/plat- > omap/include/dspbridge/dbc.h > index e9cb548..13b1ff6 100644 > --- a/arch/arm/plat-omap/include/dspbridge/dbc.h > +++ b/arch/arm/plat-omap/include/dspbridge/dbc.h > @@ -36,7 +36,7 @@ > > #define DBC_Assert(exp) \ > if (!(exp)) \ > - printk("%s, line %d: Assertion (" #exp ") failed.\n", \ > + printk(KERN_ERR "%s, line %d: Assertion (" #exp ") failed.\n", \ > __FILE__, __LINE__) > #define DBC_Require DBC_Assert /* Function Precondition. */ > #define DBC_Ensure DBC_Assert /* Function Postcondition. */ > diff --git a/arch/arm/plat-omap/include/dspbridge/gt.h b/arch/arm/plat- > omap/include/dspbridge/gt.h > index b43b1e7..c110234 100644 > --- a/arch/arm/plat-omap/include/dspbridge/gt.h > +++ b/arch/arm/plat-omap/include/dspbridge/gt.h > @@ -232,7 +232,7 @@ extern struct GT_Config _GT_params; > > #define GT_assert(mask, expr) \ > (!(expr) ? \ > - printk("assertion violation: %s, line %d\n", \ > + printk(KERN_ERR "assertion violation: %s, line %d\n", \ > __FILE__, __LINE__), NULL : NULL) > > #define GT_config(config) (_GT_params = *(config)) > diff --git a/drivers/dsp/bridge/gen/_gt_para.c > b/drivers/dsp/bridge/gen/_gt_para.c > index 9f8246b..dd22f77 100644 > --- a/drivers/dsp/bridge/gen/_gt_para.c > +++ b/drivers/dsp/bridge/gen/_gt_para.c > @@ -77,7 +77,7 @@ static void error(char *fmt, ...) > > va_end(va); > > - printk("ERROR: "); > + printk(KERN_ERR "ERROR: "); > printk(fmt, arg1, arg2, arg3, arg4, arg5, arg6); > > #if defined(DEBUG) || defined(DDSP_DEBUG_PRODUCT) > -- > 1.6.2.4 Regards, Nishanth Menon ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 2009-11-30 21:54 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 02/20] DSPBRIDGE: trivial license fix in tramp and tramp_table_c6000 Omar Ramirez Luna @ 2009-12-02 10:57 ` Felipe Contreras 2009-12-02 16:01 ` Ramirez Luna, Omar 1 sibling, 1 reply; 28+ messages in thread From: Felipe Contreras @ 2009-12-02 10:57 UTC (permalink / raw) To: Omar Ramirez Luna; +Cc: linux-omap, Artem Bityutskiy, Hiroshi Doyu On Mon, Nov 30, 2009 at 11:54 PM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote: > Prior to any further modification set the driver version to be 0.1 It should be the other way around; *after* the modifications have been merged, the version 0.1 would be released. Moreover, it would be nice to get some acknowledgement from Nokia developers that the branch is indeed correct. -- Felipe Contreras ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 2009-12-02 10:57 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Felipe Contreras @ 2009-12-02 16:01 ` Ramirez Luna, Omar 2009-12-05 14:20 ` Felipe Contreras 0 siblings, 1 reply; 28+ messages in thread From: Ramirez Luna, Omar @ 2009-12-02 16:01 UTC (permalink / raw) To: Felipe Contreras; +Cc: linux-omap, Artem Bityutskiy, Hiroshi Doyu >From: Felipe Contreras [mailto:felipe.contreras@gmail.com] > >On Mon, Nov 30, 2009 at 11:54 PM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote: >> Prior to any further modification set the driver version to be 0.1 > >It should be the other way around; *after* the modifications have been >merged,the version 0.1 would be released. Nope, version 0.2 will be once modifications are merged and branch is rebased to 2.6.32rc7 > Moreover, it would be nice >to get some acknowledgement from Nokia developers that the branch is >indeed correct. > It would be nice to get them but they are not needed. As always any bug reports are welcomed. >-- >Felipe Contreras Regards, Omar ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 2009-12-02 16:01 ` Ramirez Luna, Omar @ 2009-12-05 14:20 ` Felipe Contreras 0 siblings, 0 replies; 28+ messages in thread From: Felipe Contreras @ 2009-12-05 14:20 UTC (permalink / raw) To: Ramirez Luna, Omar; +Cc: linux-omap, Artem Bityutskiy, Hiroshi Doyu On Wed, Dec 2, 2009 at 6:01 PM, Ramirez Luna, Omar <omar.ramirez@ti.com> wrote: >>From: Felipe Contreras [mailto:felipe.contreras@gmail.com] >>It should be the other way around; *after* the modifications have been >>merged,the version 0.1 would be released. > > Nope, version 0.2 will be once modifications are merged and branch is rebased to 2.6.32rc7 There's many problems with the current dspbridge branch, for starters it doesn't work on the N900, nor beagleboard. Personally I would like 0.1 to work on both, and as discussed in an internal meeting I sent a proposal for 0.1 with an analysis I did on the current branch. >> Moreover, it would be nice >>to get some acknowledgement from Nokia developers that the branch is >>indeed correct. > > It would be nice to get them but they are not needed. As always any bug reports are welcomed. We care about the code quality and stability, and code-reviewing ensures that no regressions will sneak in. We reached some level of stability on the maemo branch, and have done extensive testing on the N900, it would be only sensible to have at least that same level of stability on 0.1. Currently there are many patches in the dspbridge branch that have never been reviewed by anybody outside TI, nor tested by Nokia, so I cannot trust that code, specially since it doesn't even work for me. To me the whole purpose of 0.1 is to have something we can all trust is "good", so NAK from me. -- Felipe Contreras ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 00/20] dspbridge cleanups 2009-11-30 21:54 [PATCH v2 00/20] dspbridge cleanups Omar Ramirez Luna 2009-11-30 21:54 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Omar Ramirez Luna @ 2009-12-01 6:49 ` Andy Shevchenko 2009-12-01 18:46 ` Ramirez Luna, Omar 1 sibling, 1 reply; 28+ messages in thread From: Andy Shevchenko @ 2009-12-01 6:49 UTC (permalink / raw) To: Omar Ramirez Luna Cc: linux-omap, Artem Bityutskiy, Felipe Balbi, Felipe Contreras, Hiroshi Doyu, Nishant Menon On Mon, Nov 30, 2009 at 11:54 PM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote: > arch/arm/plat-omap/include/dspbridge/list.h | 36 +- > drivers/dsp/bridge/services/list.c | 33 - Sorry, I missed patch that contains above changes. What they about? -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH v2 00/20] dspbridge cleanups 2009-12-01 6:49 ` [PATCH v2 00/20] dspbridge cleanups Andy Shevchenko @ 2009-12-01 18:46 ` Ramirez Luna, Omar 0 siblings, 0 replies; 28+ messages in thread From: Ramirez Luna, Omar @ 2009-12-01 18:46 UTC (permalink / raw) To: Andy Shevchenko Cc: linux-omap, Artem Bityutskiy, Felipe Balbi, Felipe Contreras, Hiroshi Doyu, Menon, Nishanth >-----Original Message----- >From: Andy Shevchenko [mailto:andy.shevchenko@gmail.com] >Sent: Tuesday, December 01, 2009 12:50 AM >To: Ramirez Luna, Omar >Cc: linux-omap; Artem Bityutskiy; Felipe Balbi; Felipe Contreras; Hiroshi Doyu; Menon, Nishanth >Subject: Re: [PATCH v2 00/20] dspbridge cleanups > >On Mon, Nov 30, 2009 at 11:54 PM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote: > >> arch/arm/plat-omap/include/dspbridge/list.h | 36 +- DSPBRIDGE: trivial file history cleanup for headers @@ -14,39 +17,6 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ - -/* - * ======== list.h ======== - * Purpose: - * Declarations of list management control structures and definitions - * of inline list management functions. - * - * Public Functions: - * LST_Create - * LST_Delete - * LST_Exit - * LST_First - * LST_GetHead - * LST_InitElem - * LST_Init - * LST_InsertBefore - * LST_IsEmpty - * LST_Next - * LST_PutTail - * LST_RemoveElem - * - * Notes: - * - *! Revision History - *! ================ - *! 10-Aug-2000 ag: Added LST_InsertBefore(). - *! 29-Oct-1999 kc: Cleaned up for code review. - *! 16-Aug-1997 cr: added explicit identifiers. - *! 10-Aug-1996 gp: Acquired from SMM for WinSPOX v.1.1; renamed identifiers. - *! 21-Oct-1994 dh4: Cleaned / commented for code review. - *! 08-Jun-1994 dh4: Converted to SPM (added extern "C"). - */ - #ifndef LIST_ #define LIST_ >> drivers/dsp/bridge/services/list.c | 33 - DSPBRIDGE: trivial file history cleanup for driver sources @@ -14,39 +14,6 @@ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ - -/* - * ======== listce.c ======== - * Purpose - * Provides standard circular list handling functions. - * - * Public Functions: - * LST_Create - * LST_Delete - * LST_Exit - * LST_First - * LST_GetHead - * LST_Init - * LST_InitElem - * LST_InsertBefore - * LST_Next - * LST_PutTail - * LST_RemoveElem - * - *! Revision History - *! ================ - *! 06-Mar-2002 jeh Don't set element self to NULL in LST_RemoveElem(). - *! 10-Aug-2000 ag: Added LST_InsertBefore(). - *! 03-Feb-2000 rr: Module init/exit is handled by SERVICES Init/Exit. - *! GT Changes. - *! 22-Nov-1999 kc: Added changes from code review. - *! 10-Aug-1999 kc: Based on wsx-c18. - *! 16-Jun-1997 gp: Removed unnecessary enabling/disabling of interrupts around - *! list manipulation code. - *! 22-Oct-1996 gp: Added LST_RemoveElem, and LST_First/LST_Next iterators. - *! 10-Aug-1996 gp: Acquired from SMM for WinSPOX v. 1.1; renamed identifiers. - */ - The original patch is way too big for the list about 250 KB, I just split those to modify header and sources separately, but they are still big. They can be found on the *temporary* experimental branch. http://dev.omapzoom.org/?p=tidspbridge/kernel-dspbridge.git;a=shortlog;h=refs/heads/experimental -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2009-12-05 14:20 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
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2009-11-30 21:54 [PATCH v2 00/20] dspbridge cleanups Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 02/20] DSPBRIDGE: trivial license fix in tramp and tramp_table_c6000 Omar Ramirez Luna
[not found] ` <1259618101-8972-4-git-send-email-omar.ramirez@ti.com>
[not found] ` <1259618101-8972-5-git-send-email-omar.ramirez@ti.com>
2009-11-30 21:54 ` [PATCH v2 05/20] DSPBRIDGE: checkpatch - space required after comma Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 06/20] DSPBRIDGE: checkpatch - space required before open parenthesis Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 07/20] DSPBRIDGE: checkpatch spacing and indentation Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 08/20] DSPBRIDGE: Checkpatch - line over 80 characters Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 10/20] DSPBRIDGE: checkpatch - braces not necessary for single statement blocks Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 11/20] DSPBRIDGE: checkpatch - struct file_operations should normally be const Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 12/20] DSPBRIDGE: checkpatch foo-should-be for pointers Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 13/20] DSPBRIDGE: Fix multiline macros to use do while Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 14/20] DSPBRIDGE: Use _IOxx macro to define ioctls Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 16/20] DSPBRIDGE: trivial fix for multiline comments on io_sm Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 17/20] DSPBRIDGE: Remove DPC, create, destroy and schedule wrappers Omar Ramirez Luna
2009-11-30 21:54 ` [PATCH v2 18/20] DSPBRIDGE: Remove main DPC wrapper for IO and MMUfault Omar Ramirez Luna
2009-11-30 21:55 ` [PATCH v2 19/20] DSPBRIDGE: Remove DPC module from SERVICES layer Omar Ramirez Luna
2009-11-30 21:55 ` [PATCH v2 20/20] DSPBRIDGE: Remove DPC object structure Omar Ramirez Luna
2009-11-30 22:52 ` [RESEND][PATCH " Ramirez Luna, Omar
2009-12-01 6:43 ` [PATCH v2 15/20] DSPBRIDGE: trivial cleanup and indentation for io_sm Andy Shevchenko
2009-12-01 18:16 ` Ramirez Luna, Omar
2009-12-01 3:57 ` [PATCH v2 09/20] DSPBRIDGE: checkpatch - printk() should include KERN_ facility level Menon, Nishanth
2009-12-02 10:57 ` [PATCH v2 01/20] DSPBRIDGE: driver version 0.1 Felipe Contreras
2009-12-02 16:01 ` Ramirez Luna, Omar
2009-12-05 14:20 ` Felipe Contreras
2009-12-01 6:49 ` [PATCH v2 00/20] dspbridge cleanups Andy Shevchenko
2009-12-01 18:46 ` Ramirez Luna, Omar
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