[PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Hari Kanigeri]

In order to enable TLB miss interrupt, the TWL should be
disabled. This patch provides the functionality to get the
MMU fault interrupt for a TLB miss in the cases where the
users are working with the locked TLB entries and with TWL
disabled.
New interface is added to disable twl and enable TLB miss
interrupt.

Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: Ramesh Gupta <grgupta@ti.com>
---
 arch/arm/mach-omap2/iommu2.c            |   13 +++++++++++++
 arch/arm/plat-omap/include/plat/iommu.h |    2 ++
 arch/arm/plat-omap/iommu.c              |   12 ++++++++++++
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index fcf4f4a..2e78cea 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -124,6 +124,18 @@ static void omap2_iommu_disable(struct iommu *obj)
 	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 }
 
+static void omap2_iommu_disable_twl(struct iommu *obj)
+{
+       u32 l = iommu_read_reg(obj, MMU_CNTL);
+
+       l &= ~MMU_CNTL_MASK;
+       l |= (MMU_CNTL_MMU_EN);
+       iommu_write_reg(obj, l, MMU_CNTL);
+
+       /* Enable TLB miss interrupt */
+       iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
+}
+
 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 {
 	int i;
@@ -306,6 +318,7 @@ static const struct iommu_functions omap2_iommu_ops = {
 
 	.enable		= omap2_iommu_enable,
 	.disable	= omap2_iommu_disable,
+	.disable_twl    = omap2_iommu_disable_twl,
 	.fault_isr	= omap2_iommu_fault_isr,
 
 	.tlb_read_cr	= omap2_tlb_read_cr,
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 0752af9..52a3852 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -80,6 +80,7 @@ struct iommu_functions {
 
 	int (*enable)(struct iommu *obj);
 	void (*disable)(struct iommu *obj);
+	void (*disable_twl)(struct iommu *obj);
 	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
 
 	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
 extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
 
 extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iommu_disable_twl(struct iommu *obj);
 extern void flush_iotlb_page(struct iommu *obj, u32 da);
 extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index b2b3937..d64a4d8 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -370,6 +370,18 @@ void flush_iotlb_all(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(flush_iotlb_all);
 
+/**
+ * Call this function if working with locked TLB entries and
+ * TWL disabled
+ */
+extern void iommu_disable_twl(struct iommu *obj)
+{
+	clk_enable(obj->clk);
+	arch_iommu->disable_twl(obj);
+	clk_disable(obj->clk);
+}
+EXPORT_SYMBOL_GPL(iommu_disable_twl);
+
 #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
 
 ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
-- 
1.7.0

Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Hiroshi DOYU]

Hi Hari,

From: ext Hari Kanigeri <h-kanigeri2@ti.com>
Subject: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt
Date: Tue, 18 May 2010 01:12:30 +0200

> In order to enable TLB miss interrupt, the TWL should be
> disabled. This patch provides the functionality to get the
> MMU fault interrupt for a TLB miss in the cases where the
> users are working with the locked TLB entries and with TWL
> disabled.

I want to keep leave the functionality to allow the locked TLB and
TWL enabled at the same time too. Is it still feasible with this?

> New interface is added to disable twl and enable TLB miss
> interrupt.
> 
> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
> Signed-off-by: Ramesh Gupta <grgupta@ti.com>
> ---
>  arch/arm/mach-omap2/iommu2.c            |   13 +++++++++++++
>  arch/arm/plat-omap/include/plat/iommu.h |    2 ++
>  arch/arm/plat-omap/iommu.c              |   12 ++++++++++++
>  3 files changed, 27 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
> index fcf4f4a..2e78cea 100644
> --- a/arch/arm/mach-omap2/iommu2.c
> +++ b/arch/arm/mach-omap2/iommu2.c
> @@ -124,6 +124,18 @@ static void omap2_iommu_disable(struct iommu *obj)
>  	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
>  }
>  
> +static void omap2_iommu_disable_twl(struct iommu *obj)
> +{
> +       u32 l = iommu_read_reg(obj, MMU_CNTL);
> +
> +       l &= ~MMU_CNTL_MASK;
> +       l |= (MMU_CNTL_MMU_EN);
> +       iommu_write_reg(obj, l, MMU_CNTL);
> +
> +       /* Enable TLB miss interrupt */
> +       iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
> +}
> +
>  static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
>  {
>  	int i;
> @@ -306,6 +318,7 @@ static const struct iommu_functions omap2_iommu_ops = {
>  
>  	.enable		= omap2_iommu_enable,
>  	.disable	= omap2_iommu_disable,
> +	.disable_twl    = omap2_iommu_disable_twl,
>  	.fault_isr	= omap2_iommu_fault_isr,
>  
>  	.tlb_read_cr	= omap2_tlb_read_cr,
> diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
> index 0752af9..52a3852 100644
> --- a/arch/arm/plat-omap/include/plat/iommu.h
> +++ b/arch/arm/plat-omap/include/plat/iommu.h
> @@ -80,6 +80,7 @@ struct iommu_functions {
>  
>  	int (*enable)(struct iommu *obj);
>  	void (*disable)(struct iommu *obj);
> +	void (*disable_twl)(struct iommu *obj);
>  	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
>  
>  	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
> @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
>  extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
>  
>  extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
> +extern void iommu_disable_twl(struct iommu *obj);
>  extern void flush_iotlb_page(struct iommu *obj, u32 da);
>  extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
>  extern void flush_iotlb_all(struct iommu *obj);
> diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
> index b2b3937..d64a4d8 100644
> --- a/arch/arm/plat-omap/iommu.c
> +++ b/arch/arm/plat-omap/iommu.c
> @@ -370,6 +370,18 @@ void flush_iotlb_all(struct iommu *obj)
>  }
>  EXPORT_SYMBOL_GPL(flush_iotlb_all);
>  
> +/**
> + * Call this function if working with locked TLB entries and
> + * TWL disabled
> + */

nitpick: It may be better to follow this for global func.

>From linux/Documentation/kernel-doc-nano-HOWTO.txt:
...
Example kernel-doc function comment:

/**
 * foobar() - short function description of foobar
 * @arg1:	Describe the first argument to foobar.
 * @arg2:	Describe the second argument to foobar.
 *		One can provide multiple line descriptions
 *		for arguments.
 *
 * A longer description, with more discussion of the function foobar()
 * that might be useful to those using or modifying it.  Begins with
 * empty comment line, and may include additional embedded empty
 * comment lines.
 *
 * The longer description can have multiple paragraphs.
 */


> +extern void iommu_disable_twl(struct iommu *obj)
 
extern?

> +{
> +	clk_enable(obj->clk);
> +	arch_iommu->disable_twl(obj);
> +	clk_disable(obj->clk);
> +}
> +EXPORT_SYMBOL_GPL(iommu_disable_twl);
> +
>  #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
>  
>  ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
> -- 
> 1.7.0
> 

RE: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Kanigeri, Hari]

Hi Hiroshi,


> -----Original Message-----
> From: Hiroshi DOYU [mailto:Hiroshi.DOYU@nokia.com]
> Sent: Tuesday, May 18, 2010 1:12 AM
> To: Kanigeri, Hari
> Cc: linux-omap@vger.kernel.org; tony@atomide.com; Gupta, Ramesh
> Subject: Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss
> interrupt
> 
> Hi Hari,
> 
> From: ext Hari Kanigeri <h-kanigeri2@ti.com>
> Subject: [PATCH 2/2] omap: iommu-add functionality to get TLB miss
> interrupt
> Date: Tue, 18 May 2010 01:12:30 +0200
> 
> > In order to enable TLB miss interrupt, the TWL should be
> > disabled. This patch provides the functionality to get the
> > MMU fault interrupt for a TLB miss in the cases where the
> > users are working with the locked TLB entries and with TWL
> > disabled.
> 
> I want to keep leave the functionality to allow the locked TLB and
> TWL enabled at the same time too. Is it still feasible with this?
> 

-- Absolutely. You can still work with locked TLB entries with TWL enabled.
My patch just provides the functionality where the users want to work only with locked TLB entries and with TWL disabled, and this is a valid use case. 

So basically, the user has to call this new function after calling iommu_get function if they want to have TWL disabled.

Reference: Check the MMU_IRQENABLE register definition in TRM for enabling TLB miss interrupt.

Please let me know if you need additional clarification.


> > New interface is added to disable twl and enable TLB miss
> > interrupt.
> >
> > Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
> > Signed-off-by: Ramesh Gupta <grgupta@ti.com>
> > ---
> >  arch/arm/mach-omap2/iommu2.c            |   13 +++++++++++++
> >  arch/arm/plat-omap/include/plat/iommu.h |    2 ++
> >  arch/arm/plat-omap/iommu.c              |   12 ++++++++++++
> >  3 files changed, 27 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
> > index fcf4f4a..2e78cea 100644
> > --- a/arch/arm/mach-omap2/iommu2.c
> > +++ b/arch/arm/mach-omap2/iommu2.c
> > @@ -124,6 +124,18 @@ static void omap2_iommu_disable(struct iommu *obj)
> >  	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
> >  }
> >
> > +static void omap2_iommu_disable_twl(struct iommu *obj)
> > +{
> > +       u32 l = iommu_read_reg(obj, MMU_CNTL);
> > +
> > +       l &= ~MMU_CNTL_MASK;
> > +       l |= (MMU_CNTL_MMU_EN);
> > +       iommu_write_reg(obj, l, MMU_CNTL);
> > +
> > +       /* Enable TLB miss interrupt */
> > +       iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
> > +}
> > +
> >  static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
> >  {
> >  	int i;
> > @@ -306,6 +318,7 @@ static const struct iommu_functions omap2_iommu_ops
> = {
> >
> >  	.enable		= omap2_iommu_enable,
> >  	.disable	= omap2_iommu_disable,
> > +	.disable_twl    = omap2_iommu_disable_twl,
> >  	.fault_isr	= omap2_iommu_fault_isr,
> >
> >  	.tlb_read_cr	= omap2_tlb_read_cr,
> > diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-
> omap/include/plat/iommu.h
> > index 0752af9..52a3852 100644
> > --- a/arch/arm/plat-omap/include/plat/iommu.h
> > +++ b/arch/arm/plat-omap/include/plat/iommu.h
> > @@ -80,6 +80,7 @@ struct iommu_functions {
> >
> >  	int (*enable)(struct iommu *obj);
> >  	void (*disable)(struct iommu *obj);
> > +	void (*disable_twl)(struct iommu *obj);
> >  	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
> >
> >  	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
> > @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct
> iotlb_entry *e);
> >  extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
> >
> >  extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
> > +extern void iommu_disable_twl(struct iommu *obj);
> >  extern void flush_iotlb_page(struct iommu *obj, u32 da);
> >  extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
> >  extern void flush_iotlb_all(struct iommu *obj);
> > diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
> > index b2b3937..d64a4d8 100644
> > --- a/arch/arm/plat-omap/iommu.c
> > +++ b/arch/arm/plat-omap/iommu.c
> > @@ -370,6 +370,18 @@ void flush_iotlb_all(struct iommu *obj)
> >  }
> >  EXPORT_SYMBOL_GPL(flush_iotlb_all);
> >
> > +/**
> > + * Call this function if working with locked TLB entries and
> > + * TWL disabled
> > + */
> 
> nitpick: It may be better to follow this for global func.
> 
> From linux/Documentation/kernel-doc-nano-HOWTO.txt:
> ...
> Example kernel-doc function comment:
> 
> /**
>  * foobar() - short function description of foobar
>  * @arg1:	Describe the first argument to foobar.
>  * @arg2:	Describe the second argument to foobar.
>  *		One can provide multiple line descriptions
>  *		for arguments.
>  *
>  * A longer description, with more discussion of the function foobar()
>  * that might be useful to those using or modifying it.  Begins with
>  * empty comment line, and may include additional embedded empty
>  * comment lines.
>  *
>  * The longer description can have multiple paragraphs.
>  */

-- Will update this in next patch revision.

> 
> 
> > +extern void iommu_disable_twl(struct iommu *obj)
> 
> extern?

Oops ! Copy paste error from header file.

> 
> > +{
> > +	clk_enable(obj->clk);
> > +	arch_iommu->disable_twl(obj);
> > +	clk_disable(obj->clk);
> > +}
> > +EXPORT_SYMBOL_GPL(iommu_disable_twl);
> > +
> >  #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
> >
> >  ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
> > --
> > 1.7.0
> >

Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Hiroshi DOYU]

From: "ext Kanigeri, Hari" <h-kanigeri2@ti.com>
Subject: RE: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt
Date: Tue, 18 May 2010 19:03:55 +0200

>> > diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-
>> omap/include/plat/iommu.h
>> > index 0752af9..52a3852 100644
>> > --- a/arch/arm/plat-omap/include/plat/iommu.h
>> > +++ b/arch/arm/plat-omap/include/plat/iommu.h
>> > @@ -80,6 +80,7 @@ struct iommu_functions {
>> >
>> >  	int (*enable)(struct iommu *obj);
>> >  	void (*disable)(struct iommu *obj);
>> > +	void (*disable_twl)(struct iommu *obj);
>> >  	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
>> >
>> >  	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
>> > @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct

Just one thought, isn't the following a little bit flexible?

-	void (*disable_twl)(struct iommu *obj);
+	void (*set_twl)(struct iommu *obj, int on);

Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Felipe Contreras]

On Wed, May 19, 2010 at 12:27 PM, Hiroshi DOYU <Hiroshi.DOYU@nokia.com> wrote:
> From: "ext Kanigeri, Hari" <h-kanigeri2@ti.com>
> Subject: RE: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt
> Date: Tue, 18 May 2010 19:03:55 +0200
>
>>> > diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-
>>> omap/include/plat/iommu.h
>>> > index 0752af9..52a3852 100644
>>> > --- a/arch/arm/plat-omap/include/plat/iommu.h
>>> > +++ b/arch/arm/plat-omap/include/plat/iommu.h
>>> > @@ -80,6 +80,7 @@ struct iommu_functions {
>>> >
>>> >    int (*enable)(struct iommu *obj);
>>> >    void (*disable)(struct iommu *obj);
>>> > +  void (*disable_twl)(struct iommu *obj);
>>> >    u32 (*fault_isr)(struct iommu *obj, u32 *ra);
>>> >
>>> >    void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
>>> > @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct
>
> Just one thought, isn't the following a little bit flexible?
>
> -       void (*disable_twl)(struct iommu *obj);
> +       void (*set_twl)(struct iommu *obj, int on);

Yeah, that would be better.

-- 
Felipe Contreras
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RE: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Kanigeri, Hari]

Hi Hiroshi,


> -----Original Message-----
> From: Hiroshi DOYU [mailto:Hiroshi.DOYU@nokia.com]
> Sent: Wednesday, May 19, 2010 4:28 AM
> To: Kanigeri, Hari
> Cc: linux-omap@vger.kernel.org; tony@atomide.com; Gupta, Ramesh
> Subject: Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss
> interrupt
> 
> From: "ext Kanigeri, Hari" <h-kanigeri2@ti.com>
> Subject: RE: [PATCH 2/2] omap: iommu-add functionality to get TLB miss
> interrupt
> Date: Tue, 18 May 2010 19:03:55 +0200
> 
> >> > diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-
> >> omap/include/plat/iommu.h
> >> > index 0752af9..52a3852 100644
> >> > --- a/arch/arm/plat-omap/include/plat/iommu.h
> >> > +++ b/arch/arm/plat-omap/include/plat/iommu.h
> >> > @@ -80,6 +80,7 @@ struct iommu_functions {
> >> >
> >> >  	int (*enable)(struct iommu *obj);
> >> >  	void (*disable)(struct iommu *obj);
> >> > +	void (*disable_twl)(struct iommu *obj);
> >> >  	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
> >> >
> >> >  	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
> >> > @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr,
> struct
> 
> Just one thought, isn't the following a little bit flexible?
> 
> -	void (*disable_twl)(struct iommu *obj);
> +	void (*set_twl)(struct iommu *obj, int on);

-- Probabaly if one want to toggle between enabling and disabling twl during run time. I agree with you about the change so that this can be flexible in future. I will make this change.
Thank you for your inputs.

Thank you,
Best regards,
Hari

[PATCH 0/2][v2] omap:iommu-enable TLB miss interrupt

[Hari Kanigeri]

The current iommu module doesn't provide the mechanism to get MMU fault on
TLB miss when working with locked TLB entries and TWL disabled.
To get the TLB miss interrupt, the TWL should be disabled.
This patch set provides the option to enable/disable TWL and to enable TLB miss
interrupt.

Based on Hiroshi, the initial patch set was revised to add more flexibility
to enable TWL.

Hari Kanigeri (2):
  omap: iommu-update irq mask to be specific about twl and tlb
  omap: iommu-add functionality to get TLB miss interrupt

 arch/arm/mach-omap2/iommu2.c            |   36 ++++++++++++++++++++++++-------
 arch/arm/plat-omap/include/plat/iommu.h |    2 +
 arch/arm/plat-omap/iommu.c              |   17 ++++++++++++++
 3 files changed, 47 insertions(+), 8 deletions(-)

[PATCH 1/2] omap: iommu-update irq mask to be specific about twl and tlb

[Hari Kanigeri]

Revise the IRQ mask definitions to handle the  MMU faults related
to TWL fault as well as TLB miss fault.

Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: Hiroshi Doyu <Hiroshi.DOYU@nokia.com>
---
 arch/arm/mach-omap2/iommu2.c |   12 ++++++++----
 1 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index e82da68..ebbdae2 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -44,9 +44,13 @@
 #define MMU_IRQ_EMUMISS		(1 << 2)
 #define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
 #define MMU_IRQ_TLBMISS		(1 << 0)
-#define MMU_IRQ_MASK	\
-	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
-	 MMU_IRQ_TRANSLATIONFAULT)
+
+#define __MMU_IRQ_FAULT		\
+	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
+#define MMU_IRQ_MASK		\
+	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
+#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
+#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
 
 /* MMU_CNTL */
 #define MMU_CNTL_SHIFT		1
@@ -96,7 +100,7 @@ static int omap2_iommu_enable(struct iommu *obj)
 	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
 	iommu_write_reg(obj, l, MMU_SYSCONFIG);
 
-	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
+	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
 	iommu_write_reg(obj, pa, MMU_TTB);
 
 	l = iommu_read_reg(obj, MMU_CNTL);
-- 
1.7.0

[PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Hari Kanigeri]

In order to enable TLB miss interrupt, the TWL should be
disabled. This patch provides the functionality to get the
MMU fault interrupt for a TLB miss in the cases where the
users are working with the locked TLB entries and with TWL
disabled.
New interface is added to select twl and to enable TLB miss
interrupt.

Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: Ramesh Gupta <grgupta@ti.com>
Signed-off-by: Hiroshi Doyu <Hiroshi.DOYU@nokia.com>
---
 arch/arm/mach-omap2/iommu2.c            |   26 +++++++++++++++++++++-----
 arch/arm/plat-omap/include/plat/iommu.h |    2 ++
 arch/arm/plat-omap/iommu.c              |   17 +++++++++++++++++
 3 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index ebbdae2..3cfe1c4 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -65,6 +65,25 @@
 	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
 	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
 
+
+static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+{
+	u32 l = iommu_read_reg(obj, MMU_CNTL);
+
+	if (on)
+		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
+	else
+		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
+
+	l &= ~MMU_CNTL_MASK;
+	if (on)
+		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
+	else
+		l |= (MMU_CNTL_MMU_EN);
+
+	iommu_write_reg(obj, l, MMU_CNTL);
+}
+
 static int omap2_iommu_enable(struct iommu *obj)
 {
 	u32 l, pa;
@@ -100,13 +119,9 @@ static int omap2_iommu_enable(struct iommu *obj)
 	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
 	iommu_write_reg(obj, l, MMU_SYSCONFIG);
 
-	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
 	iommu_write_reg(obj, pa, MMU_TTB);
 
-	l = iommu_read_reg(obj, MMU_CNTL);
-	l &= ~MMU_CNTL_MASK;
-	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
-	iommu_write_reg(obj, l, MMU_CNTL);
+	omap2_iommu_set_twl(obj, true);
 
 	return 0;
 }
@@ -304,6 +319,7 @@ static const struct iommu_functions omap2_iommu_ops = {
 
 	.enable		= omap2_iommu_enable,
 	.disable	= omap2_iommu_disable,
+	.set_twl	= omap2_iommu_set_twl,
 	.fault_isr	= omap2_iommu_fault_isr,
 
 	.tlb_read_cr	= omap2_tlb_read_cr,
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 0752af9..33c7d41 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -80,6 +80,7 @@ struct iommu_functions {
 
 	int (*enable)(struct iommu *obj);
 	void (*disable)(struct iommu *obj);
+	void (*set_twl)(struct iommu *obj, bool on);
 	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
 
 	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
 extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
 
 extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iommu_set_twl(struct iommu *obj, bool on);
 extern void flush_iotlb_page(struct iommu *obj, u32 da);
 extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index b2b3937..aa064e1 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(flush_iotlb_all);
 
+/**
+ * iommu_set_twl - enable/disable table walking logic
+ * @obj:	target iommu
+ * @on:		enable/disable
+ *
+ * Function used to enable/disable TWL. If one wants to work
+ * exclusively with locked TLB entries and receive notifications
+ * for TLB miss then call this function to disable TWL.
+ */
+void iommu_set_twl(struct iommu *obj, bool on)
+{
+	clk_enable(obj->clk);
+	arch_iommu->set_twl(obj, on);
+	clk_disable(obj->clk);
+}
+EXPORT_SYMBOL_GPL(iommu_set_twl);
+
 #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
 
 ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
-- 
1.7.0

Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Hiroshi DOYU]

Hi Hari,

From: ext Hari Kanigeri <h-kanigeri2@ti.com>
Subject: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt
Date: Thu, 20 May 2010 23:10:23 +0200

> In order to enable TLB miss interrupt, the TWL should be
> disabled. This patch provides the functionality to get the
> MMU fault interrupt for a TLB miss in the cases where the
> users are working with the locked TLB entries and with TWL
> disabled.
> New interface is added to select twl and to enable TLB miss
> interrupt.
> 
> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
> Signed-off-by: Ramesh Gupta <grgupta@ti.com>
> Signed-off-by: Hiroshi Doyu <Hiroshi.DOYU@nokia.com>
> ---
>  arch/arm/mach-omap2/iommu2.c            |   26 +++++++++++++++++++++-----
>  arch/arm/plat-omap/include/plat/iommu.h |    2 ++
>  arch/arm/plat-omap/iommu.c              |   17 +++++++++++++++++
>  3 files changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
> index ebbdae2..3cfe1c4 100644
> --- a/arch/arm/mach-omap2/iommu2.c
> +++ b/arch/arm/mach-omap2/iommu2.c
> @@ -65,6 +65,25 @@
>  	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
>  	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
>  
> +
> +static void omap2_iommu_set_twl(struct iommu *obj, bool on)
> +{
> +	u32 l = iommu_read_reg(obj, MMU_CNTL);
> +
> +	if (on)
> +		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
> +	else
> +		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
> +
> +	l &= ~MMU_CNTL_MASK;
> +	if (on)
> +		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
> +	else
> +		l |= (MMU_CNTL_MMU_EN);
> +
> +	iommu_write_reg(obj, l, MMU_CNTL);
> +}
> +
>  static int omap2_iommu_enable(struct iommu *obj)
>  {
>  	u32 l, pa;
> @@ -100,13 +119,9 @@ static int omap2_iommu_enable(struct iommu *obj)
>  	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
>  	iommu_write_reg(obj, l, MMU_SYSCONFIG);
>  
> -	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
>  	iommu_write_reg(obj, pa, MMU_TTB);
>  
> -	l = iommu_read_reg(obj, MMU_CNTL);
> -	l &= ~MMU_CNTL_MASK;
> -	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
> -	iommu_write_reg(obj, l, MMU_CNTL);
> +	omap2_iommu_set_twl(obj, true);
>  
>  	return 0;
>  }

nitpick: The function prefix "omap2_iommu_" are used to indicate that
this prefixed function belongs to "omap2_iommu_ops" to provide iommu
basic functionalities for the above layer. It's better to avoid to use
the prefixed function in the same prefixed ones, IOW, nested like
above, where "omap2_iommu_enable()" calls "omap2_iommu_set_twl()"
internally. It's can be considered as a violation of layer? Same to
"omap2_iommu_disable()".

> @@ -304,6 +319,7 @@ static const struct iommu_functions omap2_iommu_ops = {
>  
>  	.enable		= omap2_iommu_enable,
>  	.disable	= omap2_iommu_disable,
> +	.set_twl	= omap2_iommu_set_twl,
>  	.fault_isr	= omap2_iommu_fault_isr,
>  
>  	.tlb_read_cr	= omap2_tlb_read_cr,
> diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
> index 0752af9..33c7d41 100644
> --- a/arch/arm/plat-omap/include/plat/iommu.h
> +++ b/arch/arm/plat-omap/include/plat/iommu.h
> @@ -80,6 +80,7 @@ struct iommu_functions {
>  
>  	int (*enable)(struct iommu *obj);
>  	void (*disable)(struct iommu *obj);
> +	void (*set_twl)(struct iommu *obj, bool on);
>  	u32 (*fault_isr)(struct iommu *obj, u32 *ra);

This could be like the following, which also keeps the order of the
above "struct iommu_functions".

	Modified arch/arm/mach-omap2/iommu2.c
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 3cfe1c4..c87f662 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -66,7 +66,7 @@
 	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
 
 
-static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+static void __iommu_set_twl(struct iommu *obj, bool on)
 {
 	u32 l = iommu_read_reg(obj, MMU_CNTL);
 
@@ -121,7 +121,7 @@ static int omap2_iommu_enable(struct iommu *obj)
 
 	iommu_write_reg(obj, pa, MMU_TTB);
 
-	omap2_iommu_set_twl(obj, true);
+	__iommu_set_twl(obj, true);
 
 	return 0;
 }
@@ -137,6 +137,11 @@ static void omap2_iommu_disable(struct iommu *obj)
 	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 }
 
+static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+{
+	__iommu_set_twl(obj, on);
+}
+
 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 {
 	int i;

Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt

[Hiroshi DOYU]

[-- Attachment #1: Type: Text/Plain, Size: 2979 bytes --]

From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Subject: Re: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt
Date: Fri, 21 May 2010 08:45:14 +0300 (EEST)

> Hi Hari,
> 
> From: ext Hari Kanigeri <h-kanigeri2@ti.com>
> Subject: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt
> Date: Thu, 20 May 2010 23:10:23 +0200
> 
>> In order to enable TLB miss interrupt, the TWL should be
>> disabled. This patch provides the functionality to get the
>> MMU fault interrupt for a TLB miss in the cases where the
>> users are working with the locked TLB entries and with TWL
>> disabled.
>> New interface is added to select twl and to enable TLB miss
>> interrupt.
>> 
>> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
>> Signed-off-by: Ramesh Gupta <grgupta@ti.com>
>> Signed-off-by: Hiroshi Doyu <Hiroshi.DOYU@nokia.com>
>> ---
>>  arch/arm/mach-omap2/iommu2.c            |   26 +++++++++++++++++++++-----
>>  arch/arm/plat-omap/include/plat/iommu.h |    2 ++
>>  arch/arm/plat-omap/iommu.c              |   17 +++++++++++++++++
>>  3 files changed, 40 insertions(+), 5 deletions(-)
>> 
>> diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
>> index ebbdae2..3cfe1c4 100644
>> --- a/arch/arm/mach-omap2/iommu2.c
>> +++ b/arch/arm/mach-omap2/iommu2.c
>> @@ -65,6 +65,25 @@
>>  	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
>>  	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
>>  
>> +
>> +static void omap2_iommu_set_twl(struct iommu *obj, bool on)
>> +{
>> +	u32 l = iommu_read_reg(obj, MMU_CNTL);
>> +
>> +	if (on)
>> +		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
>> +	else
>> +		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
>> +
>> +	l &= ~MMU_CNTL_MASK;
>> +	if (on)
>> +		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
>> +	else
>> +		l |= (MMU_CNTL_MMU_EN);
>> +
>> +	iommu_write_reg(obj, l, MMU_CNTL);
>> +}
>> +
>>  static int omap2_iommu_enable(struct iommu *obj)
>>  {
>>  	u32 l, pa;
>> @@ -100,13 +119,9 @@ static int omap2_iommu_enable(struct iommu *obj)
>>  	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
>>  	iommu_write_reg(obj, l, MMU_SYSCONFIG);
>>  
>> -	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
>>  	iommu_write_reg(obj, pa, MMU_TTB);
>>  
>> -	l = iommu_read_reg(obj, MMU_CNTL);
>> -	l &= ~MMU_CNTL_MASK;
>> -	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
>> -	iommu_write_reg(obj, l, MMU_CNTL);
>> +	omap2_iommu_set_twl(obj, true);
>>  
>>  	return 0;
>>  }
> 
> nitpick: The function prefix "omap2_iommu_" are used to indicate that
> this prefixed function belongs to "omap2_iommu_ops" to provide iommu
> basic functionalities for the above layer. It's better to avoid to use
> the prefixed function in the same prefixed ones, IOW, nested like
> above, where "omap2_iommu_enable()" calls "omap2_iommu_set_twl()"
> internally. It's can be considered as a violation of layer? Same to
> "omap2_iommu_disable()".

For the case of "omap2_iommu_disable()", I attached the fix.

[-- Attachment #2: 0001-omap-iommu-move-iommu_disable-at-fault-to-the-above-.patch --]
[-- Type: Text/X-Patch, Size: 1599 bytes --]

>From 47994f0cb3ea3b3846f3b92bc9ab16f82d112d0b Mon Sep 17 00:00:00 2001
From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Date: Fri, 21 May 2010 12:17:32 +0300
Subject: [PATCH 1/1] omap iommu: move iommu_disable at fault to the above layer

The function prefix "omap2_iommu_" indicates that the prefixed
function belongs to "omap2_iommu_ops" to provide iommu basic
functionalities for the above layers. It's better to avoid the
prefixed function called in the same prefixed ones internally, like
nested here. Now "iommu_disable" is called just after fault_isr() in
the above layer. This is a little bit more sensible to keep the
consistency of module layers.

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
---
 arch/arm/mach-omap2/iommu2.c |    2 +-
 arch/arm/plat-omap/iommu.c   |    2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index ebbdae2..bcd816e 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -151,7 +151,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 	printk("\n");
 
 	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
-	omap2_iommu_disable(obj);
+
 	return stat;
 }
 
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 3381070..7245de4 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -783,6 +783,8 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
 	if (!stat)
 		return IRQ_HANDLED;
 
+	iommu_disable(obj);
+
 	iopgd = iopgd_offset(obj, da);
 
 	if (!iopgd_is_table(*iopgd)) {
-- 
1.7.1.rc1