* [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS
@ 2010-05-29 14:37 Thara Gopinath
2010-05-29 14:37 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Thara Gopinath
` (2 more replies)
0 siblings, 3 replies; 22+ messages in thread
From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw)
To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath
This patch series converts the OMAP Dual Mode Timer into a
platform driver. This involves using of hwmod structures and
omap_device layer for OMAP2/3/4 dmtimers and generic
linux platform device layer for OMAP1.
As a result of this patch series the dmtimer platform driver
resides in arch/arm/plat-omap directory and arch specific
implementations and device registerations reside in
arch/arm/mach-omap1 and arch/arm/mach-omap2 for OMAP1
and OMAP2 PLUS respectively.
This patch series has been compile tested for OMAP1 using
omap_1610_h2_defconfig, compile tested for OMAP2 using
omap3_defconfig and boot and sanity tested for OMAP3/OMAP4
again using omap3_defconfig. Boot testing has been done
on OMAP3430 SDP and OMAP4430 SDP boards. All testing has
been done on origin/origin/pm-wip/hwmods-omap4 branch off
Kevin Hilman's tree as these patches have dependencies on
runtime pm API's and OMAP4 autogenerated hwmod data base.
It would be great if somebody could test these patches on OMAP1
and OMAP2 platforms.
Thara Gopinath (9):
OMAP: Convert dual mode timer into a platform driver.
OMAP1: Dual mode timer device registration.
OMAP2/3/4 : Dual mode timer device registration.
OMAP2: Support for early device registration
OMAP2/3/4: Adding device names to dmtimer fclk nodes
OMAP3: Add hwmod data for OMAP3 dual mode timers.
OMAP2: Add hwmod data for OMAP2420 dual mode timers.
OMAP2: Add hwmod data for OMAP2430 dual mode timers.
OMAP4: Changing dmtimer1 fclk name
arch/arm/mach-omap1/Makefile | 1 +
arch/arm/mach-omap1/dmtimers.c | 148 +++++++
arch/arm/mach-omap1/timer32k.c | 3 -
arch/arm/mach-omap2/Makefile | 3 +-
arch/arm/mach-omap2/clock2420_data.c | 24 +-
arch/arm/mach-omap2/clock2430_data.c | 24 +-
arch/arm/mach-omap2/clock3xxx_data.c | 22 +-
arch/arm/mach-omap2/clock44xx_data.c | 24 +-
arch/arm/mach-omap2/dmtimers.c | 296 +++++++++++++
arch/arm/mach-omap2/dmtimers.h | 57 +++
arch/arm/mach-omap2/io.c | 16 +
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 619 +++++++++++++++++++++++++++-
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 619 +++++++++++++++++++++++++++-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 572 +++++++++++++++++++++++++-
arch/arm/mach-omap2/timer-gp.c | 2 -
arch/arm/plat-omap/dmtimer.c | 401 ++++++++-----------
arch/arm/plat-omap/include/plat/dmtimer.h | 12 +-
17 files changed, 2550 insertions(+), 293 deletions(-)
create mode 100644 arch/arm/mach-omap1/dmtimers.c
create mode 100644 arch/arm/mach-omap2/dmtimers.c
create mode 100644 arch/arm/mach-omap2/dmtimers.h
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver. 2010-05-29 14:37 [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 2/9] OMAP1: Dual mode timer device registration Thara Gopinath 2010-06-03 19:47 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Kevin Hilman 2010-05-30 22:11 ` [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Benoit Cousson 2010-06-01 9:37 ` Tony Lindgren 2 siblings, 2 replies; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch converts dual mode timer library into a platform driver. This essentially involves moving out interrupt and base address related info from plat-omap/dmtimer.c and making certain clock related functions platform data. This patch also initializes dm timer driver as a earlydriver. This is so that early timer devices required during system boot up can be initialized very early on. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/plat-omap/dmtimer.c | 401 ++++++++++++----------------- arch/arm/plat-omap/include/plat/dmtimer.h | 12 +- 2 files changed, 176 insertions(+), 237 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 4d99dfb..c17911d 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -10,6 +10,9 @@ * Copyright (C) 2009 Texas Instruments * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> * + * Copyright (C) 2010 Texas Instruments + * Converted to a platform driver - Thara Gopinath <thara@ti.com> + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -32,11 +35,14 @@ #include <linux/init.h> #include <linux/spinlock.h> #include <linux/errno.h> +#include <linux/err.h> #include <linux/list.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/slab.h> + #include <mach/hardware.h> #include <plat/dmtimer.h> #include <mach/irqs.h> @@ -153,136 +159,18 @@ struct omap_dm_timer { unsigned long phys_base; int irq; -#ifdef CONFIG_ARCH_OMAP2PLUS - struct clk *iclk, *fclk; -#endif void __iomem *io_base; unsigned reserved:1; unsigned enabled:1; unsigned posted:1; + unsigned is_intialized:1; + struct platform_device *pdev; }; -static int dm_timer_count; - -#ifdef CONFIG_ARCH_OMAP1 -static struct omap_dm_timer omap1_dm_timers[] = { - { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, - { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, - { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, - { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 }, - { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 }, - { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 }, - { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 }, - { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, -}; - -static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers); - -#else -#define omap1_dm_timers NULL -#define omap1_dm_timer_count 0 -#endif /* CONFIG_ARCH_OMAP1 */ - -#ifdef CONFIG_ARCH_OMAP2 -static struct omap_dm_timer omap2_dm_timers[] = { - { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, - { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, - { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, - { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 }, - { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 }, - { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 }, - { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 }, - { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 }, - { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 }, - { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, - { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, - { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, -}; - -static const char *omap2_dm_source_names[] __initdata = { - "sys_ck", - "func_32k_ck", - "alt_ck", - NULL -}; - -static struct clk *omap2_dm_source_clocks[3]; -static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers); - -#else -#define omap2_dm_timers NULL -#define omap2_dm_timer_count 0 -#define omap2_dm_source_names NULL -#define omap2_dm_source_clocks NULL -#endif /* CONFIG_ARCH_OMAP2 */ - -#ifdef CONFIG_ARCH_OMAP3 -static struct omap_dm_timer omap3_dm_timers[] = { - { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, - { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, - { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 }, - { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 }, - { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 }, - { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 }, - { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 }, - { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 }, - { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, - { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, - { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, - { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ }, -}; - -static const char *omap3_dm_source_names[] __initdata = { - "sys_ck", - "omap_32k_fck", - NULL -}; - -static struct clk *omap3_dm_source_clocks[2]; -static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers); - -#else -#define omap3_dm_timers NULL -#define omap3_dm_timer_count 0 -#define omap3_dm_source_names NULL -#define omap3_dm_source_clocks NULL -#endif /* CONFIG_ARCH_OMAP3 */ - -#ifdef CONFIG_ARCH_OMAP4 -static struct omap_dm_timer omap4_dm_timers[] = { - { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 }, - { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 }, - { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 }, - { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 }, - { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 }, - { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 }, - { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 }, - { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 }, - { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 }, - { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 }, - { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 }, - { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, -}; -static const char *omap4_dm_source_names[] __initdata = { - "sys_ck", - "omap_32k_fck", - NULL -}; -static struct clk *omap4_dm_source_clocks[2]; -static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers); - -#else -#define omap4_dm_timers NULL -#define omap4_dm_timer_count 0 -#define omap4_dm_source_names NULL -#define omap4_dm_source_clocks NULL -#endif /* CONFIG_ARCH_OMAP4 */ - +int omap_dm_timer_count; static struct omap_dm_timer *dm_timers; -static const char **dm_source_names; -static struct clk **dm_source_clocks; - static spinlock_t dm_timer_lock; +static int is_driver_init; /* * Reads timer registers in posted and non-posted mode. The posted mode bit @@ -368,7 +256,7 @@ struct omap_dm_timer *omap_dm_timer_request(void) int i; spin_lock_irqsave(&dm_timer_lock, flags); - for (i = 0; i < dm_timer_count; i++) { + for (i = 0; i < omap_dm_timer_count; i++) { if (dm_timers[i].reserved) continue; @@ -391,7 +279,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) unsigned long flags; spin_lock_irqsave(&dm_timer_lock, flags); - if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { + if (id <= 0 || id > omap_dm_timer_count || dm_timers[id-1].reserved) { spin_unlock_irqrestore(&dm_timer_lock, flags); printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", __FILE__, __LINE__, __func__, id); @@ -422,32 +310,32 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free); void omap_dm_timer_enable(struct omap_dm_timer *timer) { + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; + if (timer->enabled) return; -#ifdef CONFIG_ARCH_OMAP2PLUS - if (cpu_class_is_omap2()) { - clk_enable(timer->fclk); - clk_enable(timer->iclk); - } -#endif - + if (pdata->omap_dm_clk_enable) + pdata->omap_dm_clk_enable(timer->pdev); + else + dev_warn(&timer->pdev->dev, "%s: No enable fn registered\n", + __func__); timer->enabled = 1; } EXPORT_SYMBOL_GPL(omap_dm_timer_enable); void omap_dm_timer_disable(struct omap_dm_timer *timer) { + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; + if (!timer->enabled) return; -#ifdef CONFIG_ARCH_OMAP2PLUS - if (cpu_class_is_omap2()) { - clk_disable(timer->iclk); - clk_disable(timer->fclk); - } -#endif - + if (pdata->omap_dm_clk_disable) + pdata->omap_dm_clk_disable(timer->pdev); + else + dev_warn(&timer->pdev->dev, "%s: No disable fn registered\n", + __func__); timer->enabled = 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_disable); @@ -458,22 +346,26 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer) } EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); -#if defined(CONFIG_ARCH_OMAP1) - /** * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR + * valid only for OMAP1 * @inputmask: current value of idlect mask */ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) { int i; + if (cpu_class_is_omap2()) { + BUG(); + return 0; + } + /* If ARMXOR cannot be idled this function call is unnecessary */ if (!(inputmask & (1 << 1))) return inputmask; /* If any active timer is using ARMXOR return modified mask */ - for (i = 0; i < dm_timer_count; i++) { + for (i = 0; i < omap_dm_timer_count; i++) { u32 l; l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG); @@ -489,23 +381,18 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) } EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); -#else - struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) { - return timer->fclk; -} -EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; -__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) -{ - BUG(); + if (pdata->omap_dm_get_timer_clk) + return pdata->omap_dm_get_timer_clk(timer->pdev); - return 0; + dev_warn(&timer->pdev->dev, "%s: No get fclk clock fn registered\n", + __func__); + return ERR_PTR(-EINVAL); } -EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); - -#endif +EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); void omap_dm_timer_trigger(struct omap_dm_timer *timer) { @@ -531,64 +418,47 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (l & OMAP_TIMER_CTRL_ST) { + struct clk *timer_fclk; + l &= ~0x1; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); -#ifdef CONFIG_ARCH_OMAP2PLUS + + if (cpu_class_is_omap1()) + return; + /* Readback to make sure write has completed */ omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); /* * Wait for functional clock period x 3.5 to make sure that * timer is stopped */ - udelay(3500000 / clk_get_rate(timer->fclk) + 1); + timer_fclk = omap_dm_timer_get_fclk(timer); + if (IS_ERR(timer_fclk)) + dev_warn(&timer->pdev->dev, "%s: Unable to get" + "timer fclk!\n", __func__); + else + udelay(3500000 / clk_get_rate(timer_fclk) + 1); + /* Ack possibly pending interrupt */ omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, OMAP_TIMER_INT_OVERFLOW); -#endif } } EXPORT_SYMBOL_GPL(omap_dm_timer_stop); -#ifdef CONFIG_ARCH_OMAP1 - -int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) -{ - int n = (timer - dm_timers) << 1; - u32 l; - - l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); - l |= source << n; - omap_writel(l, MOD_CONF_CTRL_1); - - return 0; -} -EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); - -#else - int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { - int ret = -EINVAL; + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; - if (source < 0 || source >= 3) - return -EINVAL; - - clk_disable(timer->fclk); - ret = clk_set_parent(timer->fclk, dm_source_clocks[source]); - clk_enable(timer->fclk); - - /* - * When the functional clock disappears, too quick writes seem - * to cause an abort. XXX Is this still necessary? - */ - __delay(150000); + if (pdata->omap_dm_set_source_clk) + return pdata->omap_dm_set_source_clk(timer->pdev, source); - return ret; + dev_warn(&timer->pdev->dev, "%s: No set source clock fn registered\n", + __func__); + return -EINVAL; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); -#endif - void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int load) { @@ -716,7 +586,7 @@ int omap_dm_timers_active(void) { int i; - for (i = 0; i < dm_timer_count; i++) { + for (i = 0; i < omap_dm_timer_count; i++) { struct omap_dm_timer *timer; timer = &dm_timers[i]; @@ -733,61 +603,120 @@ int omap_dm_timers_active(void) } EXPORT_SYMBOL_GPL(omap_dm_timers_active); -int __init omap_dm_timer_init(void) +static int __devinit omap_dm_timer_data_init(void) { - struct omap_dm_timer *timer; - int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ + if (!is_driver_init) { + is_driver_init = 1; + spin_lock_init(&dm_timer_lock); + if (!omap_dm_timer_count) { + pr_err("%s: OMAP DMTIMER - Number of dmtimers in" + "the system not defined.Error!\n", __func__); + return -EINVAL; + } + dm_timers = kzalloc(omap_dm_timer_count * + sizeof(struct omap_dm_timer), GFP_KERNEL); + if (!dm_timers) { + pr_err("%s: OMAPP DMTIMER - Unable to allocate" + "dm_timers\n", __func__); + return -EINVAL; + } + } + return 0; +} - if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) - return -ENODEV; +static int __devinit omap_dm_timer_probe(struct platform_device *pdev) +{ + struct omap_dm_timer_plat_info *pdata = pdev->dev.platform_data; + struct resource *mem; + int id = pdev->id; + int ret; + + if (!pdata) { + dev_err(&pdev->dev, "%s: Timer device initialized without" + "platform data\n", __func__); + return -EINVAL; + } - spin_lock_init(&dm_timer_lock); - - if (cpu_class_is_omap1()) { - dm_timers = omap1_dm_timers; - dm_timer_count = omap1_dm_timer_count; - map_size = SZ_2K; - } else if (cpu_is_omap24xx()) { - dm_timers = omap2_dm_timers; - dm_timer_count = omap2_dm_timer_count; - dm_source_names = omap2_dm_source_names; - dm_source_clocks = omap2_dm_source_clocks; - } else if (cpu_is_omap34xx()) { - dm_timers = omap3_dm_timers; - dm_timer_count = omap3_dm_timer_count; - dm_source_names = omap3_dm_source_names; - dm_source_clocks = omap3_dm_source_clocks; - } else if (cpu_is_omap44xx()) { - dm_timers = omap4_dm_timers; - dm_timer_count = omap4_dm_timer_count; - dm_source_names = omap4_dm_source_names; - dm_source_clocks = omap4_dm_source_clocks; + ret = omap_dm_timer_data_init(); + if (ret) { + dev_err(&pdev->dev, "%s: Unable to do timer data init\n", + __func__); + return ret; } - if (cpu_class_is_omap2()) - for (i = 0; dm_source_names[i] != NULL; i++) - dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); + dm_timers[id].pdev = pdev; + /* + * Is the dmtimer already intialized as part of early init. If yes do + * nothing. Just return. + */ + if (dm_timers[id].is_intialized) + return 0; - if (cpu_is_omap243x()) - dm_timers[0].phys_base = 0x49018000; + dm_timers[id].is_intialized = 1; - for (i = 0; i < dm_timer_count; i++) { - timer = &dm_timers[i]; + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "%s: no mem resource\n", __func__); + return -ENODEV; + } - /* Static mapping, never released */ - timer->io_base = ioremap(timer->phys_base, map_size); - BUG_ON(!timer->io_base); - -#ifdef CONFIG_ARCH_OMAP2PLUS - if (cpu_class_is_omap2()) { - char clk_name[16]; - sprintf(clk_name, "gpt%d_ick", i + 1); - timer->iclk = clk_get(NULL, clk_name); - sprintf(clk_name, "gpt%d_fck", i + 1); - timer->fclk = clk_get(NULL, clk_name); - } -#endif + dm_timers[id].io_base = ioremap(mem->start, resource_size(mem)); + if (!dm_timers[id].io_base) { + dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); + ret = -ENOMEM; + goto exit_release_region; } + dm_timers[id].irq = platform_get_irq(pdev, 0); + if (dm_timers[id].irq < 0) { + dev_err(&pdev->dev, "%s: unable to get irq\n", __func__); + ret = dm_timers[id].irq; + goto exit_unmap; + } + dev_info(&pdev->dev, "Timer%d registered\n", pdev->id); + return 0; + +exit_unmap: + iounmap(dm_timers[id].io_base); +exit_release_region: + release_mem_region(mem->start, resource_size(mem)); + return ret; +} + +static int __devexit omap_dm_timer_remove(struct platform_device *pdev) +{ + struct resource *mem; + + iounmap(dm_timers[pdev->id].io_base); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(mem->start, resource_size(mem)); return 0; } + +static struct platform_driver omap_dmtimer_driver = { + .probe = omap_dm_timer_probe, + .remove = omap_dm_timer_remove, + .driver = { + .name = "dmtimer", + }, +}; + +static int __init omap_dm_timer_init(void) +{ + omap_dm_timer_data_init(); + return platform_driver_register(&omap_dmtimer_driver); +} + +static void __exit omap_dm_timer_exit(void) +{ + platform_driver_unregister(&omap_dmtimer_driver); +} + +early_platform_init("earlytimer", &omap_dmtimer_driver); +module_init(omap_dm_timer_init); +module_exit(omap_dm_timer_exit); + +MODULE_DESCRIPTION("OMAP DUAL MODE TIMER DRIVER"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 20f1054..0ab9fb3 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -29,6 +29,8 @@ #ifndef __ASM_ARCH_DMTIMER_H #define __ASM_ARCH_DMTIMER_H +#include <linux/platform_device.h> + /* clock sources */ #define OMAP_TIMER_SRC_SYS_CLK 0x00 #define OMAP_TIMER_SRC_32_KHZ 0x01 @@ -44,10 +46,18 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 +extern int omap_dm_timer_count; struct omap_dm_timer; struct clk; -int omap_dm_timer_init(void); +/* DMTIMER platform data structure */ +struct omap_dm_timer_plat_info { + void (*omap_dm_clk_enable) (struct platform_device *pdev); + void (*omap_dm_clk_disable) (struct platform_device *pdev); + int (*omap_dm_set_source_clk) + (struct platform_device *pdev, int source); + struct clk* (*omap_dm_get_timer_clk) (struct platform_device *pdev); +}; struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/9] OMAP1: Dual mode timer device registration. 2010-05-29 14:37 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 3/9] OMAP2/3/4 : " Thara Gopinath 2010-06-03 19:47 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Kevin Hilman 1 sibling, 1 reply; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch converts OMAP1 dual mode timers into platform devices and adds support for registering them through generic linux platform device layer. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap1/Makefile | 1 + arch/arm/mach-omap1/dmtimers.c | 148 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap1/timer32k.c | 3 - 3 files changed, 149 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-omap1/dmtimers.c diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index b6a537c..9abc6b7 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_MPU_TIMER) += time.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o +obj-$(CONFIG_OMAP_DM_TIMER) += dmtimers.o # Power Management obj-$(CONFIG_PM) += pm.o sleep.o diff --git a/arch/arm/mach-omap1/dmtimers.c b/arch/arm/mach-omap1/dmtimers.c new file mode 100644 index 0000000..4034fb7 --- /dev/null +++ b/arch/arm/mach-omap1/dmtimers.c @@ -0,0 +1,148 @@ +/** + * OMAP1 Dual-Mode Timers + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/slab.h> + +#include <mach/irqs.h> +#include <plat/dmtimer.h> + +#define OMAP1610_GPTIMER1_BASE 0xfffb1400 +#define OMAP1610_GPTIMER2_BASE 0xfffb1c00 +#define OMAP1610_GPTIMER3_BASE 0xfffb2400 +#define OMAP1610_GPTIMER4_BASE 0xfffb2c00 +#define OMAP1610_GPTIMER5_BASE 0xfffb3400 +#define OMAP1610_GPTIMER6_BASE 0xfffb3c00 +#define OMAP1610_GPTIMER7_BASE 0xfffb7400 +#define OMAP1610_GPTIMER8_BASE 0xfffbd400 + +#define OMAP1_DM_TIMER_COUNT 8 + +static int omap1_dm_timer_set_clk(struct platform_device *pdev, int source) +{ + int n = (pdev->id) << 1; + u32 l; + + l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); + l |= source << n; + omap_writel(l, MOD_CONF_CTRL_1); + + return 0; +} + +int __init omap1_dm_timer_init(void) +{ + int i = 0; + + if (!cpu_is_omap16xx()) + return 0; + + omap_dm_timer_count = OMAP1_DM_TIMER_COUNT; + + for (i = 0; i < omap_dm_timer_count; i++) { + struct platform_device *pdev; + struct omap_dm_timer_plat_info *pdata; + struct resource res[2]; + u32 base, irq; + int ret; + + switch (i) { + case 0: + base = OMAP1610_GPTIMER1_BASE; + irq = INT_1610_GPTIMER1; + break; + case 1: + base = OMAP1610_GPTIMER2_BASE; + irq = INT_1610_GPTIMER2; + break; + case 2: + base = OMAP1610_GPTIMER3_BASE; + irq = INT_1610_GPTIMER3; + break; + case 3: + base = OMAP1610_GPTIMER4_BASE; + irq = INT_1610_GPTIMER4; + break; + case 4: + base = OMAP1610_GPTIMER5_BASE; + irq = INT_1610_GPTIMER5; + break; + case 5: + base = OMAP1610_GPTIMER6_BASE; + irq = INT_1610_GPTIMER6; + break; + case 6: + base = OMAP1610_GPTIMER7_BASE; + irq = INT_1610_GPTIMER7; + break; + case 7: + base = OMAP1610_GPTIMER8_BASE; + irq = INT_1610_GPTIMER8; + break; + default: + /* Should never reach here */ + return -EINVAL; + } + + pdev = platform_device_alloc("dmtimer", i); + if (!pdev) { + pr_err("%s: Unable to device alloc for dmtimer%d\n", + __func__, i); + return -ENOMEM; + } + + memset(res, 0, 2 * sizeof(struct resource)); + res[0].start = base; + res[0].end = base + 0xff; + res[0].flags = IORESOURCE_MEM; + res[1].start = res[1].end = irq; + res[1].flags = IORESOURCE_IRQ; + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret) { + pr_err("%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_device_put; + } + + pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), + GFP_KERNEL); + if (!pdata) { + pr_err("%s: Unable to allocate pdata for %s%d\n", + __func__, pdev->name, pdev->id); + ret = -ENOMEM; + goto exit_device_put; + } + + pdata->omap_dm_set_source_clk = omap1_dm_timer_set_clk; + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { + pr_err("%s: Unable to add platform data for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_release_pdata; + } + ret = platform_device_add(pdev); + if (ret) { + pr_err("%s: Unable to add platform device for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_release_pdata; + } + continue; +exit_release_pdata: + kfree(pdata); +exit_device_put: + platform_device_put(pdev); + return ret; + } + return 0; +} +arch_initcall(omap1_dm_timer_init); diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 20cfbcc..6b8ab9b 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -183,9 +183,6 @@ static __init void omap_init_32k_timer(void) */ static void __init omap_timer_init(void) { -#ifdef CONFIG_OMAP_DM_TIMER - omap_dm_timer_init(); -#endif omap_init_32k_timer(); } -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. 2010-05-29 14:37 ` [PATCH 2/9] OMAP1: Dual mode timer device registration Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 4/9] OMAP2: Support for early " Thara Gopinath ` (3 more replies) 0 siblings, 4 replies; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch converts OMAP2/OMAP3/OMAP4 dual mode timers into platform devices using omap hwmod, omap device and runtime pm frameworks. This patch also allows GPTIMER1 and GPTIMER2 to be registered as early devices. This will allow GPTIMER1 to be registered as system timer very early on in the system boot up sequence. Later during normal plaform_device_register these are converted to normal platform device. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/dmtimers.c | 296 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/dmtimers.h | 57 ++++++++ arch/arm/mach-omap2/timer-gp.c | 2 - 4 files changed, 355 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-omap2/dmtimers.c create mode 100644 arch/arm/mach-omap2/dmtimers.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index dd3a24a..9299e4f 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,8 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o \ + dmtimers.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ diff --git a/arch/arm/mach-omap2/dmtimers.c b/arch/arm/mach-omap2/dmtimers.c new file mode 100644 index 0000000..6a2caf3 --- /dev/null +++ b/arch/arm/mach-omap2/dmtimers.c @@ -0,0 +1,296 @@ +/** + * OMAP2 Dual-Mode Timers + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/pm_runtime.h> + +#include <mach/irqs.h> +#include <plat/dmtimer.h> +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> + +#include "dmtimers.h" + +#define NO_EARLY_TIMERS 2 +#define OMAP2_DM_TIMER_COUNT 12 +#define OMAP3PLUS_DM_TIMER_COUNT 11 + +static char *omap2_dm_source_names[] __initdata = { + "sys_ck", + "func_32k_ck", + "alt_ck", + NULL +}; +static struct clk *omap2_dm_source_clocks[3]; + +static char *omap3_dm_source_names[] __initdata = { + "sys_ck", + "omap_32k_fck", + NULL +}; +static struct clk *omap3_dm_source_clocks[2]; + +static char *omap4_dm_source_names[] __initdata = { + "sys_ck", + "sys_32k_ck", + NULL +}; +static struct clk *omap4_dm_source_clocks[2]; + +static struct clk **omap_dm_source_clocks; + +static void omap2_dm_timer_enable(struct platform_device *pdev) +{ + + if (pm_runtime_get_sync(&pdev->dev)) + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", + __func__); +#ifndef CONFIG_PM_RUNTIME + if (omap_device_enable(pdev)) + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", + __func__); +#endif +} + +static void omap2_dm_timer_disable(struct platform_device *pdev) +{ + + if (pm_runtime_put_sync(&pdev->dev)) + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", + __func__); +#ifndef CONFIG_PM_RUNTIME + if (omap_device_idle(pdev)) + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", + __func__); +#endif +} + +static int omap2_dm_timer_set_src(struct platform_device *pdev, + struct clk *timer_clk, int source) +{ + int ret; + + if (IS_ERR(timer_clk)) { + dev_warn(&pdev->dev, "%s: Not able get the clock pointer\n", + __func__); + return -EINVAL; + } + + clk_disable(timer_clk); + ret = clk_set_parent(timer_clk, omap_dm_source_clocks[source]); + if (ret) + dev_warn(&pdev->dev, "%s: Not able to change the" + "fclk source\n", __func__); + + clk_enable(timer_clk); + /* + * When the functional clock disappears, too quick writes seem + * to cause an abort. XXX Is this still necessary? + */ + __delay(150000); + return ret; +} + +static int omap2_dm_timer_set_clk(struct platform_device *pdev, int source) +{ + struct clk *timer_clk = clk_get(&pdev->dev, "fck"); + + return omap2_dm_timer_set_src(pdev, timer_clk, source); +} + +static struct clk *omap2_dm_timer_get_fclk(struct platform_device *pdev) +{ + return clk_get(&pdev->dev, "fck"); +} + +/* API's to be used by early timer devices */ +static void __init omap2_dm_early_timer_enable(struct platform_device *pdev) +{ + if (omap_device_enable(pdev)) + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", + __func__); +} + +static void __init omap2_dm_early_timer_disable(struct platform_device *pdev) +{ + if (omap_device_idle(pdev)) + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", + __func__); +} + +static int __init omap2_dm_early_timer_set_clk(struct platform_device *pdev, + int source) +{ + struct omap_device *odev = to_omap_device(pdev); + + return omap2_dm_timer_set_src(pdev, odev->hwmods[0]->_clk, source); +} + +static struct clk __init *omap2_dm_early_timer_get_fclk + (struct platform_device *pdev) +{ + struct omap_device *odev = to_omap_device(pdev); + + return odev->hwmods[0]->_clk; +} + +/* One time initializations */ +static void __init omap2_dm_timer_setup(void) +{ + static int is_initialized; + char **src_clk_name; + int i; + + /* + * Check if setup has already been done as part of early init. + * If yes avoid doing it again. + */ + if (is_initialized) + return; + + if (cpu_is_omap24xx()) { + src_clk_name = omap2_dm_source_names; + omap_dm_source_clocks = omap2_dm_source_clocks; + } else if (cpu_is_omap34xx()) { + src_clk_name = omap3_dm_source_names; + omap_dm_source_clocks = omap3_dm_source_clocks; + } else if (cpu_is_omap44xx()) { + src_clk_name = omap4_dm_source_names; + omap_dm_source_clocks = omap4_dm_source_clocks; + } else { + pr_err("%s: Chip support not yet added\n", __func__); + return; + } + + /* Initialize the dmtimer src clocks */ + for (i = 0; src_clk_name[i] != NULL; i++) + omap_dm_source_clocks[i] = + clk_get(NULL, src_clk_name[i]); + + /* Number of dmtimers in the system */ + if (cpu_is_omap24xx()) + omap_dm_timer_count = OMAP2_DM_TIMER_COUNT; + else + omap_dm_timer_count = OMAP3PLUS_DM_TIMER_COUNT; + + is_initialized = 1; +} + +struct omap_device_pm_latency omap2_dmtimer_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + + }, +}; + +int __init omap2_get_early_timer_count(void) +{ + return NO_EARLY_TIMERS; +} + +void __init omap2_dm_timer_early_init(void) +{ + int i = 0; + char *name = "dmtimer"; + do { + struct omap_device *od; + struct omap_hwmod *oh; + int hw_mod_name_len = 16; + char oh_name[hw_mod_name_len]; + struct omap_dm_timer_plat_info *pdata; + + snprintf(oh_name, hw_mod_name_len, "timer%d", i + 1); + oh = omap_hwmod_lookup(oh_name); + if (!oh) + break; + + pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), + GFP_KERNEL); + if (!pdata) { + pr_err("%s: Unable to allocate pdata for %s:%s\n", + __func__, name, oh->name); + return; + } + + pdata->omap_dm_clk_enable = omap2_dm_early_timer_enable; + pdata->omap_dm_clk_disable = omap2_dm_early_timer_disable; + pdata->omap_dm_set_source_clk = omap2_dm_early_timer_set_clk; + pdata->omap_dm_get_timer_clk = omap2_dm_early_timer_get_fclk; + + od = omap_device_build(name, i, oh, pdata, sizeof(*pdata), + omap2_dmtimer_latency, + ARRAY_SIZE(omap2_dmtimer_latency), 1); + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", + __func__, name, oh->name); + kfree(pdata); + } + i++; + } while (i < NO_EARLY_TIMERS); + + omap2_dm_timer_setup(); + return; +} + +static int __init omap2_dm_timer_init_dev(struct omap_hwmod *oh, void *user) +{ + struct omap_device *od; + struct omap_dm_timer_plat_info *pdata; + static int i; + char *name = "dmtimer"; + + pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), GFP_KERNEL); + if (!pdata) { + pr_err("%s: Unable to allocate pdata for %s:%s\n", + __func__, name, oh->name); + return -ENOMEM; + } + + pdata->omap_dm_clk_enable = omap2_dm_timer_enable; + pdata->omap_dm_clk_disable = omap2_dm_timer_disable; + pdata->omap_dm_set_source_clk = omap2_dm_timer_set_clk; + pdata->omap_dm_get_timer_clk = omap2_dm_timer_get_fclk; + + od = omap_device_build(name, i, oh, pdata, sizeof(*pdata), + omap2_dmtimer_latency, + ARRAY_SIZE(omap2_dmtimer_latency), 0); + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", + __func__, name, oh->name); + kfree(pdata); + i++; + return 0; + } + pm_runtime_enable(&(od->pdev.dev)); + i++; + return 0; +} + +static int __init omap2_dm_timer_init(void) +{ + int ret; + + omap2_dm_timer_setup(); + + ret = omap_hwmod_for_each_by_class("timer_1ms", + omap2_dm_timer_init_dev, NULL); + + ret |= omap_hwmod_for_each_by_class("timer", + omap2_dm_timer_init_dev, NULL); + return ret; +} +arch_initcall(omap2_dm_timer_init); diff --git a/arch/arm/mach-omap2/dmtimers.h b/arch/arm/mach-omap2/dmtimers.h new file mode 100644 index 0000000..dbc2b9d --- /dev/null +++ b/arch/arm/mach-omap2/dmtimers.h @@ -0,0 +1,57 @@ +/** + * OMAP2 Dual-Mode Timers + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_DMTIMERS_H +#define __ASM_ARCH_DMTIMERS_H + +#define OMAP2420_GPTIMER1_BASE 0x48028000 +#define OMAP2430_GPTIMER1_BASE 0x49018000 +#define OMAP24XX_GPTIMER2_BASE 0x4802a000 +#define OMAP24XX_GPTIMER3_BASE 0x48078000 +#define OMAP24XX_GPTIMER4_BASE 0x4807a000 +#define OMAP24XX_GPTIMER5_BASE 0x4807c000 +#define OMAP24XX_GPTIMER6_BASE 0x4807e000 +#define OMAP24XX_GPTIMER7_BASE 0x48080000 +#define OMAP24XX_GPTIMER8_BASE 0x48082000 +#define OMAP24XX_GPTIMER9_BASE 0x48084000 +#define OMAP24XX_GPTIMER10_BASE 0x48086000 +#define OMAP24XX_GPTIMER11_BASE 0x48088000 +#define OMAP24XX_GPTIMER12_BASE 0x4808a000 + +#define OMAP34XX_GPTIMER1_BASE 0x48318000 +#define OMAP34XX_GPTIMER2_BASE 0x49032000 +#define OMAP34XX_GPTIMER3_BASE 0x49034000 +#define OMAP34XX_GPTIMER4_BASE 0x49036000 +#define OMAP34XX_GPTIMER5_BASE 0x49038000 +#define OMAP34XX_GPTIMER6_BASE 0x4903A000 +#define OMAP34XX_GPTIMER7_BASE 0x4903C000 +#define OMAP34XX_GPTIMER8_BASE 0x4903E000 +#define OMAP34XX_GPTIMER9_BASE 0x49040000 +#define OMAP34XX_GPTIMER10_BASE 0x48086000 +#define OMAP34XX_GPTIMER11_BASE 0x48088000 +#define OMAP34XX_GPTIMER12_BASE 0x48304000 + +#define OMAP44XX_GPTIMER1_BASE 0x4a318000 +#define OMAP44XX_GPTIMER2_BASE 0x48032000 +#define OMAP44XX_GPTIMER3_BASE 0x48034000 +#define OMAP44XX_GPTIMER4_BASE 0x48036000 +#define OMAP44XX_GPTIMER5_BASE 0x40138000 +#define OMAP44XX_GPTIMER6_BASE 0x4013a000 +#define OMAP44XX_GPTIMER7_BASE 0x4013a000 +#define OMAP44XX_GPTIMER8_BASE 0x4013e000 +#define OMAP44XX_GPTIMER9_BASE 0x4803e000 +#define OMAP44XX_GPTIMER10_BASE 0x48086000 +#define OMAP44XX_GPTIMER11_BASE 0x48088000 +#define OMAP44XX_GPTIMER12_BASE 0x4a320000 + +void __init omap2_dm_timer_early_init(void); +int __init omap2_get_early_timer_count(void); +#endif diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 74fbed8..d5f2ba7 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -231,8 +231,6 @@ static void __init omap2_gp_timer_init(void) twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); BUG_ON(!twd_base); #endif - omap_dm_timer_init(); - omap2_gp_clockevent_init(); omap2_gp_clocksource_init(); } -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/9] OMAP2: Support for early device registration 2010-05-29 14:37 ` [PATCH 3/9] OMAP2/3/4 : " Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 5/9] OMAP2/3/4: Adding device names to dmtimer fclk nodes Thara Gopinath 2010-06-03 23:19 ` [PATCH 4/9] OMAP2: Support for early device registration Kevin Hilman 2010-05-30 23:02 ` [PATCH 3/9] OMAP2/3/4 : Dual mode timer " Benoit Cousson ` (2 subsequent siblings) 3 siblings, 2 replies; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch adds a new API in the common boot up sequence to register early drivers and probe for early devices. This API can be used by any early device to register itself. This patch also adds support to register "earlytimer" drivers and probe for any associated devices that are registered as early devices. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/io.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3bf1cb4..edf1146 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -23,6 +23,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/omapfb.h> +#include <linux/platform_device.h> #include <asm/tlb.h> @@ -47,6 +48,8 @@ #include "clockdomains.h" #include <plat/omap_hwmod.h> +#include "dmtimers.h" + /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. @@ -304,6 +307,16 @@ static int __init _omap2_init_reprogram_sdrc(void) return v; } +static void __init omap_init_early_devices(void) +{ + int timer_count; + + early_platform_driver_register_all("earlytimer"); + timer_count = omap2_get_early_timer_count(); + early_platform_driver_probe("earlytimer", timer_count, 0); + /* Add any other early devices needed here */ +} + void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { @@ -341,4 +354,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, _omap2_init_reprogram_sdrc(); } gpmc_init(); + omap2_dm_timer_early_init(); + /* Call the probe for all early devices */ + omap_init_early_devices(); } -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/9] OMAP2/3/4: Adding device names to dmtimer fclk nodes 2010-05-29 14:37 ` [PATCH 4/9] OMAP2: Support for early " Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 6/9] OMAP3: Add hwmod data for OMAP3 dual mode timers Thara Gopinath 2010-06-03 23:19 ` [PATCH 4/9] OMAP2: Support for early device registration Kevin Hilman 1 sibling, 1 reply; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch adds device name info to OMAP2/3/4 dmtimer fclk nodes so that the fclk nodes can be retrieved by doing a clk_get with the corresponding device pointers. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/clock2420_data.c | 24 ++++++++++++------------ arch/arm/mach-omap2/clock2430_data.c | 24 ++++++++++++------------ arch/arm/mach-omap2/clock3xxx_data.c | 22 +++++++++++----------- arch/arm/mach-omap2/clock44xx_data.c | 22 +++++++++++----------- 4 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index d932b14..e1fb85e 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1765,29 +1765,29 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), /* general l4 interface ck, multi-parent functional clk */ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), + CLK("dmtimer.0", "fck", &gpt1_fck, CK_242X), CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), + CLK("dmtimer.1", "fck", &gpt2_fck, CK_242X), CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), + CLK("dmtimer.2", "fck", &gpt3_fck, CK_242X), CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), + CLK("dmtimer.3", "fck", &gpt4_fck, CK_242X), CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), + CLK("dmtimer.4", "fck", &gpt5_fck, CK_242X), CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), + CLK("dmtimer.5", "fck", &gpt6_fck, CK_242X), CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), + CLK("dmtimer.6", "fck", &gpt7_fck, CK_242X), CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), + CLK("dmtimer.7", "gpt8_fck", &gpt8_fck, CK_242X), CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), + CLK("dmtimer.8", "fck", &gpt9_fck, CK_242X), CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), + CLK("dmtimer.9", "fck", &gpt10_fck, CK_242X), CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), + CLK("dmtimer.10", "fck", &gpt11_fck, CK_242X), CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), + CLK("dmtimer.11", "fck", &gpt12_fck, CK_242X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 0438b6e..e574b2c 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1851,29 +1851,29 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), /* general l4 interface ck, multi-parent functional clk */ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), + CLK("dmtimer.0", "fck", &gpt1_fck, CK_243X), CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), + CLK("dmtimer.1", "fck", &gpt2_fck, CK_243X), CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), + CLK("dmtimer.2", "fck", &gpt3_fck, CK_243X), CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), + CLK("dmtimer.3", "fck", &gpt4_fck, CK_243X), CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), + CLK("dmtimer.4", "fck", &gpt5_fck, CK_243X), CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), + CLK("dmtimer.5", "fck", &gpt6_fck, CK_243X), CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), + CLK("dmtimer.6", "fck", &gpt7_fck, CK_243X), CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), + CLK("dmtimer.7", "fck", &gpt8_fck, CK_243X), CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), + CLK("dmtimer.8", "fck", &gpt9_fck, CK_243X), CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), + CLK("dmtimer.9", "fck", &gpt10_fck, CK_243X), CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), + CLK("dmtimer.10", "fck", &gpt11_fck, CK_243X), CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), + CLK("dmtimer.11", "fck", &gpt12_fck, CK_243X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 9cba556..7a317d8 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3319,8 +3319,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "modem_fck", &modem_fck, CK_343X), CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), + CLK("dmtimer.9", "fck", &gpt10_fck, CK_3XXX), + CLK("dmtimer.10", "fck", &gpt11_fck, CK_3XXX), CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), @@ -3405,7 +3405,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), + CLK("dmtimer.0", "fck", &gpt1_fck, CK_3XXX), CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), @@ -3420,14 +3420,14 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), + CLK("dmtimer.1", "fck", &gpt2_fck, CK_3XXX), + CLK("dmtimer.2", "fck", &gpt3_fck, CK_3XXX), + CLK("dmtimer.3", "fck", &gpt4_fck, CK_3XXX), + CLK("dmtimer.4", "fck", &gpt5_fck, CK_3XXX), + CLK("dmtimer.4", "fck", &gpt6_fck, CK_3XXX), + CLK("dmtimer.5", "fck", &gpt7_fck, CK_3XXX), + CLK("dmtimer.7", "fck", &gpt8_fck, CK_3XXX), + CLK("dmtimer.8", "fck", &gpt9_fck, CK_3XXX), CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index a1b4cae..2edc0a3 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -2575,17 +2575,17 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), + CLK("dmtimer.0", "fck", &gpt1_fck, CK_443X), + CLK("dmtimer.9", "fck", &gpt10_fck, CK_443X), + CLK("dmtimer.10", "fck", &gpt11_fck, CK_443X), + CLK("dmtimer.1", "fck", &gpt2_fck, CK_443X), + CLK("dmtimer.2", "fck", &gpt3_fck, CK_443X), + CLK("dmtimer.3", "fck", &gpt4_fck, CK_443X), + CLK("dmtimer.4", "fck", &gpt5_fck, CK_443X), + CLK("dmtimer.5", "fck", &gpt6_fck, CK_443X), + CLK("dmtimer.6", "fck", &gpt7_fck, CK_443X), + CLK("dmtimer.7", "fck", &gpt8_fck, CK_443X), + CLK("dmtimer.8", "fck", &gpt9_fck, CK_443X), CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/9] OMAP3: Add hwmod data for OMAP3 dual mode timers. 2010-05-29 14:37 ` [PATCH 5/9] OMAP2/3/4: Adding device names to dmtimer fclk nodes Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 7/9] OMAP2: Add hwmod data for OMAP2420 " Thara Gopinath 0 siblings, 1 reply; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch adds OMAP3 dual mode timers hwmod structures. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 572 +++++++++++++++++++++++++++- 1 files changed, 571 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 39b0c0e..597b0a1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -19,8 +19,8 @@ #include <plat/dma.h> #include "omap_hwmod_common_data.h" - #include "prm-regbits-34xx.h" +#include "dmtimers.h" /* * OMAP3xxx hardware module integration data @@ -80,6 +80,17 @@ static struct omap_hwmod omap3xxx_l3_hwmod = { }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_gptimer1_hwmod; +static struct omap_hwmod omap3xxx_gptimer2_hwmod; +static struct omap_hwmod omap3xxx_gptimer3_hwmod; +static struct omap_hwmod omap3xxx_gptimer4_hwmod; +static struct omap_hwmod omap3xxx_gptimer5_hwmod; +static struct omap_hwmod omap3xxx_gptimer6_hwmod; +static struct omap_hwmod omap3xxx_gptimer7_hwmod; +static struct omap_hwmod omap3xxx_gptimer8_hwmod; +static struct omap_hwmod omap3xxx_gptimer9_hwmod; +static struct omap_hwmod omap3xxx_gptimer10_hwmod; +static struct omap_hwmod omap3xxx_gptimer11_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -88,6 +99,50 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* GPTIMER10 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer10_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER10_BASE, + .pa_end = OMAP34XX_GPTIMER10_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__gptimer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_gptimer10_hwmod, + .clk = "gpt10_ick", + .addr = omap3xxx_gptimer10_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer10_slaves[] = { + &omap3xxx_l4_core__gptimer10, +}; + +/* GPTIMER11 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer11_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER11_BASE, + .pa_end = OMAP34XX_GPTIMER11_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__gptimer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_gptimer11_hwmod, + .clk = "gpt11_ick", + .addr = omap3xxx_gptimer11_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer11_slaves[] = { + &omap3xxx_l4_core__gptimer11, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3__l4_core, @@ -96,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, + &omap3xxx_l4_core__gptimer10, + &omap3xxx_l4_core__gptimer11, }; /* L4 CORE */ @@ -109,6 +166,182 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* GPTIMER2 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer2_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER2_BASE, + .pa_end = OMAP34XX_GPTIMER2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer2_hwmod, + .clk = "gpt2_ick", + .addr = omap3xxx_gptimer2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer2_slaves[] = { + &omap3xxx_l4_per__gptimer2, +}; + +/* GPTIMER3 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer3_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER3_BASE, + .pa_end = OMAP34XX_GPTIMER3_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer3_hwmod, + .clk = "gpt3_ick", + .addr = omap3xxx_gptimer3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer3_slaves[] = { + &omap3xxx_l4_per__gptimer3, +}; + +/* GPTIMER4 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer4_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER4_BASE, + .pa_end = OMAP34XX_GPTIMER4_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer4_hwmod, + .clk = "gpt4_ick", + .addr = omap3xxx_gptimer4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer4_slaves[] = { + &omap3xxx_l4_per__gptimer4, +}; + +/* GPTIMER5 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer5_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER5_BASE, + .pa_end = OMAP34XX_GPTIMER5_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer5_hwmod, + .clk = "gpt5_ick", + .addr = omap3xxx_gptimer5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer5_slaves[] = { + &omap3xxx_l4_per__gptimer5, +}; + +/* GPTIMER6 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer6_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER6_BASE, + .pa_end = OMAP34XX_GPTIMER6_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer6_hwmod, + .clk = "gpt6_ick", + .addr = omap3xxx_gptimer6_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer6_slaves[] = { + &omap3xxx_l4_per__gptimer6, +}; + +/* GPTIMER7 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer7_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER7_BASE, + .pa_end = OMAP34XX_GPTIMER7_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer7_hwmod, + .clk = "gpt7_ick", + .addr = omap3xxx_gptimer7_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer7_slaves[] = { + &omap3xxx_l4_per__gptimer7, +}; + +/* GPTIMER8 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer8_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER8_BASE, + .pa_end = OMAP34XX_GPTIMER8_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer8_hwmod, + .clk = "gpt8_ick", + .addr = omap3xxx_gptimer8_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer8_slaves[] = { + &omap3xxx_l4_per__gptimer8, +}; + +/* GPTIMER9 <- L4_PER interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer9_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER9_BASE, + .pa_end = OMAP34XX_GPTIMER9_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gptimer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gptimer9_hwmod, + .clk = "gpt9_ick", + .addr = omap3xxx_gptimer9_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer9_slaves[] = { + &omap3xxx_l4_per__gptimer9, +}; + /* Slave interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { &omap3xxx_l3__l4_per, @@ -116,6 +349,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { /* Master interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { + &omap3xxx_l4_per__gptimer2, + &omap3xxx_l4_per__gptimer3, + &omap3xxx_l4_per__gptimer4, + &omap3xxx_l4_per__gptimer5, + &omap3xxx_l4_per__gptimer6, + &omap3xxx_l4_per__gptimer7, + &omap3xxx_l4_per__gptimer8, + &omap3xxx_l4_per__gptimer9, }; /* L4 PER */ @@ -129,6 +370,28 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* GPTIMER1 <- L4_WKUP interface */ +static struct omap_hwmod_addr_space omap3xxx_gptimer1_addrs[] = { + { + .pa_start = OMAP34XX_GPTIMER1_BASE, + .pa_end = OMAP34XX_GPTIMER1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gptimer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gptimer1_hwmod, + .clk = "gpt1_ick", + .addr = omap3xxx_gptimer1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gptimer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gptimer1_slaves[] = { + &omap3xxx_l4_wkup__gptimer1, +}; + /* Slave interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { &omap3xxx_l4_core__l4_wkup, @@ -136,6 +399,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { /* Master interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { + &omap3xxx_l4_wkup__gptimer1, }; /* L4 WKUP */ @@ -164,12 +428,318 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_sysc, +}; + +/* TIMER 1 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer1_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER1, }, +}; + +static struct omap_hwmod omap3xxx_gptimer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap3xxx_gptimer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT1_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer1_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + + +/* TIMER 2 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer2_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER2, }, +}; + +static struct omap_hwmod omap3xxx_gptimer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap3xxx_gptimer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT2_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer2_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER3 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer3_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER3, }, +}; + +static struct omap_hwmod omap3xxx_gptimer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap3xxx_gptimer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT3_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer3_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER 4 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer4_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER4, }, +}; + +static struct omap_hwmod omap3xxx_gptimer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap3xxx_gptimer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT4_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer4_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER 5 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer5_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER5, }, +}; + +static struct omap_hwmod omap3xxx_gptimer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap3xxx_gptimer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT5_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer5_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER 6 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer6_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER6, }, +}; + +static struct omap_hwmod omap3xxx_gptimer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap3xxx_gptimer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT6_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer6_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER 7 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer7_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER7, }, +}; + +static struct omap_hwmod omap3xxx_gptimer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap3xxx_gptimer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT7_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT7_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer7_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER 8 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer8_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER8, }, +}; + +static struct omap_hwmod omap3xxx_gptimer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap3xxx_gptimer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT8_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT8_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer8_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* TIMER 9 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer9_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER9, }, +}; + +static struct omap_hwmod omap3xxx_gptimer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap3xxx_gptimer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT9_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_GPT9_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer9_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + + +/* TIMER 10 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer10_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER10, }, +}; + +static struct omap_hwmod omap3xxx_gptimer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap3xxx_gptimer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT10_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer10_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + + +/* TIMER 11 */ +static struct omap_hwmod_irq_info omap3xxx_gptimer11_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER11, }, +}; + +static struct omap_hwmod omap3xxx_gptimer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap3xxx_gptimer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gptimer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT11_SHIFT, + }, + }, + .slaves = omap3xxx_gptimer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gptimer11_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_hwmod, &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, + &omap3xxx_gptimer1_hwmod, + &omap3xxx_gptimer2_hwmod, + &omap3xxx_gptimer3_hwmod, + &omap3xxx_gptimer4_hwmod, + &omap3xxx_gptimer5_hwmod, + &omap3xxx_gptimer6_hwmod, + &omap3xxx_gptimer7_hwmod, + &omap3xxx_gptimer8_hwmod, + &omap3xxx_gptimer9_hwmod, + &omap3xxx_gptimer10_hwmod, + &omap3xxx_gptimer11_hwmod, NULL, }; -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 7/9] OMAP2: Add hwmod data for OMAP2420 dual mode timers. 2010-05-29 14:37 ` [PATCH 6/9] OMAP3: Add hwmod data for OMAP3 dual mode timers Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 8/9] OMAP2: Add hwmod data for OMAP2430 " Thara Gopinath 0 siblings, 1 reply; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch adds OMAP2420 dual mode timers hwmod structures. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 619 +++++++++++++++++++++++++++- 1 files changed, 618 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index e5530c5..475f2e8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -17,7 +17,7 @@ #include <plat/dma.h> #include "omap_hwmod_common_data.h" - +#include "dmtimers.h" #include "prm-regbits-24xx.h" /* @@ -32,6 +32,18 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_l3_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_gptimer1_hwmod; +static struct omap_hwmod omap2420_gptimer2_hwmod; +static struct omap_hwmod omap2420_gptimer3_hwmod; +static struct omap_hwmod omap2420_gptimer4_hwmod; +static struct omap_hwmod omap2420_gptimer5_hwmod; +static struct omap_hwmod omap2420_gptimer6_hwmod; +static struct omap_hwmod omap2420_gptimer7_hwmod; +static struct omap_hwmod omap2420_gptimer8_hwmod; +static struct omap_hwmod omap2420_gptimer9_hwmod; +static struct omap_hwmod omap2420_gptimer10_hwmod; +static struct omap_hwmod omap2420_gptimer11_hwmod; +static struct omap_hwmod omap2420_gptimer12_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3__l4_core = { @@ -77,6 +89,248 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* GPTIMER2 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer2_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER2_BASE, + .pa_end = OMAP24XX_GPTIMER2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2420_gptimer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer2_slaves[] = { + &omap2420_l4_core__gptimer2, +}; + +/* GPTIMER3 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer3_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER3_BASE, + .pa_end = OMAP24XX_GPTIMER3_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2420_gptimer3_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer3_slaves[] = { + &omap2420_l4_core__gptimer3, +}; + +/* GPTIMER4 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer4_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER4_BASE, + .pa_end = OMAP24XX_GPTIMER4_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer4 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2420_gptimer4_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer4_slaves[] = { + &omap2420_l4_core__gptimer4, +}; + +/* GPTIMER5 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer5_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER5_BASE, + .pa_end = OMAP24XX_GPTIMER5_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer5 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2420_gptimer5_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer5_slaves[] = { + &omap2420_l4_core__gptimer5, +}; + +/* GPTIMER6 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer6_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER6_BASE, + .pa_end = OMAP24XX_GPTIMER6_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer6 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2420_gptimer6_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer6_slaves[] = { + &omap2420_l4_core__gptimer6, +}; + +/* GPTIMER7 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer7_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER7_BASE, + .pa_end = OMAP24XX_GPTIMER7_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer7 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2420_gptimer7_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer7_slaves[] = { + &omap2420_l4_core__gptimer7, +}; + +/* GPTIMER8 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer8_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER8_BASE, + .pa_end = OMAP24XX_GPTIMER8_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer8 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2420_gptimer8_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer8_slaves[] = { + &omap2420_l4_core__gptimer8, +}; + +/* GPTIMER9 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer9_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER9_BASE, + .pa_end = OMAP24XX_GPTIMER9_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer9 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2420_gptimer9_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer9_slaves[] = { + &omap2420_l4_core__gptimer9, +}; + +/* GPTIMER10 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer10_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER10_BASE, + .pa_end = OMAP24XX_GPTIMER10_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer10 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2420_gptimer10_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer10_slaves[] = { + &omap2420_l4_core__gptimer10, +}; + +/* GPTIMER11 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer11_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER11_BASE, + .pa_end = OMAP24XX_GPTIMER11_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer11 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2420_gptimer11_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer11_slaves[] = { + &omap2420_l4_core__gptimer11, +}; + +/* GPTIMER12 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2420_gptimer12_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER12_BASE, + .pa_end = OMAP24XX_GPTIMER12_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__gptimer12 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_gptimer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2420_gptimer12_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer12_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer12_slaves[] = { + &omap2420_l4_core__gptimer12, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3__l4_core, @@ -85,6 +339,17 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2420_l4_core__l4_wkup, + &omap2420_l4_core__gptimer2, + &omap2420_l4_core__gptimer3, + &omap2420_l4_core__gptimer4, + &omap2420_l4_core__gptimer5, + &omap2420_l4_core__gptimer6, + &omap2420_l4_core__gptimer7, + &omap2420_l4_core__gptimer8, + &omap2420_l4_core__gptimer9, + &omap2420_l4_core__gptimer10, + &omap2420_l4_core__gptimer11, + &omap2420_l4_core__gptimer12, }; /* L4 CORE */ @@ -98,6 +363,28 @@ static struct omap_hwmod omap2420_l4_core_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* GPTIMER1 <- L4_WKUP interface */ +static struct omap_hwmod_addr_space omap2420_gptimer1_addrs[] = { + { + .pa_start = OMAP2420_GPTIMER1_BASE, + .pa_end = OMAP2420_GPTIMER1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__gptimer1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_gptimer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_gptimer1_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_gptimer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_gptimer1_slaves[] = { + &omap2420_l4_wkup__gptimer1, +}; + /* Slave interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { &omap2420_l4_core__l4_wkup, @@ -105,6 +392,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { /* Master interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { + &omap2420_l4_wkup__gptimer1, }; /* L4 WKUP */ @@ -133,11 +421,340 @@ static struct omap_hwmod omap2420_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_timer_hwmod_class = { + .name = "timer", + .sysc = &omap2420_timer_sysc, +}; + +/* TIMER 1 */ +static struct omap_hwmod_irq_info omap2420_gptimer1_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER1, }, +}; + +static struct omap_hwmod omap2420_gptimer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2420_gptimer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT1_SHIFT, + }, + }, + .slaves = omap2420_gptimer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer1_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 2 */ +static struct omap_hwmod_irq_info omap2420_gptimer2_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER2, }, +}; + +static struct omap_hwmod omap2420_gptimer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2420_gptimer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT2_SHIFT, + }, + }, + .slaves = omap2420_gptimer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer2_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 3 */ +static struct omap_hwmod_irq_info omap2420_gptimer3_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER3, }, +}; + +static struct omap_hwmod omap2420_gptimer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2420_gptimer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT3_SHIFT, + }, + }, + .slaves = omap2420_gptimer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer3_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 4 */ +static struct omap_hwmod_irq_info omap2420_gptimer4_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER4, }, +}; + +static struct omap_hwmod omap2420_gptimer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2420_gptimer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT4_SHIFT, + }, + }, + .slaves = omap2420_gptimer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer4_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 5 */ +static struct omap_hwmod_irq_info omap2420_gptimer5_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER5, }, +}; + +static struct omap_hwmod omap2420_gptimer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2420_gptimer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT5_SHIFT, + }, + }, + .slaves = omap2420_gptimer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer5_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 6 */ +static struct omap_hwmod_irq_info omap2420_gptimer6_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER6, }, +}; + +static struct omap_hwmod omap2420_gptimer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2420_gptimer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT6_SHIFT, + }, + }, + .slaves = omap2420_gptimer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer6_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 7 */ +static struct omap_hwmod_irq_info omap2420_gptimer7_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER7, }, +}; + +static struct omap_hwmod omap2420_gptimer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2420_gptimer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT7_SHIFT, + }, + }, + .slaves = omap2420_gptimer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer7_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 8 */ +static struct omap_hwmod_irq_info omap2420_gptimer8_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER8, }, +}; + +static struct omap_hwmod omap2420_gptimer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2420_gptimer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT8_SHIFT, + }, + }, + .slaves = omap2420_gptimer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer8_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 9 */ +static struct omap_hwmod_irq_info omap2420_gptimer9_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER9, }, +}; + +static struct omap_hwmod omap2420_gptimer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2420_gptimer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT9_SHIFT, + }, + }, + .slaves = omap2420_gptimer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer9_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 10 */ +static struct omap_hwmod_irq_info omap2420_gptimer10_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER10, }, +}; + +static struct omap_hwmod omap2420_gptimer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2420_gptimer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT10_SHIFT, + }, + }, + .slaves = omap2420_gptimer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer10_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 11 */ +static struct omap_hwmod_irq_info omap2420_gptimer11_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER11, }, +}; + +static struct omap_hwmod omap2420_gptimer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2420_gptimer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT11_SHIFT, + }, + }, + .slaves = omap2420_gptimer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer11_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* TIMER 12 */ +static struct omap_hwmod_irq_info omap2420_gptimer12_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER12, }, +}; + +static struct omap_hwmod omap2420_gptimer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2420_gptimer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_gptimer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT12_SHIFT, + }, + }, + .slaves = omap2420_gptimer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_gptimer12_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, + &omap2420_gptimer1_hwmod, + &omap2420_gptimer2_hwmod, + &omap2420_gptimer3_hwmod, + &omap2420_gptimer4_hwmod, + &omap2420_gptimer5_hwmod, + &omap2420_gptimer6_hwmod, + &omap2420_gptimer7_hwmod, + &omap2420_gptimer8_hwmod, + &omap2420_gptimer9_hwmod, + &omap2420_gptimer10_hwmod, + &omap2420_gptimer11_hwmod, + &omap2420_gptimer12_hwmod, NULL, }; -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 8/9] OMAP2: Add hwmod data for OMAP2430 dual mode timers. 2010-05-29 14:37 ` [PATCH 7/9] OMAP2: Add hwmod data for OMAP2420 " Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 2010-05-29 14:37 ` [PATCH 9/9] OMAP4: Changing dmtimer1 fclk name Thara Gopinath 0 siblings, 1 reply; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch adds OMAP2430 dual mode timers hwmod structures. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 619 +++++++++++++++++++++++++++- 1 files changed, 618 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0852d95..56d9694 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -17,7 +17,7 @@ #include <plat/dma.h> #include "omap_hwmod_common_data.h" - +#include "dmtimers.h" #include "prm-regbits-24xx.h" /* @@ -32,6 +32,18 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_l3_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_gptimer1_hwmod; +static struct omap_hwmod omap2430_gptimer2_hwmod; +static struct omap_hwmod omap2430_gptimer3_hwmod; +static struct omap_hwmod omap2430_gptimer4_hwmod; +static struct omap_hwmod omap2430_gptimer5_hwmod; +static struct omap_hwmod omap2430_gptimer6_hwmod; +static struct omap_hwmod omap2430_gptimer7_hwmod; +static struct omap_hwmod omap2430_gptimer8_hwmod; +static struct omap_hwmod omap2430_gptimer9_hwmod; +static struct omap_hwmod omap2430_gptimer10_hwmod; +static struct omap_hwmod omap2430_gptimer11_hwmod; +static struct omap_hwmod omap2430_gptimer12_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3__l4_core = { @@ -79,6 +91,248 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* GPTIMER2 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer2_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER2_BASE, + .pa_end = OMAP24XX_GPTIMER2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2430_gptimer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer2_slaves[] = { + &omap2430_l4_core__gptimer2, +}; + +/* GPTIMER3 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer3_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER3_BASE, + .pa_end = OMAP24XX_GPTIMER3_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2430_gptimer3_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer3_slaves[] = { + &omap2430_l4_core__gptimer3, +}; + +/* GPTIMER4 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer4_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER4_BASE, + .pa_end = OMAP24XX_GPTIMER4_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2430_gptimer4_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer4_slaves[] = { + &omap2430_l4_core__gptimer4, +}; + +/* GPTIMER5 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer5_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER5_BASE, + .pa_end = OMAP24XX_GPTIMER5_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2430_gptimer5_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer5_slaves[] = { + &omap2430_l4_core__gptimer5, +}; + +/* GPTIMER6 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer6_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER6_BASE, + .pa_end = OMAP24XX_GPTIMER6_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer6 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2430_gptimer6_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer6_slaves[] = { + &omap2430_l4_core__gptimer6, +}; + +/* GPTIMER7 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer7_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER7_BASE, + .pa_end = OMAP24XX_GPTIMER7_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer7 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2430_gptimer7_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer7_slaves[] = { + &omap2430_l4_core__gptimer7, +}; + +/* GPTIMER8 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer8_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER8_BASE, + .pa_end = OMAP24XX_GPTIMER8_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer8 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2430_gptimer8_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer8_slaves[] = { + &omap2430_l4_core__gptimer8, +}; + +/* GPTIMER9 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer9_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER9_BASE, + .pa_end = OMAP24XX_GPTIMER9_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer9 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2430_gptimer9_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer9_slaves[] = { + &omap2430_l4_core__gptimer9, +}; + +/* GPTIMER10 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer10_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER10_BASE, + .pa_end = OMAP24XX_GPTIMER10_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer10 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2430_gptimer10_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer10_slaves[] = { + &omap2430_l4_core__gptimer10, +}; + +/* GPTIMER11 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer11_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER11_BASE, + .pa_end = OMAP24XX_GPTIMER11_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer11 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2430_gptimer11_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer11_slaves[] = { + &omap2430_l4_core__gptimer11, +}; + +/* GPTIMER12 <- L4_CORE interface */ +static struct omap_hwmod_addr_space omap2430_gptimer12_addrs[] = { + { + .pa_start = OMAP24XX_GPTIMER12_BASE, + .pa_end = OMAP24XX_GPTIMER12_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gptimer12 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gptimer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2430_gptimer12_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer12_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer12_slaves[] = { + &omap2430_l4_core__gptimer12, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3__l4_core, @@ -87,6 +341,17 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { &omap2430_l4_core__l4_wkup, + &omap2430_l4_core__gptimer2, + &omap2430_l4_core__gptimer3, + &omap2430_l4_core__gptimer4, + &omap2430_l4_core__gptimer5, + &omap2430_l4_core__gptimer6, + &omap2430_l4_core__gptimer7, + &omap2430_l4_core__gptimer8, + &omap2430_l4_core__gptimer9, + &omap2430_l4_core__gptimer10, + &omap2430_l4_core__gptimer11, + &omap2430_l4_core__gptimer12, }; /* L4 CORE */ @@ -100,6 +365,28 @@ static struct omap_hwmod omap2430_l4_core_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* GPTIMER1 <- L4_WKUP interface */ +static struct omap_hwmod_addr_space omap2430_gptimer1_addrs[] = { + { + .pa_start = OMAP2430_GPTIMER1_BASE, + .pa_end = OMAP2430_GPTIMER1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gptimer1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gptimer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2430_gptimer1_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_gptimer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_gptimer1_slaves[] = { + &omap2430_l4_wkup__gptimer1, +}; + /* Slave interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { &omap2430_l4_core__l4_wkup, @@ -107,6 +394,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { /* Master interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { + &omap2430_l4_wkup__gptimer1, }; /* L4 WKUP */ @@ -135,11 +423,340 @@ static struct omap_hwmod omap2430_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_timer_hwmod_class = { + .name = "timer", + .sysc = &omap2430_timer_sysc, +}; + +/* TIMER 1 */ +static struct omap_hwmod_irq_info omap2430_gptimer1_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER1, }, +}; + +static struct omap_hwmod omap2430_gptimer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2430_gptimer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT1_SHIFT, + }, + }, + .slaves = omap2430_gptimer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer1_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 2 */ +static struct omap_hwmod_irq_info omap2430_gptimer2_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER2, }, +}; + +static struct omap_hwmod omap2430_gptimer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2430_gptimer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT2_SHIFT, + }, + }, + .slaves = omap2430_gptimer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer2_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 3 */ +static struct omap_hwmod_irq_info omap2430_gptimer3_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER3, }, +}; + +static struct omap_hwmod omap2430_gptimer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2430_gptimer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT3_SHIFT, + }, + }, + .slaves = omap2430_gptimer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer3_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 4 */ +static struct omap_hwmod_irq_info omap2430_gptimer4_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER4, }, +}; + +static struct omap_hwmod omap2430_gptimer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2430_gptimer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT4_SHIFT, + }, + }, + .slaves = omap2430_gptimer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer4_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 5 */ +static struct omap_hwmod_irq_info omap2430_gptimer5_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER5, }, +}; + +static struct omap_hwmod omap2430_gptimer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2430_gptimer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT5_SHIFT, + }, + }, + .slaves = omap2430_gptimer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer5_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 6 */ +static struct omap_hwmod_irq_info omap2430_gptimer6_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER6, }, +}; + +static struct omap_hwmod omap2430_gptimer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2430_gptimer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT6_SHIFT, + }, + }, + .slaves = omap2430_gptimer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer6_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 7 */ +static struct omap_hwmod_irq_info omap2430_gptimer7_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER7, }, +}; + +static struct omap_hwmod omap2430_gptimer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2430_gptimer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT7_SHIFT, + }, + }, + .slaves = omap2430_gptimer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer7_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 8 */ +static struct omap_hwmod_irq_info omap2430_gptimer8_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER8, }, +}; + +static struct omap_hwmod omap2430_gptimer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2430_gptimer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT8_SHIFT, + }, + }, + .slaves = omap2430_gptimer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer8_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 9 */ +static struct omap_hwmod_irq_info omap2430_gptimer9_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER9, }, +}; + +static struct omap_hwmod omap2430_gptimer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2430_gptimer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT9_SHIFT, + }, + }, + .slaves = omap2430_gptimer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer9_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 10 */ +static struct omap_hwmod_irq_info omap2430_gptimer10_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER10, }, +}; + +static struct omap_hwmod omap2430_gptimer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2430_gptimer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT10_SHIFT, + }, + }, + .slaves = omap2430_gptimer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer10_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 11 */ +static struct omap_hwmod_irq_info omap2430_gptimer11_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER11, }, +}; + +static struct omap_hwmod omap2430_gptimer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2430_gptimer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT11_SHIFT, + }, + }, + .slaves = omap2430_gptimer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer11_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* TIMER 12 */ +static struct omap_hwmod_irq_info omap2430_gptimer12_mpu_irqs[] = { + { .irq = INT_24XX_GPTIMER12, }, +}; + +static struct omap_hwmod omap2430_gptimer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2430_gptimer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_gptimer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPT12_SHIFT, + }, + }, + .slaves = omap2430_gptimer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gptimer12_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, + &omap2430_gptimer1_hwmod, + &omap2430_gptimer2_hwmod, + &omap2430_gptimer3_hwmod, + &omap2430_gptimer4_hwmod, + &omap2430_gptimer5_hwmod, + &omap2430_gptimer6_hwmod, + &omap2430_gptimer7_hwmod, + &omap2430_gptimer8_hwmod, + &omap2430_gptimer9_hwmod, + &omap2430_gptimer10_hwmod, + &omap2430_gptimer11_hwmod, + &omap2430_gptimer12_hwmod, NULL, }; -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 9/9] OMAP4: Changing dmtimer1 fclk name 2010-05-29 14:37 ` [PATCH 8/9] OMAP2: Add hwmod data for OMAP2430 " Thara Gopinath @ 2010-05-29 14:37 ` Thara Gopinath 0 siblings, 0 replies; 22+ messages in thread From: Thara Gopinath @ 2010-05-29 14:37 UTC (permalink / raw) To: linux-omap; +Cc: khilman, tony, sawant, Thara Gopinath This patch changes the dmtimer1 fclk name so that it is in sync with the autogenerated OMAP4 hwmod database.Without this change this patch series will not boot on OMAP4. This is a temporary hack patch till a proper cleanup of OMAP4 clock database is done. Signed-off-by: Thara Gopinath <thara@ti.com> --- arch/arm/mach-omap2/clock44xx_data.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 2edc0a3..23540ea 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1526,7 +1526,7 @@ static const struct clksel dmt1_clk_mux_sel[] = { * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention */ static struct clk gpt1_fck = { - .name = "gpt1_fck", + .name = "timer1_fck", .parent = &sys_clkin_ck, .clksel = dmt1_clk_mux_sel, .init = &omap2_init_clksel_parent, -- 1.7.0.rc1.33.g07cf0f ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 4/9] OMAP2: Support for early device registration 2010-05-29 14:37 ` [PATCH 4/9] OMAP2: Support for early " Thara Gopinath 2010-05-29 14:37 ` [PATCH 5/9] OMAP2/3/4: Adding device names to dmtimer fclk nodes Thara Gopinath @ 2010-06-03 23:19 ` Kevin Hilman 1 sibling, 0 replies; 22+ messages in thread From: Kevin Hilman @ 2010-06-03 23:19 UTC (permalink / raw) To: Thara Gopinath; +Cc: linux-omap, tony, sawant Thara Gopinath <thara@ti.com> writes: > This patch adds a new API in the common boot up sequence to register > early drivers and probe for early devices. This API can be used by any > early device to register itself. > This patch also adds support to register "earlytimer" drivers and > probe for any associated devices that are registered as early devices. > > Signed-off-by: Thara Gopinath <thara@ti.com> Personally, I'd rather see the earlytimer registers/probes contained in the timer code itself. Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. 2010-05-29 14:37 ` [PATCH 3/9] OMAP2/3/4 : " Thara Gopinath 2010-05-29 14:37 ` [PATCH 4/9] OMAP2: Support for early " Thara Gopinath @ 2010-05-30 23:02 ` Benoit Cousson 2010-06-01 9:20 ` Tony Lindgren 2010-06-03 23:18 ` Kevin Hilman 2010-06-03 23:24 ` Kevin Hilman 3 siblings, 1 reply; 22+ messages in thread From: Benoit Cousson @ 2010-05-30 23:02 UTC (permalink / raw) To: Gopinath, Thara Cc: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, tony@atomide.com, Sawant, Anand Hi Thara, On 5/29/2010 4:37 PM, Gopinath, Thara wrote: > This patch converts OMAP2/OMAP3/OMAP4 dual mode timers into > platform devices using omap hwmod, omap device and runtime pm frameworks. > This patch also allows GPTIMER1 and GPTIMER2 to be registered as > early devices. This will allow GPTIMER1 to be registered as > system timer very early on in the system boot up sequence. > Later during normal plaform_device_register these are converted > to normal platform device. > > Signed-off-by: Thara Gopinath<thara@ti.com> > --- > arch/arm/mach-omap2/Makefile | 3 +- > arch/arm/mach-omap2/dmtimers.c | 296 ++++++++++++++++++++++++++++++++++++++++ > arch/arm/mach-omap2/dmtimers.h | 57 ++++++++ > arch/arm/mach-omap2/timer-gp.c | 2 - > 4 files changed, 355 insertions(+), 3 deletions(-) > create mode 100644 arch/arm/mach-omap2/dmtimers.c > create mode 100644 arch/arm/mach-omap2/dmtimers.h > > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile > index dd3a24a..9299e4f 100644 > --- a/arch/arm/mach-omap2/Makefile > +++ b/arch/arm/mach-omap2/Makefile > @@ -3,7 +3,8 @@ > # > > # Common support > -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o > +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o \ > + dmtimers.o > > omap-2-3-common = irq.o sdrc.o > hwmod-common = omap_hwmod.o \ > diff --git a/arch/arm/mach-omap2/dmtimers.c b/arch/arm/mach-omap2/dmtimers.c > new file mode 100644 > index 0000000..6a2caf3 > --- /dev/null > +++ b/arch/arm/mach-omap2/dmtimers.c > @@ -0,0 +1,296 @@ > +/** > + * OMAP2 Dual-Mode Timers > + * > + * Copyright (C) 2010 Texas Instruments, Inc. > + * Thara Gopinath<thara@ti.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include<linux/clk.h> > +#include<linux/delay.h> > +#include<linux/io.h> > +#include<linux/err.h> > +#include<linux/slab.h> > +#include<linux/pm_runtime.h> > + > +#include<mach/irqs.h> > +#include<plat/dmtimer.h> > +#include<plat/omap_hwmod.h> > +#include<plat/omap_device.h> > + > +#include "dmtimers.h" > + > +#define NO_EARLY_TIMERS 2 The "NO_" is a little bit confusing, you should maybe use _COUNT. > +#define OMAP2_DM_TIMER_COUNT 12 > +#define OMAP3PLUS_DM_TIMER_COUNT 11 Why do you need such SoC specific info hard coded here? You should extract that from hwmod data. > + > +static char *omap2_dm_source_names[] __initdata = { > + "sys_ck", > + "func_32k_ck", > + "alt_ck", > + NULL > +}; > +static struct clk *omap2_dm_source_clocks[3]; > + > +static char *omap3_dm_source_names[] __initdata = { > + "sys_ck", > + "omap_32k_fck", > + NULL > +}; > +static struct clk *omap3_dm_source_clocks[2]; > + > +static char *omap4_dm_source_names[] __initdata = { > + "sys_ck", > + "sys_32k_ck", > + NULL > +}; > +static struct clk *omap4_dm_source_clocks[2]; > + > +static struct clk **omap_dm_source_clocks; > + > +static void omap2_dm_timer_enable(struct platform_device *pdev) > +{ > + > + if (pm_runtime_get_sync(&pdev->dev)) > + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", > + __func__); > +#ifndef CONFIG_PM_RUNTIME > + if (omap_device_enable(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", > + __func__); > +#endif > +} > + > +static void omap2_dm_timer_disable(struct platform_device *pdev) > +{ > + > + if (pm_runtime_put_sync(&pdev->dev)) > + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", > + __func__); > +#ifndef CONFIG_PM_RUNTIME > + if (omap_device_idle(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", > + __func__); > +#endif > +} > + > +static int omap2_dm_timer_set_src(struct platform_device *pdev, > + struct clk *timer_clk, int source) > +{ > + int ret; > + > + if (IS_ERR(timer_clk)) { > + dev_warn(&pdev->dev, "%s: Not able get the clock pointer\n", > + __func__); > + return -EINVAL; > + } > + > + clk_disable(timer_clk); > + ret = clk_set_parent(timer_clk, omap_dm_source_clocks[source]); > + if (ret) > + dev_warn(&pdev->dev, "%s: Not able to change the" > + "fclk source\n", __func__); > + > + clk_enable(timer_clk); > + /* > + * When the functional clock disappears, too quick writes seem > + * to cause an abort. XXX Is this still necessary? > + */ Good question... it is still necessary? Do you know what platform has that bug? > + __delay(150000); > + return ret; > +} > + > +static int omap2_dm_timer_set_clk(struct platform_device *pdev, int source) > +{ > + struct clk *timer_clk = clk_get(&pdev->dev, "fck"); > + > + return omap2_dm_timer_set_src(pdev, timer_clk, source); > +} > + > +static struct clk *omap2_dm_timer_get_fclk(struct platform_device *pdev) > +{ > + return clk_get(&pdev->dev, "fck"); > +} > + > +/* API's to be used by early timer devices */ > +static void __init omap2_dm_early_timer_enable(struct platform_device *pdev) > +{ > + if (omap_device_enable(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", > + __func__); > +} > + > +static void __init omap2_dm_early_timer_disable(struct platform_device *pdev) > +{ > + if (omap_device_idle(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", > + __func__); > +} > + > +static int __init omap2_dm_early_timer_set_clk(struct platform_device *pdev, > + int source) > +{ > + struct omap_device *odev = to_omap_device(pdev); > + > + return omap2_dm_timer_set_src(pdev, odev->hwmods[0]->_clk, source); We should maybe consider some new omap_device accessors in order to avoid direct access to internal hwmod attribute from that code. > +} > + > +static struct clk __init *omap2_dm_early_timer_get_fclk > + (struct platform_device *pdev) > +{ > + struct omap_device *odev = to_omap_device(pdev); > + > + return odev->hwmods[0]->_clk; > +} > + > +/* One time initializations */ > +static void __init omap2_dm_timer_setup(void) > +{ > + static int is_initialized; > + char **src_clk_name; > + int i; > + > + /* > + * Check if setup has already been done as part of early init. > + * If yes avoid doing it again. > + */ > + if (is_initialized) > + return; > + > + if (cpu_is_omap24xx()) { > + src_clk_name = omap2_dm_source_names; > + omap_dm_source_clocks = omap2_dm_source_clocks; > + } else if (cpu_is_omap34xx()) { > + src_clk_name = omap3_dm_source_names; > + omap_dm_source_clocks = omap3_dm_source_clocks; > + } else if (cpu_is_omap44xx()) { > + src_clk_name = omap4_dm_source_names; > + omap_dm_source_clocks = omap4_dm_source_clocks; > + } else { > + pr_err("%s: Chip support not yet added\n", __func__); > + return; I don't know how yet, but there is probably a better way to handle that SoC specific part. We have to do that just because the clocks names are not consistent between chip. Using hwmod, there is probably something doable... > + > + > + /* Initialize the dmtimer src clocks */ > + for (i = 0; src_clk_name[i] != NULL; i++) > + omap_dm_source_clocks[i] = > + clk_get(NULL, src_clk_name[i]); > + > + /* Number of dmtimers in the system */ > + if (cpu_is_omap24xx()) > + omap_dm_timer_count = OMAP2_DM_TIMER_COUNT; > + else > + omap_dm_timer_count = OMAP3PLUS_DM_TIMER_COUNT; > + > + is_initialized = 1; > +} > + > +struct omap_device_pm_latency omap2_dmtimer_latency[] = { > + { > + .deactivate_func = omap_device_idle_hwmods, > + .activate_func = omap_device_enable_hwmods, > + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, > + > + }, > +}; > + > +int __init omap2_get_early_timer_count(void) > +{ > + return NO_EARLY_TIMERS; > +} > + > +void __init omap2_dm_timer_early_init(void) > +{ > + int i = 0; > + char *name = "dmtimer"; > + do { > + struct omap_device *od; > + struct omap_hwmod *oh; > + int hw_mod_name_len = 16; > + char oh_name[hw_mod_name_len]; > + struct omap_dm_timer_plat_info *pdata; > + > + snprintf(oh_name, hw_mod_name_len, "timer%d", i + 1); > + oh = omap_hwmod_lookup(oh_name); > + if (!oh) > + break; > + > + pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), > + GFP_KERNEL); > + if (!pdata) { > + pr_err("%s: Unable to allocate pdata for %s:%s\n", > + __func__, name, oh->name); > + return; > + } > + > + pdata->omap_dm_clk_enable = omap2_dm_early_timer_enable; > + pdata->omap_dm_clk_disable = omap2_dm_early_timer_disable; > + pdata->omap_dm_set_source_clk = omap2_dm_early_timer_set_clk; > + pdata->omap_dm_get_timer_clk = omap2_dm_early_timer_get_fclk; > + > + od = omap_device_build(name, i, oh, pdata, sizeof(*pdata), > + omap2_dmtimer_latency, > + ARRAY_SIZE(omap2_dmtimer_latency), 1); > + if (IS_ERR(od)) { > + pr_err("%s: Cant build omap_device for %s:%s.\n", > + __func__, name, oh->name); > + kfree(pdata); > + } > + i++; > + } while (i< NO_EARLY_TIMERS); > + > + omap2_dm_timer_setup(); > + return; > +} > + > +static int __init omap2_dm_timer_init_dev(struct omap_hwmod *oh, void *user) > +{ > + struct omap_device *od; > + struct omap_dm_timer_plat_info *pdata; > + static int i; > + char *name = "dmtimer"; > + > + pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), GFP_KERNEL); > + if (!pdata) { > + pr_err("%s: Unable to allocate pdata for %s:%s\n", > + __func__, name, oh->name); > + return -ENOMEM; > + } > + > + pdata->omap_dm_clk_enable = omap2_dm_timer_enable; > + pdata->omap_dm_clk_disable = omap2_dm_timer_disable; > + pdata->omap_dm_set_source_clk = omap2_dm_timer_set_clk; > + pdata->omap_dm_get_timer_clk = omap2_dm_timer_get_fclk; > + > + od = omap_device_build(name, i, oh, pdata, sizeof(*pdata), > + omap2_dmtimer_latency, > + ARRAY_SIZE(omap2_dmtimer_latency), 0); > + if (IS_ERR(od)) { > + pr_err("%s: Cant build omap_device for %s:%s.\n", > + __func__, name, oh->name); > + kfree(pdata); > + i++; > + return 0; > + } > + pm_runtime_enable(&(od->pdev.dev)); > + i++; > + return 0; > +} > + > +static int __init omap2_dm_timer_init(void) > +{ > + int ret; > + > + omap2_dm_timer_setup(); > + > + ret = omap_hwmod_for_each_by_class("timer_1ms", > + omap2_dm_timer_init_dev, NULL); > + > + ret |= omap_hwmod_for_each_by_class("timer", > + omap2_dm_timer_init_dev, NULL); > + return ret; > +} > +arch_initcall(omap2_dm_timer_init); > diff --git a/arch/arm/mach-omap2/dmtimers.h b/arch/arm/mach-omap2/dmtimers.h > new file mode 100644 > index 0000000..dbc2b9d > --- /dev/null > +++ b/arch/arm/mach-omap2/dmtimers.h > @@ -0,0 +1,57 @@ > +/** > + * OMAP2 Dual-Mode Timers > + * > + * Copyright (C) 2010 Texas Instruments, Inc. > + * Thara Gopinath<thara@ti.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#ifndef __ASM_ARCH_DMTIMERS_H > +#define __ASM_ARCH_DMTIMERS_H > + > +#define OMAP2420_GPTIMER1_BASE 0x48028000 > +#define OMAP2430_GPTIMER1_BASE 0x49018000 > +#define OMAP24XX_GPTIMER2_BASE 0x4802a000 > +#define OMAP24XX_GPTIMER3_BASE 0x48078000 > +#define OMAP24XX_GPTIMER4_BASE 0x4807a000 > +#define OMAP24XX_GPTIMER5_BASE 0x4807c000 > +#define OMAP24XX_GPTIMER6_BASE 0x4807e000 > +#define OMAP24XX_GPTIMER7_BASE 0x48080000 > +#define OMAP24XX_GPTIMER8_BASE 0x48082000 > +#define OMAP24XX_GPTIMER9_BASE 0x48084000 > +#define OMAP24XX_GPTIMER10_BASE 0x48086000 > +#define OMAP24XX_GPTIMER11_BASE 0x48088000 > +#define OMAP24XX_GPTIMER12_BASE 0x4808a000 > + > +#define OMAP34XX_GPTIMER1_BASE 0x48318000 > +#define OMAP34XX_GPTIMER2_BASE 0x49032000 > +#define OMAP34XX_GPTIMER3_BASE 0x49034000 > +#define OMAP34XX_GPTIMER4_BASE 0x49036000 > +#define OMAP34XX_GPTIMER5_BASE 0x49038000 > +#define OMAP34XX_GPTIMER6_BASE 0x4903A000 > +#define OMAP34XX_GPTIMER7_BASE 0x4903C000 > +#define OMAP34XX_GPTIMER8_BASE 0x4903E000 > +#define OMAP34XX_GPTIMER9_BASE 0x49040000 > +#define OMAP34XX_GPTIMER10_BASE 0x48086000 > +#define OMAP34XX_GPTIMER11_BASE 0x48088000 > +#define OMAP34XX_GPTIMER12_BASE 0x48304000 > + > +#define OMAP44XX_GPTIMER1_BASE 0x4a318000 > +#define OMAP44XX_GPTIMER2_BASE 0x48032000 > +#define OMAP44XX_GPTIMER3_BASE 0x48034000 > +#define OMAP44XX_GPTIMER4_BASE 0x48036000 > +#define OMAP44XX_GPTIMER5_BASE 0x40138000 > +#define OMAP44XX_GPTIMER6_BASE 0x4013a000 > +#define OMAP44XX_GPTIMER7_BASE 0x4013a000 > +#define OMAP44XX_GPTIMER8_BASE 0x4013e000 > +#define OMAP44XX_GPTIMER9_BASE 0x4803e000 > +#define OMAP44XX_GPTIMER10_BASE 0x48086000 > +#define OMAP44XX_GPTIMER11_BASE 0x48088000 > +#define OMAP44XX_GPTIMER12_BASE 0x4a320000 If these defines are only used for the hwmod definition, they should be moved to a per Soc memory map file. Benoit > + > +void __init omap2_dm_timer_early_init(void); > +int __init omap2_get_early_timer_count(void); > +#endif > diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c > index 74fbed8..d5f2ba7 100644 > --- a/arch/arm/mach-omap2/timer-gp.c > +++ b/arch/arm/mach-omap2/timer-gp.c > @@ -231,8 +231,6 @@ static void __init omap2_gp_timer_init(void) > twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); > BUG_ON(!twd_base); > #endif > - omap_dm_timer_init(); > - > omap2_gp_clockevent_init(); > omap2_gp_clocksource_init(); > } > -- > 1.7.0.rc1.33.g07cf0f > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. 2010-05-30 23:02 ` [PATCH 3/9] OMAP2/3/4 : Dual mode timer " Benoit Cousson @ 2010-06-01 9:20 ` Tony Lindgren 2010-06-03 9:30 ` Gopinath, Thara 0 siblings, 1 reply; 22+ messages in thread From: Tony Lindgren @ 2010-06-01 9:20 UTC (permalink / raw) To: Benoit Cousson Cc: Gopinath, Thara, linux-omap@vger.kernel.org, khilman@deeprootsystems.com, Sawant, Anand * Benoit Cousson <b-cousson@ti.com> [100531 01:57]: > >+ > >+#define NO_EARLY_TIMERS 2 > The "NO_" is a little bit confusing, you should maybe use _COUNT. Also NR_ is commonly used. Tony ^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. 2010-06-01 9:20 ` Tony Lindgren @ 2010-06-03 9:30 ` Gopinath, Thara 0 siblings, 0 replies; 22+ messages in thread From: Gopinath, Thara @ 2010-06-03 9:30 UTC (permalink / raw) To: Tony Lindgren, Cousson, Benoit Cc: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, Sawant, Anand >>-----Original Message----- >>From: Tony Lindgren [mailto:tony@atomide.com] >>Sent: Tuesday, June 01, 2010 2:51 PM >>To: Cousson, Benoit >>Cc: Gopinath, Thara; linux-omap@vger.kernel.org; khilman@deeprootsystems.com; Sawant, Anand >>Subject: Re: [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. >> >>* Benoit Cousson <b-cousson@ti.com> [100531 01:57]: >>> >+ >>> >+#define NO_EARLY_TIMERS 2 >>> The "NO_" is a little bit confusing, you should maybe use _COUNT. >> >>Also NR_ is commonly used. I will fix this in the repost >> >>Tony ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. 2010-05-29 14:37 ` [PATCH 3/9] OMAP2/3/4 : " Thara Gopinath 2010-05-29 14:37 ` [PATCH 4/9] OMAP2: Support for early " Thara Gopinath 2010-05-30 23:02 ` [PATCH 3/9] OMAP2/3/4 : Dual mode timer " Benoit Cousson @ 2010-06-03 23:18 ` Kevin Hilman 2010-06-03 23:24 ` Kevin Hilman 3 siblings, 0 replies; 22+ messages in thread From: Kevin Hilman @ 2010-06-03 23:18 UTC (permalink / raw) To: Thara Gopinath; +Cc: linux-omap, tony, sawant Thara Gopinath <thara@ti.com> writes: > This patch converts OMAP2/OMAP3/OMAP4 dual mode timers into > platform devices using omap hwmod, omap device and runtime pm frameworks. > This patch also allows GPTIMER1 and GPTIMER2 to be registered as > early devices. This will allow GPTIMER1 to be registered as > system timer very early on in the system boot up sequence. > Later during normal plaform_device_register these are converted > to normal platform device. > > Signed-off-by: Thara Gopinath <thara@ti.com> First, a couple of general comments. You're using the runtime PM API here in the device layer hooks. This should be in the driver. It will be a noop for OMAP1 since there will be no runtime PM implementation, but that is fine. Moving this into the driver should allow you to get rid of the enable/disable clock hooks you currently have in platform_data as well (for early timers you could leave them enabled until they are converted to "normal" timers.) Also, I suggested this to Charu as well for GPIO and WDT, but we should leave out the handling of the #ifndef CONFIG_PM_RUNTIME from this code. I'd rather not have every driver handling that special case. Instead I propose we handle this in the omap_hwmod init sequence by enabling all the hwmods if !CONFIG_PM_RUNTIME. > --- > arch/arm/mach-omap2/Makefile | 3 +- > arch/arm/mach-omap2/dmtimers.c | 296 ++++++++++++++++++++++++++++++++++++++++ > arch/arm/mach-omap2/dmtimers.h | 57 ++++++++ > arch/arm/mach-omap2/timer-gp.c | 2 - > 4 files changed, 355 insertions(+), 3 deletions(-) > create mode 100644 arch/arm/mach-omap2/dmtimers.c > create mode 100644 arch/arm/mach-omap2/dmtimers.h > > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile > index dd3a24a..9299e4f 100644 > --- a/arch/arm/mach-omap2/Makefile > +++ b/arch/arm/mach-omap2/Makefile > @@ -3,7 +3,8 @@ > # > > # Common support > -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o > +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o \ > + dmtimers.o > > omap-2-3-common = irq.o sdrc.o > hwmod-common = omap_hwmod.o \ > diff --git a/arch/arm/mach-omap2/dmtimers.c b/arch/arm/mach-omap2/dmtimers.c > new file mode 100644 > index 0000000..6a2caf3 > --- /dev/null > +++ b/arch/arm/mach-omap2/dmtimers.c > @@ -0,0 +1,296 @@ > +/** > + * OMAP2 Dual-Mode Timers > + * > + * Copyright (C) 2010 Texas Instruments, Inc. > + * Thara Gopinath <thara@ti.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/io.h> > +#include <linux/err.h> > +#include <linux/slab.h> > +#include <linux/pm_runtime.h> > + > +#include <mach/irqs.h> > +#include <plat/dmtimer.h> > +#include <plat/omap_hwmod.h> > +#include <plat/omap_device.h> > + > +#include "dmtimers.h" > + > +#define NO_EARLY_TIMERS 2 Please use NR_EARLY_TIMERS > +#define OMAP2_DM_TIMER_COUNT 12 > +#define OMAP3PLUS_DM_TIMER_COUNT 11 and these you should get rid of as Benoit pointed out. More on this below. > +static char *omap2_dm_source_names[] __initdata = { > + "sys_ck", > + "func_32k_ck", > + "alt_ck", > + NULL > +}; > +static struct clk *omap2_dm_source_clocks[3]; > + > +static char *omap3_dm_source_names[] __initdata = { > + "sys_ck", > + "omap_32k_fck", > + NULL > +}; > +static struct clk *omap3_dm_source_clocks[2]; > + > +static char *omap4_dm_source_names[] __initdata = { > + "sys_ck", > + "sys_32k_ck", > + NULL > +}; > +static struct clk *omap4_dm_source_clocks[2]; > + > +static struct clk **omap_dm_source_clocks; > + > +static void omap2_dm_timer_enable(struct platform_device *pdev) > +{ > + > + if (pm_runtime_get_sync(&pdev->dev)) > + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", > + __func__); > +#ifndef CONFIG_PM_RUNTIME > + if (omap_device_enable(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", > + __func__); > +#endif > +} > + > +static void omap2_dm_timer_disable(struct platform_device *pdev) > +{ > + > + if (pm_runtime_put_sync(&pdev->dev)) > + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", > + __func__); > +#ifndef CONFIG_PM_RUNTIME > + if (omap_device_idle(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", > + __func__); > +#endif > +} > + > +static int omap2_dm_timer_set_src(struct platform_device *pdev, > + struct clk *timer_clk, int source) > +{ > + int ret; > + > + if (IS_ERR(timer_clk)) { > + dev_warn(&pdev->dev, "%s: Not able get the clock pointer\n", > + __func__); > + return -EINVAL; > + } > + > + clk_disable(timer_clk); > + ret = clk_set_parent(timer_clk, omap_dm_source_clocks[source]); > + if (ret) > + dev_warn(&pdev->dev, "%s: Not able to change the" > + "fclk source\n", __func__); > + > + clk_enable(timer_clk); > + /* > + * When the functional clock disappears, too quick writes seem > + * to cause an abort. XXX Is this still necessary? > + */ > + __delay(150000); > + return ret; > +} > + > +static int omap2_dm_timer_set_clk(struct platform_device *pdev, int source) > +{ > + struct clk *timer_clk = clk_get(&pdev->dev, "fck"); > + > + return omap2_dm_timer_set_src(pdev, timer_clk, source); Missing a clk_put() here. > +} > + > +static struct clk *omap2_dm_timer_get_fclk(struct platform_device *pdev) > +{ > + return clk_get(&pdev->dev, "fck"); > +} > + > +/* API's to be used by early timer devices */ > +static void __init omap2_dm_early_timer_enable(struct platform_device *pdev) > +{ > + if (omap_device_enable(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to enable the timer\n", > + __func__); > +} > + > +static void __init omap2_dm_early_timer_disable(struct platform_device *pdev) > +{ > + if (omap_device_idle(pdev)) > + dev_warn(&pdev->dev, "%s: Unable to disable the timer\n", > + __func__); > +} I suggest just dropping the early enable/disable hooks and leaving them enabled. Once the "normal" probe runs, they can be disabled if unused. That will avoid having to havea special set of hooks for early devices. > +static int __init omap2_dm_early_timer_set_clk(struct platform_device *pdev, > + int source) > +{ > + struct omap_device *odev = to_omap_device(pdev); > + > + return omap2_dm_timer_set_src(pdev, odev->hwmods[0]->_clk, source); > +} As Benoit mentioned, I think we may need an omap_hwmod_get_clk() or something to avoid touching hwmod internals and make this cleaner. That being said, why do you need a special "early" version of the set_clk. You could use this version for both. > +static struct clk __init *omap2_dm_early_timer_get_fclk > + (struct platform_device *pdev) > +{ > + struct omap_device *odev = to_omap_device(pdev); > + > + return odev->hwmods[0]->_clk; > +} Likewise, this could use a new function omap_hwmod_get_clk() and could be used for both early and normal versions. > +/* One time initializations */ > +static void __init omap2_dm_timer_setup(void) > +{ > + static int is_initialized; > + char **src_clk_name; > + int i; > + > + /* > + * Check if setup has already been done as part of early init. > + * If yes avoid doing it again. > + */ > + if (is_initialized) > + return; > + > + if (cpu_is_omap24xx()) { > + src_clk_name = omap2_dm_source_names; > + omap_dm_source_clocks = omap2_dm_source_clocks; > + } else if (cpu_is_omap34xx()) { > + src_clk_name = omap3_dm_source_names; > + omap_dm_source_clocks = omap3_dm_source_clocks; > + } else if (cpu_is_omap44xx()) { > + src_clk_name = omap4_dm_source_names; > + omap_dm_source_clocks = omap4_dm_source_clocks; > + } else { > + pr_err("%s: Chip support not yet added\n", __func__); > + return; > + } > + > + /* Initialize the dmtimer src clocks */ > + for (i = 0; src_clk_name[i] != NULL; i++) > + omap_dm_source_clocks[i] = > + clk_get(NULL, src_clk_name[i]); > + > + /* Number of dmtimers in the system */ > + if (cpu_is_omap24xx()) > + omap_dm_timer_count = OMAP2_DM_TIMER_COUNT; > + else > + omap_dm_timer_count = OMAP3PLUS_DM_TIMER_COUNT; This shouldn't be necessary. You should have a count after iterating through the hwmods in this class. > + is_initialized = 1; > +} > + > +struct omap_device_pm_latency omap2_dmtimer_latency[] = { > + { > + .deactivate_func = omap_device_idle_hwmods, > + .activate_func = omap_device_enable_hwmods, > + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, indentation > + }, > +}; > + > +int __init omap2_get_early_timer_count(void) > +{ > + return NO_EARLY_TIMERS; > +} > + > +void __init omap2_dm_timer_early_init(void) > +{ > + int i = 0; > + char *name = "dmtimer"; insert blank line > + do { minor nit, but this would be clearer if it were a for loop. If someone wanted to set NR_EARLY_TIMERS = 0, this loop would still execute once, and would not be the intended behavior. > + struct omap_device *od; > + struct omap_hwmod *oh; > + int hw_mod_name_len = 16; > + char oh_name[hw_mod_name_len]; s/hw_mod/hwmod/ > + struct omap_dm_timer_plat_info *pdata; > + > + snprintf(oh_name, hw_mod_name_len, "timer%d", i + 1); > + oh = omap_hwmod_lookup(oh_name); > + if (!oh) > + break; > + > + pdata = kzalloc(sizeof(struct omap_dm_timer_plat_info), > + GFP_KERNEL); > + if (!pdata) { > + pr_err("%s: Unable to allocate pdata for %s:%s\n", > + __func__, name, oh->name); > + return; > + } > + > + pdata->omap_dm_clk_enable = omap2_dm_early_timer_enable; > + pdata->omap_dm_clk_disable = omap2_dm_early_timer_disable; > + pdata->omap_dm_set_source_clk = omap2_dm_early_timer_set_clk; > + pdata->omap_dm_get_timer_clk = omap2_dm_early_timer_get_fclk; > + > + od = omap_device_build(name, i, oh, pdata, sizeof(*pdata), > + omap2_dmtimer_latency, > + ARRAY_SIZE(omap2_dmtimer_latency), 1); > + if (IS_ERR(od)) { > + pr_err("%s: Cant build omap_device for %s:%s.\n", > + __func__, name, oh->name); > + kfree(pdata); > + } > + i++; > + } while (i < NO_EARLY_TIMERS); > + > + omap2_dm_timer_setup(); > + return; > +} Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/9] OMAP2/3/4 : Dual mode timer device registration. 2010-05-29 14:37 ` [PATCH 3/9] OMAP2/3/4 : " Thara Gopinath ` (2 preceding siblings ...) 2010-06-03 23:18 ` Kevin Hilman @ 2010-06-03 23:24 ` Kevin Hilman 3 siblings, 0 replies; 22+ messages in thread From: Kevin Hilman @ 2010-06-03 23:24 UTC (permalink / raw) To: Thara Gopinath; +Cc: linux-omap, tony, sawant Thara Gopinath <thara@ti.com> writes: > This patch converts OMAP2/OMAP3/OMAP4 dual mode timers into > platform devices using omap hwmod, omap device and runtime pm frameworks. > This patch also allows GPTIMER1 and GPTIMER2 to be registered as > early devices. This will allow GPTIMER1 to be registered as > system timer very early on in the system boot up sequence. > Later during normal plaform_device_register these are converted > to normal platform device. > > Signed-off-by: Thara Gopinath <thara@ti.com> [...] > +#define OMAP2_DM_TIMER_COUNT 12 > +#define OMAP3PLUS_DM_TIMER_COUNT 11 Also, I noticed this patch drops support for handling GPT12, but is not explained in the changelog or in PATCH 0/x description. Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver. 2010-05-29 14:37 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Thara Gopinath 2010-05-29 14:37 ` [PATCH 2/9] OMAP1: Dual mode timer device registration Thara Gopinath @ 2010-06-03 19:47 ` Kevin Hilman 1 sibling, 0 replies; 22+ messages in thread From: Kevin Hilman @ 2010-06-03 19:47 UTC (permalink / raw) To: Thara Gopinath; +Cc: linux-omap, tony, sawant Thara Gopinath <thara@ti.com> writes: > This patch converts dual mode timer library into a platform driver. > This essentially involves moving out interrupt and base address > related info from plat-omap/dmtimer.c and making certain clock related > functions platform data. This patch also initializes dm timer driver as > a earlydriver. This is so that early timer devices required during > system boot up can be initialized very early on. > > Signed-off-by: Thara Gopinath <thara@ti.com> > --- > arch/arm/plat-omap/dmtimer.c | 401 ++++++++++++----------------- > arch/arm/plat-omap/include/plat/dmtimer.h | 12 +- > 2 files changed, 176 insertions(+), 237 deletions(-) > > diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c > index 4d99dfb..c17911d 100644 > --- a/arch/arm/plat-omap/dmtimer.c > +++ b/arch/arm/plat-omap/dmtimer.c > @@ -10,6 +10,9 @@ > * Copyright (C) 2009 Texas Instruments > * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> > * > + * Copyright (C) 2010 Texas Instruments > + * Converted to a platform driver - Thara Gopinath <thara@ti.com> > + * > * This program is free software; you can redistribute it and/or modify it > * under the terms of the GNU General Public License as published by the > * Free Software Foundation; either version 2 of the License, or (at your > @@ -32,11 +35,14 @@ > #include <linux/init.h> > #include <linux/spinlock.h> > #include <linux/errno.h> > +#include <linux/err.h> > #include <linux/list.h> > #include <linux/clk.h> > #include <linux/delay.h> > #include <linux/io.h> > #include <linux/module.h> > +#include <linux/slab.h> > + > #include <mach/hardware.h> > #include <plat/dmtimer.h> > #include <mach/irqs.h> > @@ -153,136 +159,18 @@ > struct omap_dm_timer { > unsigned long phys_base; > int irq; > -#ifdef CONFIG_ARCH_OMAP2PLUS > - struct clk *iclk, *fclk; > -#endif > void __iomem *io_base; > unsigned reserved:1; > unsigned enabled:1; > unsigned posted:1; > + unsigned is_intialized:1; typo: is_initialized. > + struct platform_device *pdev; > }; > > -static int dm_timer_count; > - > -#ifdef CONFIG_ARCH_OMAP1 > -static struct omap_dm_timer omap1_dm_timers[] = { > - { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, > - { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, > - { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, > - { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 }, > - { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 }, > - { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 }, > - { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 }, > - { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, > -}; > - > -static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers); > - > -#else > -#define omap1_dm_timers NULL > -#define omap1_dm_timer_count 0 > -#endif /* CONFIG_ARCH_OMAP1 */ > - > -#ifdef CONFIG_ARCH_OMAP2 > -static struct omap_dm_timer omap2_dm_timers[] = { > - { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, > - { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, > - { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, > - { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 }, > - { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 }, > - { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 }, > - { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 }, > - { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 }, > - { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 }, > - { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, > - { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, > - { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, > -}; > - > -static const char *omap2_dm_source_names[] __initdata = { > - "sys_ck", > - "func_32k_ck", > - "alt_ck", > - NULL > -}; > - > -static struct clk *omap2_dm_source_clocks[3]; > -static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers); > - > -#else > -#define omap2_dm_timers NULL > -#define omap2_dm_timer_count 0 > -#define omap2_dm_source_names NULL > -#define omap2_dm_source_clocks NULL > -#endif /* CONFIG_ARCH_OMAP2 */ > - > -#ifdef CONFIG_ARCH_OMAP3 > -static struct omap_dm_timer omap3_dm_timers[] = { > - { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, > - { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, > - { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 }, > - { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 }, > - { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 }, > - { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 }, > - { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 }, > - { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 }, > - { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, > - { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, > - { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, > - { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ }, > -}; > - > -static const char *omap3_dm_source_names[] __initdata = { > - "sys_ck", > - "omap_32k_fck", > - NULL > -}; > - > -static struct clk *omap3_dm_source_clocks[2]; > -static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers); > - > -#else > -#define omap3_dm_timers NULL > -#define omap3_dm_timer_count 0 > -#define omap3_dm_source_names NULL > -#define omap3_dm_source_clocks NULL > -#endif /* CONFIG_ARCH_OMAP3 */ > - > -#ifdef CONFIG_ARCH_OMAP4 > -static struct omap_dm_timer omap4_dm_timers[] = { > - { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 }, > - { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 }, > - { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 }, > - { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 }, > - { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 }, > - { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 }, > - { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 }, > - { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 }, > - { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 }, > - { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 }, > - { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 }, > - { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, > -}; > -static const char *omap4_dm_source_names[] __initdata = { > - "sys_ck", > - "omap_32k_fck", > - NULL > -}; > -static struct clk *omap4_dm_source_clocks[2]; > -static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers); > - > -#else > -#define omap4_dm_timers NULL > -#define omap4_dm_timer_count 0 > -#define omap4_dm_source_names NULL > -#define omap4_dm_source_clocks NULL > -#endif /* CONFIG_ARCH_OMAP4 */ > - > +int omap_dm_timer_count; > static struct omap_dm_timer *dm_timers; > -static const char **dm_source_names; > -static struct clk **dm_source_clocks; > - > static spinlock_t dm_timer_lock; > +static int is_driver_init; > > /* > * Reads timer registers in posted and non-posted mode. The posted mode bit > @@ -368,7 +256,7 @@ struct omap_dm_timer *omap_dm_timer_request(void) > int i; > > spin_lock_irqsave(&dm_timer_lock, flags); > - for (i = 0; i < dm_timer_count; i++) { > + for (i = 0; i < omap_dm_timer_count; i++) { > if (dm_timers[i].reserved) > continue; > > @@ -391,7 +279,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) > unsigned long flags; > > spin_lock_irqsave(&dm_timer_lock, flags); > - if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { > + if (id <= 0 || id > omap_dm_timer_count || dm_timers[id-1].reserved) { > spin_unlock_irqrestore(&dm_timer_lock, flags); > printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", > __FILE__, __LINE__, __func__, id); > @@ -422,32 +310,32 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free); > > void omap_dm_timer_enable(struct omap_dm_timer *timer) > { > + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; > + > if (timer->enabled) > return; > > -#ifdef CONFIG_ARCH_OMAP2PLUS > - if (cpu_class_is_omap2()) { > - clk_enable(timer->fclk); > - clk_enable(timer->iclk); > - } > -#endif > - > + if (pdata->omap_dm_clk_enable) > + pdata->omap_dm_clk_enable(timer->pdev); > + else > + dev_warn(&timer->pdev->dev, "%s: No enable fn registered\n", > + __func__); > timer->enabled = 1; > } > EXPORT_SYMBOL_GPL(omap_dm_timer_enable); > > void omap_dm_timer_disable(struct omap_dm_timer *timer) > { > + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; > + > if (!timer->enabled) > return; > > -#ifdef CONFIG_ARCH_OMAP2PLUS > - if (cpu_class_is_omap2()) { > - clk_disable(timer->iclk); > - clk_disable(timer->fclk); > - } > -#endif > - > + if (pdata->omap_dm_clk_disable) > + pdata->omap_dm_clk_disable(timer->pdev); > + else > + dev_warn(&timer->pdev->dev, "%s: No disable fn registered\n", > + __func__); > timer->enabled = 0; > } > EXPORT_SYMBOL_GPL(omap_dm_timer_disable); > @@ -458,22 +346,26 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer) > } > EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); > > -#if defined(CONFIG_ARCH_OMAP1) > - > /** > * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR > + * valid only for OMAP1 > * @inputmask: current value of idlect mask > */ > __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) > { > int i; > > + if (cpu_class_is_omap2()) { > + BUG(); > + return 0; > + } > + > /* If ARMXOR cannot be idled this function call is unnecessary */ > if (!(inputmask & (1 << 1))) > return inputmask; > > /* If any active timer is using ARMXOR return modified mask */ > - for (i = 0; i < dm_timer_count; i++) { > + for (i = 0; i < omap_dm_timer_count; i++) { > u32 l; > > l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG); > @@ -489,23 +381,18 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) > } > EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); > > -#else > - > struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) > { > - return timer->fclk; > -} > -EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); > + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; > > -__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) > -{ > - BUG(); > + if (pdata->omap_dm_get_timer_clk) > + return pdata->omap_dm_get_timer_clk(timer->pdev); > > - return 0; > + dev_warn(&timer->pdev->dev, "%s: No get fclk clock fn registered\n", > + __func__); > + return ERR_PTR(-EINVAL); > } > -EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); > - > -#endif > +EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); > > void omap_dm_timer_trigger(struct omap_dm_timer *timer) > { > @@ -531,64 +418,47 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) > > l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); > if (l & OMAP_TIMER_CTRL_ST) { > + struct clk *timer_fclk; > + > l &= ~0x1; > omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); > -#ifdef CONFIG_ARCH_OMAP2PLUS > + > + if (cpu_class_is_omap1()) > + return; > + > /* Readback to make sure write has completed */ > omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); > /* > * Wait for functional clock period x 3.5 to make sure that > * timer is stopped > */ > - udelay(3500000 / clk_get_rate(timer->fclk) + 1); > + timer_fclk = omap_dm_timer_get_fclk(timer); > + if (IS_ERR(timer_fclk)) > + dev_warn(&timer->pdev->dev, "%s: Unable to get" > + "timer fclk!\n", __func__); > + else > + udelay(3500000 / clk_get_rate(timer_fclk) + 1); > + > /* Ack possibly pending interrupt */ > omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, > OMAP_TIMER_INT_OVERFLOW); > -#endif > } > } > EXPORT_SYMBOL_GPL(omap_dm_timer_stop); > > -#ifdef CONFIG_ARCH_OMAP1 > - > -int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) > -{ > - int n = (timer - dm_timers) << 1; > - u32 l; > - > - l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); > - l |= source << n; > - omap_writel(l, MOD_CONF_CTRL_1); > - > - return 0; > -} > -EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); > - > -#else > - > int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) > { > - int ret = -EINVAL; > + struct omap_dm_timer_plat_info *pdata = timer->pdev->dev.platform_data; > > - if (source < 0 || source >= 3) > - return -EINVAL; > - > - clk_disable(timer->fclk); > - ret = clk_set_parent(timer->fclk, dm_source_clocks[source]); > - clk_enable(timer->fclk); > - > - /* > - * When the functional clock disappears, too quick writes seem > - * to cause an abort. XXX Is this still necessary? > - */ > - __delay(150000); > + if (pdata->omap_dm_set_source_clk) > + return pdata->omap_dm_set_source_clk(timer->pdev, source); > > - return ret; > + dev_warn(&timer->pdev->dev, "%s: No set source clock fn registered\n", > + __func__); > + return -EINVAL; > } > EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); > > -#endif > - > void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, > unsigned int load) > { > @@ -716,7 +586,7 @@ int omap_dm_timers_active(void) > { > int i; > > - for (i = 0; i < dm_timer_count; i++) { > + for (i = 0; i < omap_dm_timer_count; i++) { > struct omap_dm_timer *timer; > > timer = &dm_timers[i]; > @@ -733,61 +603,120 @@ int omap_dm_timers_active(void) > } > EXPORT_SYMBOL_GPL(omap_dm_timers_active); > > -int __init omap_dm_timer_init(void) > +static int __devinit omap_dm_timer_data_init(void) > { > - struct omap_dm_timer *timer; > - int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ > + if (!is_driver_init) { > + is_driver_init = 1; > + spin_lock_init(&dm_timer_lock); > + if (!omap_dm_timer_count) { > + pr_err("%s: OMAP DMTIMER - Number of dmtimers in" > + "the system not defined.Error!\n", __func__); > + return -EINVAL; > + } > + dm_timers = kzalloc(omap_dm_timer_count * > + sizeof(struct omap_dm_timer), GFP_KERNEL); > + if (!dm_timers) { > + pr_err("%s: OMAPP DMTIMER - Unable to allocate" > + "dm_timers\n", __func__); > + return -EINVAL; > + } > + } > + return 0; > +} I don't follow the need for this as a separate function. Can't this just live in _probe() with some error checking? Also, it looks like the spin_lock_init() could be moved to after the 'is_initialized' check in probe. > - if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) > - return -ENODEV; > +static int __devinit omap_dm_timer_probe(struct platform_device *pdev) > +{ > + struct omap_dm_timer_plat_info *pdata = pdev->dev.platform_data; > + struct resource *mem; > + int id = pdev->id; > + int ret; > + > + if (!pdata) { > + dev_err(&pdev->dev, "%s: Timer device initialized without" > + "platform data\n", __func__); > + return -EINVAL; > + } > > - spin_lock_init(&dm_timer_lock); > - > - if (cpu_class_is_omap1()) { > - dm_timers = omap1_dm_timers; > - dm_timer_count = omap1_dm_timer_count; > - map_size = SZ_2K; > - } else if (cpu_is_omap24xx()) { > - dm_timers = omap2_dm_timers; > - dm_timer_count = omap2_dm_timer_count; > - dm_source_names = omap2_dm_source_names; > - dm_source_clocks = omap2_dm_source_clocks; > - } else if (cpu_is_omap34xx()) { > - dm_timers = omap3_dm_timers; > - dm_timer_count = omap3_dm_timer_count; > - dm_source_names = omap3_dm_source_names; > - dm_source_clocks = omap3_dm_source_clocks; > - } else if (cpu_is_omap44xx()) { > - dm_timers = omap4_dm_timers; > - dm_timer_count = omap4_dm_timer_count; > - dm_source_names = omap4_dm_source_names; > - dm_source_clocks = omap4_dm_source_clocks; > + ret = omap_dm_timer_data_init(); > + if (ret) { > + dev_err(&pdev->dev, "%s: Unable to do timer data init\n", > + __func__); > + return ret; > } > > - if (cpu_class_is_omap2()) > - for (i = 0; dm_source_names[i] != NULL; i++) > - dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); > + dm_timers[id].pdev = pdev; I don't like the use of the id index here. It makes _probe() assume that there are multiple instances which it should not have to know. Just make _probe() allocate memory for its own instance. Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS 2010-05-29 14:37 [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Thara Gopinath 2010-05-29 14:37 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Thara Gopinath @ 2010-05-30 22:11 ` Benoit Cousson 2010-06-03 22:20 ` Kevin Hilman 2010-06-01 9:37 ` Tony Lindgren 2 siblings, 1 reply; 22+ messages in thread From: Benoit Cousson @ 2010-05-30 22:11 UTC (permalink / raw) To: Gopinath, Thara Cc: linux-omap@vger.kernel.org, khilman@deeprootsystems.com, tony@atomide.com, Sawant, Anand On 5/29/2010 4:37 PM, Gopinath, Thara wrote: > This patch series converts the OMAP Dual Mode Timer into a > platform driver. This involves using of hwmod structures and > omap_device layer for OMAP2/3/4 dmtimers and generic > linux platform device layer for OMAP1. > > As a result of this patch series the dmtimer platform driver > resides in arch/arm/plat-omap directory and arch specific > implementations and device registerations reside in > arch/arm/mach-omap1 and arch/arm/mach-omap2 for OMAP1 > and OMAP2 PLUS respectively. Hi Thara, The Dual timer terminology is not used anymore since 2420. It was replaced by gptimer and will be simplified going forward using timer. This IP is almost the same since 1610, but will have 3 different names. It might be the good opportunity to align the names? (OK, the code is full of dm_timer everywhere... so that might not worth the effort). Let's consider that as my 2 cents... Benoit > This patch series has been compile tested for OMAP1 using > omap_1610_h2_defconfig, compile tested for OMAP2 using > omap3_defconfig and boot and sanity tested for OMAP3/OMAP4 > again using omap3_defconfig. Boot testing has been done > on OMAP3430 SDP and OMAP4430 SDP boards. All testing has > been done on origin/origin/pm-wip/hwmods-omap4 branch off > Kevin Hilman's tree as these patches have dependencies on > runtime pm API's and OMAP4 autogenerated hwmod data base. > > It would be great if somebody could test these patches on OMAP1 > and OMAP2 platforms. > > Thara Gopinath (9): > OMAP: Convert dual mode timer into a platform driver. > OMAP1: Dual mode timer device registration. > OMAP2/3/4 : Dual mode timer device registration. > OMAP2: Support for early device registration > OMAP2/3/4: Adding device names to dmtimer fclk nodes > OMAP3: Add hwmod data for OMAP3 dual mode timers. > OMAP2: Add hwmod data for OMAP2420 dual mode timers. > OMAP2: Add hwmod data for OMAP2430 dual mode timers. > OMAP4: Changing dmtimer1 fclk name > > arch/arm/mach-omap1/Makefile | 1 + > arch/arm/mach-omap1/dmtimers.c | 148 +++++++ > arch/arm/mach-omap1/timer32k.c | 3 - > arch/arm/mach-omap2/Makefile | 3 +- > arch/arm/mach-omap2/clock2420_data.c | 24 +- > arch/arm/mach-omap2/clock2430_data.c | 24 +- > arch/arm/mach-omap2/clock3xxx_data.c | 22 +- > arch/arm/mach-omap2/clock44xx_data.c | 24 +- > arch/arm/mach-omap2/dmtimers.c | 296 +++++++++++++ > arch/arm/mach-omap2/dmtimers.h | 57 +++ > arch/arm/mach-omap2/io.c | 16 + > arch/arm/mach-omap2/omap_hwmod_2420_data.c | 619 +++++++++++++++++++++++++++- > arch/arm/mach-omap2/omap_hwmod_2430_data.c | 619 +++++++++++++++++++++++++++- > arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 572 +++++++++++++++++++++++++- > arch/arm/mach-omap2/timer-gp.c | 2 - > arch/arm/plat-omap/dmtimer.c | 401 ++++++++----------- > arch/arm/plat-omap/include/plat/dmtimer.h | 12 +- > 17 files changed, 2550 insertions(+), 293 deletions(-) > create mode 100644 arch/arm/mach-omap1/dmtimers.c > create mode 100644 arch/arm/mach-omap2/dmtimers.c > create mode 100644 arch/arm/mach-omap2/dmtimers.h > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS 2010-05-30 22:11 ` [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Benoit Cousson @ 2010-06-03 22:20 ` Kevin Hilman 2010-06-03 22:29 ` Benoit 0 siblings, 1 reply; 22+ messages in thread From: Kevin Hilman @ 2010-06-03 22:20 UTC (permalink / raw) To: Benoit Cousson Cc: Gopinath, Thara, linux-omap@vger.kernel.org, tony@atomide.com, Sawant, Anand Benoit Cousson <b-cousson@ti.com> writes: > On 5/29/2010 4:37 PM, Gopinath, Thara wrote: >> This patch series converts the OMAP Dual Mode Timer into a >> platform driver. This involves using of hwmod structures and >> omap_device layer for OMAP2/3/4 dmtimers and generic >> linux platform device layer for OMAP1. >> >> As a result of this patch series the dmtimer platform driver >> resides in arch/arm/plat-omap directory and arch specific >> implementations and device registerations reside in >> arch/arm/mach-omap1 and arch/arm/mach-omap2 for OMAP1 >> and OMAP2 PLUS respectively. > > Hi Thara, > > The Dual timer terminology is not used anymore since 2420. > It was replaced by gptimer and will be simplified going forward > using timer. This IP is almost the same since 1610, but will have 3 > different names. > It might be the good opportunity to align the names? If we were to align the names, what should be the "aligned" name? gptimer or timer? I tend to prefer gptimer as 'timer' is rather ambiguous in this context. For now, we could leave the names of all the functions and structs as 'dm_timer', but at least this serious could name the new files and the platform devices with the new name. At the end of the series, one final patch to s/dm_timer/new_beautiful_name/ would be an easy patch. Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS 2010-06-03 22:20 ` Kevin Hilman @ 2010-06-03 22:29 ` Benoit 2010-06-03 23:46 ` Kevin Hilman 0 siblings, 1 reply; 22+ messages in thread From: Benoit @ 2010-06-03 22:29 UTC (permalink / raw) To: Kevin Hilman Cc: Gopinath, Thara, linux-omap@vger.kernel.org, tony@atomide.com, Sawant, Anand On 6/4/2010 12:20 AM, Kevin Hilman wrote: > Benoit Cousson<b-cousson@ti.com> writes: > >> On 5/29/2010 4:37 PM, Gopinath, Thara wrote: >>> This patch series converts the OMAP Dual Mode Timer into a >>> platform driver. This involves using of hwmod structures and >>> omap_device layer for OMAP2/3/4 dmtimers and generic >>> linux platform device layer for OMAP1. >>> >>> As a result of this patch series the dmtimer platform driver >>> resides in arch/arm/plat-omap directory and arch specific >>> implementations and device registerations reside in >>> arch/arm/mach-omap1 and arch/arm/mach-omap2 for OMAP1 >>> and OMAP2 PLUS respectively. >> >> Hi Thara, >> >> The Dual timer terminology is not used anymore since 2420. >> It was replaced by gptimer and will be simplified going forward >> using timer. This IP is almost the same since 1610, but will have 3 >> different names. >> It might be the good opportunity to align the names? > > If we were to align the names, what should be the "aligned" name? > gptimer or timer? I tend to prefer gptimer as 'timer' is rather > ambiguous in this context. Arrrgs, too late... After many discussions we agreed on 'timer' with HW folks. Neither dmtimer not gptimer bring any useful information. Timer that are not regular timers will have some prefix / postfix like wd_ for the watchdog. And synctimer not being a timer at all will then be renamed counter. Why do you think 'timer' is ambiguous? Benoit > For now, we could leave the names of all the functions and structs as > 'dm_timer', but at least this serious could name the new files and the > platform devices with the new name. At the end of the series, one > final patch to s/dm_timer/new_beautiful_name/ would be an easy patch. > > Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS 2010-06-03 22:29 ` Benoit @ 2010-06-03 23:46 ` Kevin Hilman 0 siblings, 0 replies; 22+ messages in thread From: Kevin Hilman @ 2010-06-03 23:46 UTC (permalink / raw) To: Benoit Cc: Gopinath, Thara, linux-omap@vger.kernel.org, tony@atomide.com, Sawant, Anand Benoit <b-cousson@ti.com> writes: > On 6/4/2010 12:20 AM, Kevin Hilman wrote: >> Benoit Cousson<b-cousson@ti.com> writes: >> >>> On 5/29/2010 4:37 PM, Gopinath, Thara wrote: >>>> This patch series converts the OMAP Dual Mode Timer into a >>>> platform driver. This involves using of hwmod structures and >>>> omap_device layer for OMAP2/3/4 dmtimers and generic >>>> linux platform device layer for OMAP1. >>>> >>>> As a result of this patch series the dmtimer platform driver >>>> resides in arch/arm/plat-omap directory and arch specific >>>> implementations and device registerations reside in >>>> arch/arm/mach-omap1 and arch/arm/mach-omap2 for OMAP1 >>>> and OMAP2 PLUS respectively. >>> >>> Hi Thara, >>> >>> The Dual timer terminology is not used anymore since 2420. >>> It was replaced by gptimer and will be simplified going forward >>> using timer. This IP is almost the same since 1610, but will have 3 >>> different names. >>> It might be the good opportunity to align the names? >> >> If we were to align the names, what should be the "aligned" name? >> gptimer or timer? I tend to prefer gptimer as 'timer' is rather >> ambiguous in this context. > > Arrrgs, too late... After many discussions we agreed on 'timer' with > HW folks. Neither dmtimer not gptimer bring any useful > information. Timer that are not regular timers will have some prefix / > postfix like wd_ for the watchdog. And synctimer not being a timer at > all will then be renamed counter. > Why do you think 'timer' is ambiguous? Maybe vague is better than ambiguous. Timer is an all-encompasing term for all the things you mentioned above, as well as ARM-generic timers presumably coming down the road. I guess since this is in OMAP-specific code, 'timer' is fine, but it doesn't feel right. Maybe we need to call it 'omap_timer'.? Kevin ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS 2010-05-29 14:37 [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Thara Gopinath 2010-05-29 14:37 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Thara Gopinath 2010-05-30 22:11 ` [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Benoit Cousson @ 2010-06-01 9:37 ` Tony Lindgren 2 siblings, 0 replies; 22+ messages in thread From: Tony Lindgren @ 2010-06-01 9:37 UTC (permalink / raw) To: Thara Gopinath; +Cc: linux-omap, khilman, sawant * Thara Gopinath <thara@ti.com> [100529 17:31]: > This patch series converts the OMAP Dual Mode Timer into a > platform driver. This involves using of hwmod structures and > omap_device layer for OMAP2/3/4 dmtimers and generic > linux platform device layer for OMAP1. > > As a result of this patch series the dmtimer platform driver > resides in arch/arm/plat-omap directory and arch specific > implementations and device registerations reside in > arch/arm/mach-omap1 and arch/arm/mach-omap2 for OMAP1 > and OMAP2 PLUS respectively. > > This patch series has been compile tested for OMAP1 using > omap_1610_h2_defconfig, compile tested for OMAP2 using > omap3_defconfig and boot and sanity tested for OMAP3/OMAP4 > again using omap3_defconfig. Boot testing has been done > on OMAP3430 SDP and OMAP4430 SDP boards. All testing has > been done on origin/origin/pm-wip/hwmods-omap4 branch off > Kevin Hilman's tree as these patches have dependencies on > runtime pm API's and OMAP4 autogenerated hwmod data base. > > It would be great if somebody could test these patches on OMAP1 > and OMAP2 platforms. Looks good, but the problem I see with this series is that it's not an incremental set of patches where each patch can be verified to compile and work for all the omaps. Please restructure your series so each patch keeps working and we end up with the actual timer code under plat-omap you should be able to add all the hwmod and platform data, then add a patch that changes the timer code to use the platform data as the last patch. Regards, Tony ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2010-06-03 23:46 UTC | newest] Thread overview: 22+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-05-29 14:37 [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Thara Gopinath 2010-05-29 14:37 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Thara Gopinath 2010-05-29 14:37 ` [PATCH 2/9] OMAP1: Dual mode timer device registration Thara Gopinath 2010-05-29 14:37 ` [PATCH 3/9] OMAP2/3/4 : " Thara Gopinath 2010-05-29 14:37 ` [PATCH 4/9] OMAP2: Support for early " Thara Gopinath 2010-05-29 14:37 ` [PATCH 5/9] OMAP2/3/4: Adding device names to dmtimer fclk nodes Thara Gopinath 2010-05-29 14:37 ` [PATCH 6/9] OMAP3: Add hwmod data for OMAP3 dual mode timers Thara Gopinath 2010-05-29 14:37 ` [PATCH 7/9] OMAP2: Add hwmod data for OMAP2420 " Thara Gopinath 2010-05-29 14:37 ` [PATCH 8/9] OMAP2: Add hwmod data for OMAP2430 " Thara Gopinath 2010-05-29 14:37 ` [PATCH 9/9] OMAP4: Changing dmtimer1 fclk name Thara Gopinath 2010-06-03 23:19 ` [PATCH 4/9] OMAP2: Support for early device registration Kevin Hilman 2010-05-30 23:02 ` [PATCH 3/9] OMAP2/3/4 : Dual mode timer " Benoit Cousson 2010-06-01 9:20 ` Tony Lindgren 2010-06-03 9:30 ` Gopinath, Thara 2010-06-03 23:18 ` Kevin Hilman 2010-06-03 23:24 ` Kevin Hilman 2010-06-03 19:47 ` [PATCH 1/9] OMAP: Convert dual mode timer into a platform driver Kevin Hilman 2010-05-30 22:11 ` [PATCH 0/9] OMAP: DMTIMER: Convert platform driver so as to make use of hwmod + omap device framework for OMAP2 PLUS Benoit Cousson 2010-06-03 22:20 ` Kevin Hilman 2010-06-03 22:29 ` Benoit 2010-06-03 23:46 ` Kevin Hilman 2010-06-01 9:37 ` Tony Lindgren
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