[RFC][PATCH 0/8] OMAP: DSS2: Overlay Manager LCD2 support in DISPC

[RFC][PATCH 0/8] OMAP: DSS2: Overlay Manager LCD2 support in DISPC

[Archit Taneja]

From: Semwal, Sumit <sumit.semwal@ti.com>

This patch series incorporates changes in DSS2 to enable
omap_dss_device instances to use the new Overlay Manager LCD2 in
DISPC.

On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. This
channel's video port is a source port for RFBI, DSI2 and DPI. The
Primary channel's video port is connected to RFBI and DSI1.

There is a set of regsiters for LCD2 channel similar to the existing
LCD channel, like DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so
on.

In order to decide which LCD Overlay Manager to configure(LCD/LCD2),
there is a need for the omap_dss_device instances to tell the interface
drivers(DSI, DPI, RFBI etc) which LCD channel they want to connect to, so
that the corresponding registers get configured. Therefore, a new
enum omap_channel member is introduced to omap_dss_device.

This design was made keeping in mind the possible addition of more
Overlay Managers in future OMAPs, this code is also backward compatible
with OMAP3 as omap_dss_device instances in OMAP3 will stick only with
OMAP_DSS_CHANNEL_LCD.

Sumit Semwal (7):
  OMAP: DSS2: Overlay Manager LCD2 changes in dispay.h
  OMAP: DSS2: Add new Overlay Manager
  OMAP: DSS2: Modify dss_recheck_connections
  OMAP: DSS2: OMAP4 Secondary LCD Channel DISPC Registers
  OMAP: DSS2: Secondary LCD Channel in DISPC functions
  OMAP: DSS2: Secondary LCD Channel DISPC IRQs
  OMAP: DSS2: Interface driver changes for Secondary LCD Channel

Mayuresh Janorkar (1)
  OMAP: DSS2: Context Save and Restore of DISPC registers for Secondary LCD

 arch/arm/plat-omap/include/plat/display.h |    7 +
 drivers/video/omap2/dss/core.c            |    2 +-
 drivers/video/omap2/dss/dispc.c           |  478 +++++++++++++++++++++++------
 drivers/video/omap2/dss/dpi.c             |   38 ++-
 drivers/video/omap2/dss/dsi.c             |   22 +-
 drivers/video/omap2/dss/dss.h             |   37 ++-
 drivers/video/omap2/dss/manager.c         |   87 ++++--
 drivers/video/omap2/dss/overlay.c         |   14 +-
 drivers/video/omap2/dss/rfbi.c            |   21 +-
 drivers/video/omap2/dss/sdi.c             |   22 +-
 10 files changed, 536 insertions(+), 192 deletions(-)
--

[RFC][PATCH 1/8] OMAP: DSS2: Overlay Manager LCD2 changes in dispay.h

[Archit Taneja]

From: Sumit Semwal <sumit.semwal@ti.com>

Overlay Manager LCD2 changes in dispay.h

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 arch/arm/plat-omap/include/plat/display.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 8bd15bd..c3643f5
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -64,6 +64,7 @@ enum omap_plane {
 enum omap_channel {
 	OMAP_DSS_CHANNEL_LCD	= 0,
 	OMAP_DSS_CHANNEL_DIGIT	= 1,
+	OMAP_DSS_CHANNEL_LCD2   = 2,
 };
 
 enum omap_color_mode {
@@ -173,6 +174,7 @@ enum omap_dss_display_state {
 enum omap_dss_overlay_managers {
 	OMAP_DSS_OVL_MGR_LCD,
 	OMAP_DSS_OVL_MGR_TV,
+	OMAP_DSS_OVL_MGR_LCD2,
 };
 
 enum omap_dss_rotation_type {
@@ -462,6 +464,7 @@ struct omap_dss_device {
 	struct omap_overlay_manager *manager;
 
 	enum omap_dss_display_state state;
+	enum omap_channel channel;
 
 	/* platform specific  */
 	int (*platform_enable)(struct omap_dss_device *dssdev);
-- 
1.6.3.3

[PATCH] [RFC][PATCH 2/8] OMAP: DSS2: Add new Overlay Manager

[Archit Taneja]

From: Sumit Semwal <sumit.semwal@ti.com>

Add new Overlay Manager in manager.c, make secondary channel changes
and update supported displays for the managers in OMAP4

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 drivers/video/omap2/dss/manager.c |   54 ++++++++++++++++++++++---------------
 1 files changed, 32 insertions(+), 22 deletions(-)

diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 6a649ab..2636b7f
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -34,6 +34,8 @@
 
 #include "dss.h"
 
+#define MAX_DSS_MANAGERS (cpu_is_omap44xx() ? 3 : 2)
+
 static int num_managers;
 static struct list_head manager_list;
 
@@ -449,7 +451,7 @@ struct manager_cache_data {
 static struct {
 	spinlock_t lock;
 	struct overlay_cache_data overlay_cache[3];
-	struct manager_cache_data manager_cache[2];
+	struct manager_cache_data manager_cache[3];
 
 	bool irq_enabled;
 } dss_cache;
@@ -531,10 +533,9 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
 
 	if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
 		return 0;
-
+	channel = mgr->device->channel;
 	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
 		irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
-		channel = OMAP_DSS_CHANNEL_DIGIT;
 	} else {
 		if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
 			enum omap_dss_update_mode mode;
@@ -546,7 +547,6 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
 		} else {
 			irq = DISPC_IRQ_VSYNC;
 		}
-		channel = OMAP_DSS_CHANNEL_LCD;
 	}
 
 	mc = &dss_cache.manager_cache[mgr->id];
@@ -604,13 +604,13 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
 		return 0;
 
 	dssdev = ovl->manager->device;
+	channel = dssdev->channel;
 
 	if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
 		return 0;
 
 	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
 		irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
-		channel = OMAP_DSS_CHANNEL_DIGIT;
 	} else {
 		if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
 			enum omap_dss_update_mode mode;
@@ -622,7 +622,6 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
 		} else {
 			irq = DISPC_IRQ_VSYNC;
 		}
-		channel = OMAP_DSS_CHANNEL_LCD;
 	}
 
 	oc = &dss_cache.overlay_cache[ovl->id];
@@ -841,7 +840,8 @@ static int configure_overlay(enum omap_plane plane)
 			c->rotation_type,
 			c->rotation,
 			c->mirror,
-			c->global_alpha);
+			c->global_alpha,
+			c->channel);
 
 	if (r) {
 		/* this shouldn't happen */
@@ -883,20 +883,20 @@ static int configure_dispc(void)
 	struct overlay_cache_data *oc;
 	struct manager_cache_data *mc;
 	const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
-	const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
+	const int num_mgrs = MAX_DSS_MANAGERS;
 	int i;
 	int r;
-	bool mgr_busy[2];
-	bool mgr_go[2];
+	bool mgr_busy[MAX_DSS_MANAGERS];
+	bool mgr_go[MAX_DSS_MANAGERS];
 	bool busy;
 
 	r = 0;
 	busy = false;
 
-	mgr_busy[0] = dispc_go_busy(0);
-	mgr_busy[1] = dispc_go_busy(1);
-	mgr_go[0] = false;
-	mgr_go[1] = false;
+	for (i = 0; i < num_mgrs; i++) {
+		mgr_busy[i] = dispc_go_busy(i);
+		mgr_go[i] = false;
+	}
 
 	/* Commit overlay settings */
 	for (i = 0; i < num_ovls; ++i) {
@@ -1122,7 +1122,7 @@ void dss_start_update(struct omap_dss_device *dssdev)
 	struct manager_cache_data *mc;
 	struct overlay_cache_data *oc;
 	const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
-	const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
+	const int num_mgrs = MAX_DSS_MANAGERS;
 	struct omap_overlay_manager *mgr;
 	int i;
 
@@ -1154,10 +1154,10 @@ static void dss_apply_irq_handler(void *data, u32 mask)
 	const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
 	const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
 	int i, r;
-	bool mgr_busy[2];
+	bool mgr_busy[MAX_DSS_MANAGERS];
 
-	mgr_busy[0] = dispc_go_busy(0);
-	mgr_busy[1] = dispc_go_busy(1);
+	for (i = 0; i < num_mgrs; i++)
+		mgr_busy[i] = dispc_go_busy(i);
 
 	spin_lock(&dss_cache.lock);
 
@@ -1461,7 +1461,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
 
 	num_managers = 0;
 
-	for (i = 0; i < 2; ++i) {
+	for (i = 0; i < MAX_DSS_MANAGERS; ++i) {
 		struct omap_overlay_manager *mgr;
 		mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
 
@@ -1471,15 +1471,25 @@ int dss_init_overlay_managers(struct platform_device *pdev)
 		case 0:
 			mgr->name = "lcd";
 			mgr->id = OMAP_DSS_CHANNEL_LCD;
-			mgr->supported_displays =
-				OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
-				OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
+			mgr->supported_displays = OMAP_DISPLAY_TYPE_DBI |
+				OMAP_DISPLAY_TYPE_DSI;
+			if (cpu_is_omap34xx())
+				mgr->supported_displays |=
+					OMAP_DISPLAY_TYPE_DPI |
+					OMAP_DISPLAY_TYPE_SDI;
 			break;
 		case 1:
 			mgr->name = "tv";
 			mgr->id = OMAP_DSS_CHANNEL_DIGIT;
 			mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
 			break;
+		case 2:
+			mgr->name = "2lcd";
+			mgr->id = OMAP_DSS_CHANNEL_LCD2;
+			mgr->supported_displays =
+				OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
+				OMAP_DISPLAY_TYPE_DSI;
+			break;
 		}
 
 		mgr->set_device = &omap_dss_set_device;
-- 
1.5.4.7

[RFC][PATCH 3/8] OMAP: DSS2: Modify dss_recheck_connections

[Archit Taneja]

From: Sumit Semwal <sumit.semwal@ti.com>

The addition of the new 2lcd manager requires modifications in the
dss_recheck_connections patch, this function behaves the same if
the 2lcd manager doesn't exist

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 drivers/video/omap2/dss/overlay.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index 8233658..c7ad1d1
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -627,12 +627,22 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
 	int i;
 	struct omap_overlay_manager *lcd_mgr;
 	struct omap_overlay_manager *tv_mgr;
+	struct omap_overlay_manager *lcd2_mgr = NULL;
 	struct omap_overlay_manager *mgr = NULL;
 
 	lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
 	tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
-
-	if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
+	if (cpu_is_omap44xx())
+		lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD2);
+
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
+		if (!lcd2_mgr->device || force) {
+			if (lcd2_mgr->device)
+				lcd2_mgr->unset_device(lcd2_mgr);
+			lcd2_mgr->set_device(lcd2_mgr, dssdev);
+			mgr = lcd2_mgr;
+		}
+	} else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
 		if (!lcd_mgr->device || force) {
 			if (lcd_mgr->device)
 				lcd_mgr->unset_device(lcd_mgr);
-- 
1.6.3.3

[RFC][PATCH 4/8] OMAP: DSS2: OMAP4 Secondary LCD Channel DISPC Registers

[Archit Taneja]

From: Semwal, Sumit <sumit.semwal@ti.com>

Introduce OMAP4 DISPC base address and Secondary LCD Channel registers, use them
in register dumps.

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 drivers/video/omap2/dss/dispc.c |   42 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 41 insertions(+), 1 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 5ecdc00..08b36d6
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -41,9 +41,13 @@
 #include "dss.h"
 
 /* DISPC */
+#ifdef CONFIG_ARCH_OMAP4
+#define DISPC_BASE			0x58001000
+#define DISPC_SZ_REGS			SZ_16K
+#else
 #define DISPC_BASE			0x48050400
-
 #define DISPC_SZ_REGS			SZ_1K
+#endif
 
 struct dispc_reg { u16 idx; };
 
@@ -68,6 +72,7 @@ struct dispc_reg { u16 idx; };
 #define DISPC_TIMING_V			DISPC_REG(0x0068)
 #define DISPC_POL_FREQ			DISPC_REG(0x006C)
 #define DISPC_DIVISOR			DISPC_REG(0x0070)
+#define DISPC_DIVISOR1			DISPC_REG(0x0804)
 #define DISPC_GLOBAL_ALPHA		DISPC_REG(0x0074)
 #define DISPC_SIZE_DIG			DISPC_REG(0x0078)
 #define DISPC_SIZE_LCD			DISPC_REG(0x007C)
@@ -131,6 +136,23 @@ struct dispc_reg { u16 idx; };
 					 DISPC_IRQ_SYNC_LOST | \
 					 DISPC_IRQ_SYNC_LOST_DIGIT)
 
+/* OMAP4 new global registers */
+#define DISPC_CONTROL2		DISPC_REG(0x0238)
+#define DISPC_DEFAULT_COLOR2		DISPC_REG(0x03AC)
+#define DISPC_TRANS_COLOR2		DISPC_REG(0x03B0)
+#define DISPC_CPR2_COEF_B		DISPC_REG(0x03B4)
+#define DISPC_CPR2_COEF_G		DISPC_REG(0x03B8)
+#define DISPC_CPR2_COEF_R		DISPC_REG(0x03BC)
+#define DISPC_DATA2_CYCLE1		DISPC_REG(0x03C0)
+#define DISPC_DATA2_CYCLE2		DISPC_REG(0x03C4)
+#define DISPC_DATA2_CYCLE3		DISPC_REG(0x03C8)
+#define DISPC_SIZE_LCD2		DISPC_REG(0x03CC)
+#define DISPC_TIMING_H2		DISPC_REG(0x0400)
+#define DISPC_TIMING_V2		DISPC_REG(0x0404)
+#define DISPC_POL_FREQ2		DISPC_REG(0x0408)
+#define DISPC_DIVISOR2		DISPC_REG(0x040C)
+#define DISPC_CONFIG2		DISPC_REG(0x0620)
+
 #define DISPC_MAX_NR_ISRS		8
 
 struct omap_dispc_isr_data {
@@ -2361,6 +2383,24 @@ void dispc_dump_regs(struct seq_file *s)
 	DUMPREG(DISPC_SIZE_DIG);
 	DUMPREG(DISPC_SIZE_LCD);
 
+	/* OMAP4 LCD2 channel registers*/
+	if (cpu_is_omap44xx()) {
+		DUMPREG(DISPC_CONTROL2);
+		DUMPREG(DISPC_DEFAULT_COLOR2);
+		DUMPREG(DISPC_TRANS_COLOR2);
+		DUMPREG(DISPC_CPR2_COEF_B);
+		DUMPREG(DISPC_CPR2_COEF_G);
+		DUMPREG(DISPC_CPR2_COEF_R);
+		DUMPREG(DISPC_DATA2_CYCLE1);
+		DUMPREG(DISPC_DATA2_CYCLE2);
+		DUMPREG(DISPC_DATA2_CYCLE3);
+		DUMPREG(DISPC_SIZE_LCD2);
+		DUMPREG(DISPC_TIMING_H2);
+		DUMPREG(DISPC_TIMING_V2);
+		DUMPREG(DISPC_POL_FREQ2);
+		DUMPREG(DISPC_DIVISOR2);
+		DUMPREG(DISPC_CONFIG2);
+	}
 	DUMPREG(DISPC_GFX_BA0);
 	DUMPREG(DISPC_GFX_BA1);
 	DUMPREG(DISPC_GFX_POSITION);
-- 
1.6.3.3

[RFC][PATCH 5/8] OMAP: DSS2: Secondary LCD Channel in DISPC functions

[Archit Taneja]

From: Sumit Semwal <sumit.semwal@ti.com>

Introduce the new enum channel as a parameter in all dispc functions
used by interface drivers(dsi, sdi etc) in order to differentiate
between the 2 channels

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 drivers/video/omap2/dss/dispc.c |  326 ++++++++++++++++++++++++++++-----------
 drivers/video/omap2/dss/dss.h   |   29 ++--
 2 files changed, 253 insertions(+), 102 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 08b36d6..22fd2c2
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -521,12 +521,17 @@ bool dispc_go_busy(enum omap_channel channel)
 {
 	int bit;
 
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if ((!cpu_is_omap44xx()) && (channel == OMAP_DSS_CHANNEL_LCD))
+		bit = 5; /* GOLCD */
+	else if (cpu_is_omap44xx() && (channel != OMAP_DSS_CHANNEL_DIGIT))
 		bit = 5; /* GOLCD */
 	else
 		bit = 6; /* GODIGIT */
 
-	return REG_GET(DISPC_CONTROL, bit, bit) == 1;
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2))
+		return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
+	else
+		return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 }
 
 void dispc_go(enum omap_channel channel)
@@ -535,28 +540,47 @@ void dispc_go(enum omap_channel channel)
 
 	enable_clocks(1);
 
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if ((channel == OMAP_DSS_CHANNEL_LCD) ||
+			(channel == OMAP_DSS_CHANNEL_LCD2))
 		bit = 0; /* LCDENABLE */
 	else
 		bit = 1; /* DIGITALENABLE */
 
 	/* if the channel is not enabled, we don't need GO */
-	if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
-		goto end;
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2)) {
+		if (REG_GET(DISPC_CONTROL2, bit, bit) == 0)
+			goto end;
+	} else {
+		if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
+			goto end;
+	}
 
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if ((channel == OMAP_DSS_CHANNEL_LCD) ||
+			(channel == OMAP_DSS_CHANNEL_LCD2))
 		bit = 5; /* GOLCD */
 	else
 		bit = 6; /* GODIGIT */
 
-	if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
-		DSSERR("GO bit not down for channel %d\n", channel);
-		goto end;
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2)) {
+		if (REG_GET(DISPC_CONTROL2, bit, bit) == 1) {
+			DSSERR("GO bit not down for channel %d\n", channel);
+			goto end;
+		}
+	} else {
+		if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
+			DSSERR("GO bit not down for channel %d\n", channel);
+			goto end;
+		}
 	}
 
-	DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
+	DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
+		channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT");
+
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2))
+		REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 
-	REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 end:
 	enable_clocks(0);
 }
@@ -898,6 +922,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
 {
 	int shift;
 	u32 val;
+	int chan = 0, chan2 = 0;
 
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -913,7 +938,30 @@ static void _dispc_set_channel_out(enum omap_plane plane,
 	}
 
 	val = dispc_read_reg(dispc_reg_att[plane]);
-	val = FLD_MOD(val, channel, shift, shift);
+	if (cpu_is_omap44xx()) {
+		switch (channel) {
+
+		case OMAP_DSS_CHANNEL_LCD:
+			chan = 0;
+			chan2 = 0;
+			break;
+		case OMAP_DSS_CHANNEL_DIGIT:
+			chan = 1;
+			chan2 = 0;
+			break;
+		case OMAP_DSS_CHANNEL_LCD2:
+			chan = 0;
+			chan2 = 1;
+			break;
+		default:
+			BUG();
+		}
+
+		val = FLD_MOD(val, chan, shift, shift);
+		val = FLD_MOD(val, chan2, 31, 30);
+	} else {
+		val = FLD_MOD(val, channel, shift, shift);
+	}
 	dispc_write_reg(dispc_reg_att[plane], val);
 }
 
@@ -970,13 +1018,16 @@ void dispc_enable_replication(enum omap_plane plane, bool enable)
 	enable_clocks(0);
 }
 
-void dispc_set_lcd_size(u16 width, u16 height)
+void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 {
 	u32 val;
 	BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 	enable_clocks(1);
-	dispc_write_reg(DISPC_SIZE_LCD, val);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		dispc_write_reg(DISPC_SIZE_LCD2, val);
+	else
+		dispc_write_reg(DISPC_SIZE_LCD, val);
 	enable_clocks(0);
 }
 
@@ -1471,12 +1522,13 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
 	}
 }
 
-static unsigned long calc_fclk_five_taps(u16 width, u16 height,
-		u16 out_width, u16 out_height, enum omap_color_mode color_mode)
+static unsigned long calc_fclk_five_taps(enum omap_channel channel,
+		u16 width, u16 height, u16 out_width, u16 out_height,
+		enum omap_color_mode color_mode)
 {
 	u32 fclk = 0;
 	/* FIXME venc pclk? */
-	u64 tmp, pclk = dispc_pclk_rate();
+	u64 tmp, pclk = dispc_pclk_rate(channel);
 
 	if (height > out_height) {
 		/* FIXME get real display PPL */
@@ -1508,8 +1560,8 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
 	return fclk;
 }
 
-static unsigned long calc_fclk(u16 width, u16 height,
-		u16 out_width, u16 out_height)
+static unsigned long calc_fclk(enum omap_channel channel, u16 width,
+			u16 height, u16 out_width, u16 out_height)
 {
 	unsigned int hf, vf;
 
@@ -1533,7 +1585,7 @@ static unsigned long calc_fclk(u16 width, u16 height,
 		vf = 1;
 
 	/* FIXME venc pclk? */
-	return dispc_pclk_rate() * vf * hf;
+	return dispc_pclk_rate(channel) * vf * hf;
 }
 
 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
@@ -1552,7 +1604,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		bool ilace,
 		enum omap_dss_rotation_type rotation_type,
 		u8 rotation, int mirror,
-		u8 global_alpha)
+		u8 global_alpha,
+		enum omap_channel channel)
 {
 	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
 	bool five_taps = 0;
@@ -1648,7 +1701,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		five_taps = height > out_height * 2;
 
 		if (!five_taps) {
-			fclk = calc_fclk(width, height,
+			fclk = calc_fclk(channel, width, height,
 					out_width, out_height);
 
 			/* Try 5-tap filter if 3-tap fclk is too high */
@@ -1663,7 +1716,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		}
 
 		if (five_taps)
-			fclk = calc_fclk_five_taps(width, height,
+			fclk = calc_fclk_five_taps(channel, width, height,
 					out_width, out_height, color_mode);
 
 		DSSDBG("required fclk rate = %lu Hz\n", fclk);
@@ -1752,12 +1805,16 @@ static void dispc_disable_isr(void *data, u32 mask)
 	complete(compl);
 }
 
-static void _enable_lcd_out(bool enable)
+static void _enable_lcd_out(enum omap_channel channel, bool enable)
 {
-	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
 }
 
-static void dispc_enable_lcd_out(bool enable)
+
+static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
 {
 	struct completion frame_done_completion;
 	bool is_on;
@@ -1781,7 +1838,7 @@ static void dispc_enable_lcd_out(bool enable)
 			DSSERR("failed to register FRAMEDONE isr\n");
 	}
 
-	_enable_lcd_out(enable);
+	_enable_lcd_out(channel, enable);
 
 	if (!enable && is_on) {
 		if (!wait_for_completion_timeout(&frame_done_completion,
@@ -1870,7 +1927,9 @@ static void dispc_enable_digit_out(bool enable)
 
 bool dispc_is_channel_enabled(enum omap_channel channel)
 {
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if (channel == OMAP_DSS_CHANNEL_LCD2)
+		return !!REG_GET(DISPC_CONTROL2, 0, 0);
+	else if (channel == OMAP_DSS_CHANNEL_LCD)
 		return !!REG_GET(DISPC_CONTROL, 0, 0);
 	else if (channel == OMAP_DSS_CHANNEL_DIGIT)
 		return !!REG_GET(DISPC_CONTROL, 1, 1);
@@ -1880,8 +1939,9 @@ bool dispc_is_channel_enabled(enum omap_channel channel)
 
 void dispc_enable_channel(enum omap_channel channel, bool enable)
 {
-	if (channel == OMAP_DSS_CHANNEL_LCD)
-		dispc_enable_lcd_out(enable);
+	if (channel == OMAP_DSS_CHANNEL_LCD ||
+		channel == OMAP_DSS_CHANNEL_LCD2)
+		dispc_enable_lcd_out(channel, enable);
 	else if (channel == OMAP_DSS_CHANNEL_DIGIT)
 		dispc_enable_digit_out(enable);
 	else
@@ -1890,6 +1950,9 @@ void dispc_enable_channel(enum omap_channel channel, bool enable)
 
 void dispc_lcd_enable_signal_polarity(bool act_high)
 {
+	if (cpu_is_omap44xx())
+		return;
+
 	enable_clocks(1);
 	REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
 	enable_clocks(0);
@@ -1897,6 +1960,9 @@ void dispc_lcd_enable_signal_polarity(bool act_high)
 
 void dispc_lcd_enable_signal(bool enable)
 {
+	if (cpu_is_omap44xx())
+		return;
+
 	enable_clocks(1);
 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
 	enable_clocks(0);
@@ -1904,6 +1970,9 @@ void dispc_lcd_enable_signal(bool enable)
 
 void dispc_pck_free_enable(bool enable)
 {
+	if (cpu_is_omap44xx())
+		return;
+
 	enable_clocks(1);
 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
 	enable_clocks(0);
@@ -1917,7 +1986,8 @@ void dispc_enable_fifohandcheck(bool enable)
 }
 
 
-void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
+void dispc_set_lcd_display_type(enum omap_channel channel,
+				enum omap_lcd_display_type type)
 {
 	int mode;
 
@@ -1936,7 +2006,11 @@ void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
 	}
 
 	enable_clocks(1);
-	REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
+
 	enable_clocks(0);
 }
 
@@ -1947,12 +2021,10 @@ void dispc_set_loadmode(enum omap_dss_load_mode mode)
 	enable_clocks(0);
 }
 
-
 void dispc_set_default_color(enum omap_channel channel, u32 color)
 {
 	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
-				DISPC_DEFAULT_COLOR1 };
-
+				DISPC_DEFAULT_COLOR1, DISPC_DEFAULT_COLOR2 };
 	enable_clocks(1);
 	dispc_write_reg(def_reg[channel], color);
 	enable_clocks(0);
@@ -1961,11 +2033,12 @@ void dispc_set_default_color(enum omap_channel channel, u32 color)
 u32 dispc_get_default_color(enum omap_channel channel)
 {
 	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
-				DISPC_DEFAULT_COLOR1 };
+				DISPC_DEFAULT_COLOR1, DISPC_DEFAULT_COLOR2 };
 	u32 l;
 
-	BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
-	       channel != OMAP_DSS_CHANNEL_LCD);
+	if (!cpu_is_omap44xx())
+		BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
+			channel != OMAP_DSS_CHANNEL_LCD);
 
 	enable_clocks(1);
 	l = dispc_read_reg(def_reg[channel]);
@@ -1979,10 +2052,13 @@ void dispc_set_trans_key(enum omap_channel ch,
 		u32 trans_key)
 {
 	const struct dispc_reg tr_reg[] = {
-		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
+		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1,
+		DISPC_TRANS_COLOR2};
 
 	enable_clocks(1);
-	if (ch == OMAP_DSS_CHANNEL_LCD)
+	if (ch == OMAP_DSS_CHANNEL_LCD2)
+		REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
+	else if (ch == OMAP_DSS_CHANNEL_LCD)
 		REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
 	else /* OMAP_DSS_CHANNEL_DIGIT */
 		REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
@@ -1996,11 +2072,14 @@ void dispc_get_trans_key(enum omap_channel ch,
 		u32 *trans_key)
 {
 	const struct dispc_reg tr_reg[] = {
-		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
+		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1,
+		DISPC_TRANS_COLOR2 };
 
 	enable_clocks(1);
 	if (type) {
-		if (ch == OMAP_DSS_CHANNEL_LCD)
+		if (ch == OMAP_DSS_CHANNEL_LCD2)
+			*type = REG_GET(DISPC_CONFIG2, 11, 11);
+		else if (ch == OMAP_DSS_CHANNEL_LCD)
 			*type = REG_GET(DISPC_CONFIG, 11, 11);
 		else if (ch == OMAP_DSS_CHANNEL_DIGIT)
 			*type = REG_GET(DISPC_CONFIG, 13, 13);
@@ -2016,12 +2095,15 @@ void dispc_get_trans_key(enum omap_channel ch,
 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
 {
 	enable_clocks(1);
-	if (ch == OMAP_DSS_CHANNEL_LCD)
+	if (ch == OMAP_DSS_CHANNEL_LCD2)
+		REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
+	else if (ch == OMAP_DSS_CHANNEL_LCD)
 		REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
 	else /* OMAP_DSS_CHANNEL_DIGIT */
 		REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
 	enable_clocks(0);
 }
+
 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
 {
 	if (cpu_is_omap24xx())
@@ -2053,13 +2135,13 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
 	return enabled;
 
 }
-
-
 bool dispc_trans_key_enabled(enum omap_channel ch)
 {
 	bool enabled;
 
 	enable_clocks(1);
+	if (ch == OMAP_DSS_CHANNEL_LCD2)
+		enabled = REG_GET(DISPC_CONFIG2, 10, 10);
 	if (ch == OMAP_DSS_CHANNEL_LCD)
 		enabled = REG_GET(DISPC_CONFIG, 10, 10);
 	else if (ch == OMAP_DSS_CHANNEL_DIGIT)
@@ -2072,7 +2154,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
 }
 
 
-void dispc_set_tft_data_lines(u8 data_lines)
+void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
 {
 	int code;
 
@@ -2095,11 +2177,15 @@ void dispc_set_tft_data_lines(u8 data_lines)
 	}
 
 	enable_clocks(1);
-	REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
+	if (channel == OMAP_DSS_CHANNEL_LCD2)
+		REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
 	enable_clocks(0);
 }
 
-void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
+void dispc_set_parallel_interface_mode(enum omap_channel channel,
+				enum omap_parallel_interface_mode mode)
 {
 	u32 l;
 	int stallmode;
@@ -2129,13 +2215,19 @@ void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
 
 	enable_clocks(1);
 
-	l = dispc_read_reg(DISPC_CONTROL);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		l = dispc_read_reg(DISPC_CONTROL2);
+		l = FLD_MOD(l, stallmode, 11, 11);
 
-	l = FLD_MOD(l, stallmode, 11, 11);
-	l = FLD_MOD(l, gpout0, 15, 15);
-	l = FLD_MOD(l, gpout1, 16, 16);
+		dispc_write_reg(DISPC_CONTROL2, l);
+	} else {
+		l = dispc_read_reg(DISPC_CONTROL);
+		l = FLD_MOD(l, stallmode, 11, 11);
+		l = FLD_MOD(l, gpout0, 15, 15);
+		l = FLD_MOD(l, gpout1, 16, 16);
 
-	dispc_write_reg(DISPC_CONTROL, l);
+		dispc_write_reg(DISPC_CONTROL, l);
+	}
 
 	enable_clocks(0);
 }
@@ -2171,8 +2263,8 @@ bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
 			timings->vfp, timings->vbp);
 }
 
-static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
-				   int vsw, int vfp, int vbp)
+static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
+			int hfp, int hbp, int vsw, int vfp, int vbp)
 {
 	u32 timing_h, timing_v;
 
@@ -2191,13 +2283,19 @@ static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
 	}
 
 	enable_clocks(1);
-	dispc_write_reg(DISPC_TIMING_H, timing_h);
-	dispc_write_reg(DISPC_TIMING_V, timing_v);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		dispc_write_reg(DISPC_TIMING_H2, timing_h);
+		dispc_write_reg(DISPC_TIMING_V2, timing_v);
+	} else {
+		dispc_write_reg(DISPC_TIMING_H, timing_h);
+		dispc_write_reg(DISPC_TIMING_V, timing_v);
+	}
 	enable_clocks(0);
 }
 
 /* change name to mode? */
-void dispc_set_lcd_timings(struct omap_video_timings *timings)
+void dispc_set_lcd_timings(enum omap_channel channel,
+				struct omap_video_timings *timings)
 {
 	unsigned xtot, ytot;
 	unsigned long ht, vt;
@@ -2207,10 +2305,11 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
 				timings->vfp, timings->vbp))
 		BUG();
 
-	_dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
-			timings->vsw, timings->vfp, timings->vbp);
+	_dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
+				timings->hbp, timings->vsw, timings->vfp,
+				timings->vbp);
 
-	dispc_set_lcd_size(timings->x_res, timings->y_res);
+	dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
 
 	xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
 	ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
@@ -2218,7 +2317,8 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
 	ht = (timings->pixel_clock * 1000) / xtot;
 	vt = (timings->pixel_clock * 1000) / xtot / ytot;
 
-	DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
+	DSSDBG("channel %u xres %u yres %u\n", channel, timings->x_res,
+						timings->y_res);
 	DSSDBG("pck %u\n", timings->pixel_clock);
 	DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
 			timings->hsw, timings->hfp, timings->hbp,
@@ -2227,21 +2327,30 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
 	DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
 }
 
-static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
+static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
+								u16 pck_div)
 {
 	BUG_ON(lck_div < 1);
 	BUG_ON(pck_div < 2);
 
 	enable_clocks(1);
-	dispc_write_reg(DISPC_DIVISOR,
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		dispc_write_reg(DISPC_DIVISOR2,
+			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
+	else
+		dispc_write_reg(DISPC_DIVISOR,
 			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
 	enable_clocks(0);
 }
 
-static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
+static void dispc_get_lcd_divisor(enum omap_channel channel,
+						int *lck_div, int *pck_div)
 {
 	u32 l;
-	l = dispc_read_reg(DISPC_DIVISOR);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		l = dispc_read_reg(DISPC_DIVISOR2);
+	else
+		l = dispc_read_reg(DISPC_DIVISOR);
 	*lck_div = FLD_GET(l, 23, 16);
 	*pck_div = FLD_GET(l, 7, 0);
 }
@@ -2261,13 +2370,15 @@ unsigned long dispc_fclk_rate(void)
 	return r;
 }
 
-unsigned long dispc_lclk_rate(void)
+unsigned long dispc_lclk_rate(enum omap_channel channel)
 {
 	int lcd;
 	unsigned long r;
 	u32 l;
-
-	l = dispc_read_reg(DISPC_DIVISOR);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		l = dispc_read_reg(DISPC_DIVISOR2);
+	else
+		l = dispc_read_reg(DISPC_DIVISOR);
 
 	lcd = FLD_GET(l, 23, 16);
 
@@ -2276,13 +2387,15 @@ unsigned long dispc_lclk_rate(void)
 	return r / lcd;
 }
 
-unsigned long dispc_pclk_rate(void)
+unsigned long dispc_pclk_rate(enum omap_channel channel)
 {
 	int lcd, pcd;
 	unsigned long r;
 	u32 l;
-
-	l = dispc_read_reg(DISPC_DIVISOR);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		l = dispc_read_reg(DISPC_DIVISOR2);
+	else
+		l = dispc_read_reg(DISPC_DIVISOR);
 
 	lcd = FLD_GET(l, 23, 16);
 	pcd = FLD_GET(l, 7, 0);
@@ -2298,7 +2411,7 @@ void dispc_dump_clocks(struct seq_file *s)
 
 	enable_clocks(1);
 
-	dispc_get_lcd_divisor(&lcd, &pcd);
+	dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
 
 	seq_printf(s, "- DISPC -\n");
 
@@ -2307,8 +2420,26 @@ void dispc_dump_clocks(struct seq_file *s)
 			"dss1_alwon_fclk" : "dsi1_pll_fclk");
 
 	seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
-	seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
-	seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
+	seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+			dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
+	seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+			dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
+
+	if (cpu_is_omap44xx()) {
+		dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
+
+		seq_printf(s, "- DISPC - LCD 2\n");
+
+		seq_printf(s, "dispc fclk source = %s\n",
+			 dss_get_dispc_clk_source() == 0 ?
+			 "dss1_alwon_fclk" : "dsi1_pll_fclk");
+
+		seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
+		seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+				dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
+		seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+				dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
+	}
 
 	enable_clocks(0);
 }
@@ -2518,8 +2649,9 @@ void dispc_dump_regs(struct seq_file *s)
 #undef DUMPREG
 }
 
-static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
-				bool ihs, bool ivs, u8 acbi, u8 acb)
+static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
+				bool ieo, bool ipc, bool ihs, bool ivs,
+				u8 acbi, u8 acb)
 {
 	u32 l = 0;
 
@@ -2536,13 +2668,17 @@ static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
 	l |= FLD_VAL(acb, 7, 0);
 
 	enable_clocks(1);
-	dispc_write_reg(DISPC_POL_FREQ, l);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		dispc_write_reg(DISPC_POL_FREQ2, l);
+	else
+		dispc_write_reg(DISPC_POL_FREQ, l);
 	enable_clocks(0);
 }
 
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
+void dispc_set_pol_freq(enum omap_channel channel,
+			enum omap_panel_config config, u8 acbi, u8 acb)
 {
-	_dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
+	_dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
 			(config & OMAP_DSS_LCD_RF) != 0,
 			(config & OMAP_DSS_LCD_IEO) != 0,
 			(config & OMAP_DSS_LCD_IPC) != 0,
@@ -2611,25 +2747,31 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 	return 0;
 }
 
-int dispc_set_clock_div(struct dispc_clock_info *cinfo)
+int dispc_set_clock_div(enum omap_channel channel,
+	struct dispc_clock_info *cinfo)
 {
 	DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
 	DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
 
-	dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
+	dispc_set_lcd_divisor(channel, cinfo->lck_div,
+		cinfo->pck_div);
 
 	return 0;
 }
 
-int dispc_get_clock_div(struct dispc_clock_info *cinfo)
+int dispc_get_clock_div(enum omap_channel channel,
+	struct dispc_clock_info *cinfo)
 {
 	unsigned long fck;
 
 	fck = dispc_fclk_rate();
-
-	cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
-	cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
-
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		cinfo->lck_div = REG_GET(DISPC_DIVISOR2, 23, 16);
+		cinfo->pck_div = REG_GET(DISPC_DIVISOR2, 7, 0);
+	} else {
+		cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
+		cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
+	}
 	cinfo->lck = fck / cinfo->lck_div;
 	cinfo->pck = cinfo->lck / cinfo->pck_div;
 
@@ -3199,17 +3341,18 @@ int dispc_setup_plane(enum omap_plane plane,
 		       enum omap_color_mode color_mode,
 		       bool ilace,
 		       enum omap_dss_rotation_type rotation_type,
-		       u8 rotation, bool mirror, u8 global_alpha)
+		       u8 rotation, bool mirror, u8 global_alpha,
+		       enum omap_channel channel)
 {
 	int r = 0;
 
 	DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
-	       "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
+	       "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
 	       plane, paddr, screen_width, pos_x, pos_y,
 	       width, height,
 	       out_width, out_height,
 	       ilace, color_mode,
-	       rotation, mirror);
+	       rotation, mirror, channel);
 
 	enable_clocks(1);
 
@@ -3221,7 +3364,8 @@ int dispc_setup_plane(enum omap_plane plane,
 			   color_mode, ilace,
 			   rotation_type,
 			   rotation, mirror,
-			   global_alpha);
+			   global_alpha,
+			   channel);
 
 	enable_clocks(0);
 
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 5c7940d..456c702
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -335,7 +335,7 @@ void dispc_lcd_enable_signal(bool enable);
 void dispc_pck_free_enable(bool enable);
 void dispc_enable_fifohandcheck(bool enable);
 
-void dispc_set_lcd_size(u16 width, u16 height);
+void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 void dispc_set_digit_size(u16 width, u16 height);
 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
@@ -359,7 +359,7 @@ int dispc_setup_plane(enum omap_plane plane,
 		      bool ilace,
 		      enum omap_dss_rotation_type rotation_type,
 		      u8 rotation, bool mirror,
-		      u8 global_alpha);
+		      u8 global_alpha, enum omap_channel channel);
 
 bool dispc_go_busy(enum omap_channel channel);
 void dispc_go(enum omap_channel channel);
@@ -368,9 +368,12 @@ bool dispc_is_channel_enabled(enum omap_channel channel);
 int dispc_enable_plane(enum omap_plane plane, bool enable);
 void dispc_enable_replication(enum omap_plane plane, bool enable);
 
-void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
-void dispc_set_tft_data_lines(u8 data_lines);
-void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
+void dispc_set_parallel_interface_mode(enum omap_channel channel,
+				enum omap_parallel_interface_mode mode);
+void dispc_set_tft_data_lines(enum omap_channel channel,
+						u8 data_lines);
+void dispc_set_lcd_display_type(enum omap_channel channel,
+				enum omap_lcd_display_type type);
 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 
 void dispc_set_default_color(enum omap_channel channel, u32 color);
@@ -387,17 +390,21 @@ bool dispc_trans_key_enabled(enum omap_channel ch);
 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 
 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
-void dispc_set_lcd_timings(struct omap_video_timings *timings);
+void dispc_set_lcd_timings(enum omap_channel channel,
+				struct omap_video_timings *timings);
 unsigned long dispc_fclk_rate(void);
-unsigned long dispc_lclk_rate(void);
-unsigned long dispc_pclk_rate(void);
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb);
+unsigned long dispc_lclk_rate(enum omap_channel channel);
+unsigned long dispc_pclk_rate(enum omap_channel channel);
+void dispc_set_pol_freq(enum omap_channel channel,
+			enum omap_panel_config config, u8 acbi, u8 acb);
 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 		struct dispc_clock_info *cinfo);
 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 		struct dispc_clock_info *cinfo);
-int dispc_set_clock_div(struct dispc_clock_info *cinfo);
-int dispc_get_clock_div(struct dispc_clock_info *cinfo);
+int dispc_set_clock_div(enum omap_channel channel,
+		struct dispc_clock_info *cinfo);
+int dispc_get_clock_div(enum omap_channel channel,
+		struct dispc_clock_info *cinfo);
 
 
 /* VENC */
-- 
1.6.3.3

[PATCH] [RFC][PATCH 6/8] OMAP: DSS2: Secondary LCD Channel DISPC IRQs

[Archit Taneja]

From: Sumit Semwal <sumit.semwal@ti.com>

Introduce Secondary Channel IRQS for dumps and error handling

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 arch/arm/plat-omap/include/plat/display.h |    4 ++
 drivers/video/omap2/dss/dispc.c           |   62 +++++++++++++++++++++++++++--
 drivers/video/omap2/dss/manager.c         |   33 +++++++++++-----
 3 files changed, 85 insertions(+), 14 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index c3643f5..cfcde7d
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -42,6 +42,10 @@
 #define DISPC_IRQ_SYNC_LOST		(1 << 14)
 #define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
 #define DISPC_IRQ_WAKEUP		(1 << 16)
+#define DISPC_IRQ_SYNC_LOST_2  (1 << 17)
+#define DISPC_IRQ_VSYNC2		(1 << 18)
+#define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
+#define DISPC_IRQ_FRAMEDONE2		(1 << 22)
 
 struct omap_dss_device;
 struct omap_overlay_manager;
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 22fd2c2..785b8c1
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -134,7 +134,9 @@ struct dispc_reg { u16 idx; };
 					 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 					 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 					 DISPC_IRQ_SYNC_LOST | \
-					 DISPC_IRQ_SYNC_LOST_DIGIT)
+					DISPC_IRQ_SYNC_LOST_DIGIT | \
+					(cpu_is_omap44xx() ? \
+					DISPC_IRQ_SYNC_LOST_2 : 0))
 
 /* OMAP4 new global registers */
 #define DISPC_CONTROL2		DISPC_REG(0x0238)
@@ -1819,20 +1821,27 @@ static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
 	struct completion frame_done_completion;
 	bool is_on;
 	int r;
+	int irq;
 
 	enable_clocks(1);
 
 	/* When we disable LCD output, we need to wait until frame is done.
 	 * Otherwise the DSS is still working, and turning off the clocks
 	 * prevents DSS from going to OFF mode */
-	is_on = REG_GET(DISPC_CONTROL, 0, 0);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		is_on = REG_GET(DISPC_CONTROL2, 0, 0);
+		irq = DISPC_IRQ_FRAMEDONE2;
+	} else {
+		is_on = REG_GET(DISPC_CONTROL, 0, 0);
+		irq = DISPC_IRQ_FRAMEDONE;
+	}
 
 	if (!enable && is_on) {
 		init_completion(&frame_done_completion);
 
 		r = omap_dispc_register_isr(dispc_disable_isr,
 				&frame_done_completion,
-				DISPC_IRQ_FRAMEDONE);
+				irq);
 
 		if (r)
 			DSSERR("failed to register FRAMEDONE isr\n");
@@ -1847,7 +1856,7 @@ static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
 
 		r = omap_dispc_unregister_isr(dispc_disable_isr,
 				&frame_done_completion,
-				DISPC_IRQ_FRAMEDONE);
+				irq);
 
 		if (r)
 			DSSERR("failed to unregister FRAMEDONE isr\n");
@@ -2482,6 +2491,12 @@ void dispc_dump_irqs(struct seq_file *s)
 	PIS(SYNC_LOST);
 	PIS(SYNC_LOST_DIGIT);
 	PIS(WAKEUP);
+	if (cpu_is_omap44xx()) {
+		PIS(FRAMEDONE2);
+		PIS(VSYNC2);
+		PIS(ACBIAS_COUNT_STAT2);
+		PIS(SYNC_LOST_2);
+	}
 #undef PIS
 }
 #endif
@@ -3089,6 +3104,45 @@ static void dispc_error_worker(struct work_struct *work)
 		}
 	}
 
+	if (errors & DISPC_IRQ_SYNC_LOST_2) {
+		struct omap_overlay_manager *manager = NULL;
+		bool enable = false;
+
+		DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
+
+		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
+			struct omap_overlay_manager *mgr;
+			mgr = omap_dss_get_overlay_manager(i);
+
+			if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
+				manager = mgr;
+				enable = mgr->device->state ==
+						OMAP_DSS_DISPLAY_ACTIVE;
+				mgr->device->driver->disable(mgr->device);
+				break;
+			}
+		}
+
+		if (manager) {
+			for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+				struct omap_overlay *ovl;
+				ovl = omap_dss_get_overlay(i);
+
+				if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+					continue;
+
+				if (ovl->id != 0 && ovl->manager == manager)
+					dispc_enable_plane(ovl->id, 0);
+			}
+
+			dispc_go(manager->id);
+			mdelay(50);
+			if (enable)
+				manager->device->driver->enable(
+							manager->device);
+		}
+	}
+
 	if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
 		struct omap_overlay_manager *manager = NULL;
 		bool enable = false;
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 2636b7f..0166b76
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -513,11 +513,14 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
 	unsigned long timeout = msecs_to_jiffies(500);
 	u32 irq;
 
-	if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC)
+	if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) {
 		irq = DISPC_IRQ_EVSYNC_ODD;
-	else
-		irq = DISPC_IRQ_VSYNC;
-
+	} else {
+		if (mgr->device->channel == OMAP_DSS_CHANNEL_LCD)
+			irq = DISPC_IRQ_VSYNC;
+		else
+			irq = DISPC_IRQ_VSYNC2;
+	}
 	return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
 }
 
@@ -543,9 +546,13 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
 			if (mode != OMAP_DSS_UPDATE_AUTO)
 				return 0;
 
-			irq = DISPC_IRQ_FRAMEDONE;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+				DISPC_IRQ_FRAMEDONE
+				: DISPC_IRQ_FRAMEDONE2;
 		} else {
-			irq = DISPC_IRQ_VSYNC;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+				DISPC_IRQ_VSYNC
+				: DISPC_IRQ_VSYNC2;
 		}
 	}
 
@@ -618,9 +625,13 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
 			if (mode != OMAP_DSS_UPDATE_AUTO)
 				return 0;
 
-			irq = DISPC_IRQ_FRAMEDONE;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+				DISPC_IRQ_FRAMEDONE
+				: DISPC_IRQ_FRAMEDONE2;
 		} else {
-			irq = DISPC_IRQ_VSYNC;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+				DISPC_IRQ_VSYNC
+				: DISPC_IRQ_VSYNC2;
 		}
 	}
 
@@ -1190,7 +1201,8 @@ static void dss_apply_irq_handler(void *data, u32 mask)
 
 	omap_dispc_unregister_isr(dss_apply_irq_handler, NULL,
 			DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
-			DISPC_IRQ_EVSYNC_EVEN);
+			DISPC_IRQ_EVSYNC_EVEN | (cpu_is_omap44xx()) ?
+			DISPC_IRQ_VSYNC2 : 0);
 	dss_cache.irq_enabled = false;
 
 end:
@@ -1384,7 +1396,8 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 	if (!dss_cache.irq_enabled) {
 		r = omap_dispc_register_isr(dss_apply_irq_handler, NULL,
 				DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
-				DISPC_IRQ_EVSYNC_EVEN);
+				DISPC_IRQ_EVSYNC_EVEN |
+				(cpu_is_omap44xx()) ? DISPC_IRQ_VSYNC2 : 0);
 		dss_cache.irq_enabled = true;
 	}
 	configure_dispc();
-- 
1.5.4.7

[RFC][PATCH 7/8] OMAP: DSS2: Context Save and Restore of DISPC registers for Secondary LCD

[Archit Taneja]

From: Mayuresh Janorkar <mayur@ti.com>

Context Save and Restore of DISPC registers for Secondary LCD

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 drivers/video/omap2/dss/dispc.c |   48 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 47 insertions(+), 1 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 3dcd3fe..ca90593
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -237,6 +237,17 @@ void dispc_save_context(void)
 	SR(SIZE_DIG);
 	SR(SIZE_LCD);
 
+	if (cpu_is_omap44xx()) {
+		SR(CONTROL2);
+		SR(DEFAULT_COLOR2);
+		SR(TRANS_COLOR2);
+		SR(SIZE_LCD2);
+		SR(TIMING_H2);
+		SR(TIMING_V2);
+		SR(POL_FREQ2);
+		SR(DIVISOR2);
+		SR(CONFIG2);
+	}
 	SR(GFX_BA0);
 	SR(GFX_BA1);
 	SR(GFX_POSITION);
@@ -256,6 +267,15 @@ void dispc_save_context(void)
 	SR(CPR_COEF_G);
 	SR(CPR_COEF_B);
 
+	if (cpu_is_omap44xx()) {
+		SR(CPR2_COEF_B);
+		SR(CPR2_COEF_G);
+		SR(CPR2_COEF_R);
+
+		SR(DATA2_CYCLE1);
+		SR(DATA2_CYCLE2);
+		SR(DATA2_CYCLE3);
+	}
 	SR(GFX_PRELOAD);
 
 	/* VID1 */
@@ -376,6 +396,22 @@ void dispc_restore_context(void)
 	RR(SIZE_DIG);
 	RR(SIZE_LCD);
 
+	if (cpu_is_omap44xx()) {
+		RR(DEFAULT_COLOR2);
+		RR(TRANS_COLOR2);
+		RR(CPR2_COEF_B);
+		RR(CPR2_COEF_G);
+		RR(CPR2_COEF_R);
+		RR(DATA2_CYCLE1);
+		RR(DATA2_CYCLE2);
+		RR(DATA2_CYCLE3);
+		RR(SIZE_LCD2);
+		RR(TIMING_H2);
+		RR(TIMING_V2);
+		RR(POL_FREQ2);
+		RR(DIVISOR2);
+		RR(CONFIG2);
+	}
 	RR(GFX_BA0);
 	RR(GFX_BA1);
 	RR(GFX_POSITION);
@@ -395,6 +431,15 @@ void dispc_restore_context(void)
 	RR(CPR_COEF_G);
 	RR(CPR_COEF_B);
 
+	if (cpu_is_omap44xx()) {
+		RR(CPR2_COEF_B);
+		RR(CPR2_COEF_G);
+		RR(CPR2_COEF_R);
+
+		RR(DATA2_CYCLE1);
+		RR(DATA2_CYCLE2);
+		RR(DATA2_CYCLE3);
+	}
 	RR(GFX_PRELOAD);
 
 	/* VID1 */
@@ -497,7 +542,8 @@ void dispc_restore_context(void)
 
 	/* enable last, because LCD & DIGIT enable are here */
 	RR(CONTROL);
-
+	if (cpu_is_omap44xx())
+		RR(CONTROL2);
 	/* clear spurious SYNC_LOST_DIGIT interrupts */
 	dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 
-- 
1.6.3.3

[PATCH] [PATCH] [RFC][PATCH 8/8] OMAP: DSS2: Interface driver changes for Secondary LCD Channel

[Archit Taneja]

From: Sumit Semwal <sumit.semwal@ti.com>

Make necessary changes in the interface drivers for the dispc
functions which have the new enum channel added to them

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
 drivers/video/omap2/dss/core.c |    2 +-
 drivers/video/omap2/dss/dpi.c  |   38 +++++++++++++++++++++-----------------
 drivers/video/omap2/dss/dsi.c  |   22 ++++++++++++----------
 drivers/video/omap2/dss/dss.h  |    8 +++++---
 drivers/video/omap2/dss/rfbi.c |   21 ++++++++++++---------
 drivers/video/omap2/dss/sdi.c  |   22 ++++++++++++----------
 6 files changed, 63 insertions(+), 50 deletions(-)

diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index b3a498f..e4909ad
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -411,7 +411,7 @@ static void dss_debug_dump_clocks(struct seq_file *s)
 	dss_dump_clocks(s);
 	dispc_dump_clocks(s);
 #ifdef CONFIG_OMAP2_DSS_DSI
-	dsi_dump_clocks(s);
+	dsi_dump_clocks(OMAP_DSS_CHANNEL_LCD, s);
 #endif
 }
 
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 960e977..592c0c0
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -40,8 +40,9 @@ static struct {
 } dpi;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
-		unsigned long *fck, int *lck_div, int *pck_div)
+static int dpi_set_dsi_clk(enum omap_channel channel, bool is_tft,
+		unsigned long pck_req, unsigned long *fck, int *lck_div,
+		int *pck_div)
 {
 	struct dsi_clock_info dsi_cinfo;
 	struct dispc_clock_info dispc_cinfo;
@@ -58,7 +59,7 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
 
 	dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(channel, &dispc_cinfo);
 	if (r)
 		return r;
 
@@ -69,8 +70,9 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
 	return 0;
 }
 #else
-static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
-		unsigned long *fck, int *lck_div, int *pck_div)
+static int dpi_set_dispc_clk(enum omap_channel channel, bool is_tft,
+		unsigned long pck_req, unsigned long *fck, int *lck_div,
+		int *pck_div)
 {
 	struct dss_clock_info dss_cinfo;
 	struct dispc_clock_info dispc_cinfo;
@@ -84,7 +86,7 @@ static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
 	if (r)
 		return r;
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(channel, &dispc_cinfo);
 	if (r)
 		return r;
 
@@ -107,17 +109,17 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
 
 	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 
-	dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
-			dssdev->panel.acb);
+	dispc_set_pol_freq(dssdev->channel, dssdev->panel.config,
+		dssdev->panel.acbi, dssdev->panel.acb);
 
 	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-	r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
-			&fck, &lck_div, &pck_div);
+	r = dpi_set_dsi_clk(dssdev->channel, is_tft,
+			t->pixel_clock * 1000, &fck, &lck_div, &pck_div);
 #else
-	r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
-			&fck, &lck_div, &pck_div);
+	r = dpi_set_dispc_clk(dssdev->channel, is_tft,
+			t->pixel_clock * 1000, &fck, &lck_div, &pck_div);
 #endif
 	if (r)
 		goto err0;
@@ -132,7 +134,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
 		t->pixel_clock = pck;
 	}
 
-	dispc_set_lcd_timings(t);
+	dispc_set_lcd_timings(dssdev->channel, t);
 
 err0:
 	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
@@ -145,10 +147,12 @@ static int dpi_basic_init(struct omap_dss_device *dssdev)
 
 	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
 
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
-	dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
-			OMAP_DSS_LCD_DISPLAY_STN);
-	dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines);
+	dispc_set_parallel_interface_mode(dssdev->channel,
+						OMAP_DSS_PARALLELMODE_BYPASS);
+	dispc_set_lcd_display_type(dssdev->channel,
+		is_tft ? OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
+	dispc_set_tft_data_lines(dssdev->channel,
+				dssdev->phy.dpi.data_lines);
 
 	return 0;
 }
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index a6e0f64..94069d7
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -812,7 +812,7 @@ static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
 		 * with DSS2_FCK source also */
 		cinfo->highfreq = 0;
 	} else {
-		cinfo->clkin = dispc_pclk_rate();
+		cinfo->clkin = dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD);
 
 		if (cinfo->clkin < 32000000)
 			cinfo->highfreq = 0;
@@ -1157,7 +1157,7 @@ void dsi_pll_uninit(void)
 	DSSDBG("PLL uninit done\n");
 }
 
-void dsi_dump_clocks(struct seq_file *s)
+void dsi_dump_clocks(enum omap_channel channel, struct seq_file *s)
 {
 	int clksel;
 	struct dsi_clock_info *cinfo = &dsi.current_cinfo;
@@ -1206,8 +1206,8 @@ void dsi_dump_clocks(struct seq_file *s)
 
 	seq_printf(s,	"VP_CLK\t\t%lu\n"
 			"VP_PCLK\t\t%lu\n",
-			dispc_lclk_rate(),
-			dispc_pclk_rate());
+			dispc_lclk_rate(channel),
+			dispc_pclk_rate(channel));
 
 	enable_clocks(0);
 }
@@ -2888,7 +2888,7 @@ int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
 	if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
 		dss_setup_partial_planes(dssdev, x, y, w, h,
 				enlarge_update_area);
-		dispc_set_lcd_size(*w, *h);
+		dispc_set_lcd_size(dssdev->channel, *w, *h);
 	}
 
 	return 0;
@@ -2942,12 +2942,14 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 		return r;
 	}
 
-	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
+	dispc_set_lcd_display_type(dssdev->channel,
+					OMAP_DSS_LCD_DISPLAY_TFT);
 
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
+	dispc_set_parallel_interface_mode(dssdev->channel,
+					OMAP_DSS_PARALLELMODE_DSI);
 	dispc_enable_fifohandcheck(1);
 
-	dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
+	dispc_set_tft_data_lines(dssdev->channel, dssdev->ctrl.pixel_size);
 
 	{
 		struct omap_video_timings timings = {
@@ -2959,7 +2961,7 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 			.vbp		= 0,
 		};
 
-		dispc_set_lcd_timings(&timings);
+		dispc_set_lcd_timings(dssdev->channel, &timings);
 	}
 
 	return 0;
@@ -3014,7 +3016,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
 		return r;
 	}
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(dssdev->channel, &dispc_cinfo);
 	if (r) {
 		DSSERR("Failed to set dispc clocks\n");
 		return r;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 456c702..c596249
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -262,7 +262,8 @@ static inline void sdi_exit(void)
 int dsi_init(struct platform_device *pdev);
 void dsi_exit(void);
 
-void dsi_dump_clocks(struct seq_file *s);
+void dsi_dump_clocks(enum omap_channel channel,
+		struct seq_file *s);
 void dsi_dump_irqs(struct seq_file *s);
 void dsi_dump_regs(struct seq_file *s);
 
@@ -431,8 +432,9 @@ void rfbi_dump_regs(struct seq_file *s);
 
 int rfbi_configure(int rfbi_module, int bpp, int lines);
 void rfbi_enable_rfbi(bool enable);
-void rfbi_transfer_area(u16 width, u16 height,
-			     void (callback)(void *data), void *data);
+void rfbi_transfer_area(struct omap_dss_device *dssdev,
+		u16 width, u16 height,
+		void (callback)(void *data), void *data);
 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
 unsigned long rfbi_get_max_tx_rate(void);
 int rfbi_init_display(struct omap_dss_device *display);
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index bbe6246..f7e9b95
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -301,8 +301,8 @@ void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 }
 EXPORT_SYMBOL(omap_rfbi_write_pixels);
 
-void rfbi_transfer_area(u16 width, u16 height,
-			     void (callback)(void *data), void *data)
+void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
+			u16 height, void (*callback)(void *data), void *data)
 {
 	u32 l;
 
@@ -311,9 +311,9 @@ void rfbi_transfer_area(u16 width, u16 height,
 
 	DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
 
-	dispc_set_lcd_size(width, height);
+	dispc_set_lcd_size(dssdev->channel, width, height);
 
-	dispc_enable_channel(OMAP_DSS_CHANNEL_LCD, true);
+	dispc_enable_channel(dssdev->channel, true);
 
 	rfbi.framedone_callback = callback;
 	rfbi.framedone_callback_data = data;
@@ -887,7 +887,7 @@ int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
 
 	if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
 		dss_setup_partial_planes(dssdev, x, y, w, h, true);
-		dispc_set_lcd_size(*w, *h);
+		dispc_set_lcd_size(dssdev->channel, *w, *h);
 	}
 
 	return 0;
@@ -899,7 +899,7 @@ int omap_rfbi_update(struct omap_dss_device *dssdev,
 		void (*callback)(void *), void *data)
 {
 	if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-		rfbi_transfer_area(w, h, callback, data);
+		rfbi_transfer_area(dssdev, w, h, callback, data);
 	} else {
 		struct omap_overlay *ovl;
 		void __iomem *addr;
@@ -1018,11 +1018,14 @@ int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
 		goto err1;
 	}
 
-	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
+	dispc_set_lcd_display_type(dssdev->channel,
+					OMAP_DSS_LCD_DISPLAY_TFT);
 
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
+	dispc_set_parallel_interface_mode(dssdev->channel,
+					OMAP_DSS_PARALLELMODE_RFBI);
 
-	dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
+	dispc_set_tft_data_lines(dssdev->channel,
+					dssdev->ctrl.pixel_size);
 
 	rfbi_configure(dssdev->phy.rfbi.channel,
 			       dssdev->ctrl.pixel_size,
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index ee07a3c..2f8924b
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -35,12 +35,14 @@ static struct {
 	struct regulator *vdds_sdi_reg;
 } sdi;
 
-static void sdi_basic_init(void)
+static void sdi_basic_init(struct omap_dss_device *dssdev)
 {
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
+	dispc_set_parallel_interface_mode(dssdev->channel,
+					OMAP_DSS_PARALLELMODE_BYPASS);
 
-	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-	dispc_set_tft_data_lines(24);
+	dispc_set_lcd_display_type(dssdev->channel,
+					OMAP_DSS_LCD_DISPLAY_TFT);
+	dispc_set_tft_data_lines(dssdev->channel, 24);
 	dispc_lcd_enable_signal_polarity(1);
 }
 
@@ -68,20 +70,20 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
 	if (!sdi.skip_init)
 		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 
-	sdi_basic_init();
+	sdi_basic_init(dssdev);
 
 	/* 15.5.9.1.2 */
 	dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
 
-	dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
-			dssdev->panel.acb);
+	dispc_set_pol_freq(dssdev->channel, dssdev->panel.config,
+				dssdev->panel.acbi, dssdev->panel.acb);
 
 	if (!sdi.skip_init) {
 		r = dss_calc_clock_div(1, t->pixel_clock * 1000,
 				&dss_cinfo, &dispc_cinfo);
 	} else {
 		r = dss_get_clock_div(&dss_cinfo);
-		r = dispc_get_clock_div(&dispc_cinfo);
+		r = dispc_get_clock_div(dssdev->channel, &dispc_cinfo);
 	}
 
 	if (r)
@@ -102,13 +104,13 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
 	}
 
 
-	dispc_set_lcd_timings(t);
+	dispc_set_lcd_timings(dssdev->channel, t);
 
 	r = dss_set_clock_div(&dss_cinfo);
 	if (r)
 		goto err2;
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(dssdev->channel, &dispc_cinfo);
 	if (r)
 		goto err2;
 
-- 
1.5.4.7

Re: [RFC][PATCH 4/8] OMAP: DSS2: OMAP4 Secondary LCD Channel DISPC Registers

[Tomi Valkeinen]

On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> From: Semwal, Sumit <sumit.semwal@ti.com>
> 
> Introduce OMAP4 DISPC base address and Secondary LCD Channel registers, use them
> in register dumps.
> 
> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
> Signed-off-by: Mukund Mittal <mmittal@ti.com>
> Signed-off-by: Archit Taneja <archit@ti.com>
> Signed-off-by: Samreen <samreen@ti.com>
> ---
>  drivers/video/omap2/dss/dispc.c |   42 ++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 41 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index 5ecdc00..08b36d6
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -41,9 +41,13 @@
>  #include "dss.h"
>  
>  /* DISPC */
> +#ifdef CONFIG_ARCH_OMAP4
> +#define DISPC_BASE			0x58001000
> +#define DISPC_SZ_REGS			SZ_16K
> +#else
>  #define DISPC_BASE			0x48050400
> -
>  #define DISPC_SZ_REGS			SZ_1K
> +#endif
>  
>  struct dispc_reg { u16 idx; };
>  
> @@ -68,6 +72,7 @@ struct dispc_reg { u16 idx; };
>  #define DISPC_TIMING_V			DISPC_REG(0x0068)
>  #define DISPC_POL_FREQ			DISPC_REG(0x006C)
>  #define DISPC_DIVISOR			DISPC_REG(0x0070)
> +#define DISPC_DIVISOR1			DISPC_REG(0x0804)

What is this?

>  #define DISPC_GLOBAL_ALPHA		DISPC_REG(0x0074)
>  #define DISPC_SIZE_DIG			DISPC_REG(0x0078)
>  #define DISPC_SIZE_LCD			DISPC_REG(0x007C)
> @@ -131,6 +136,23 @@ struct dispc_reg { u16 idx; };
>  					 DISPC_IRQ_SYNC_LOST | \
>  					 DISPC_IRQ_SYNC_LOST_DIGIT)
>  
> +/* OMAP4 new global registers */
> +#define DISPC_CONTROL2		DISPC_REG(0x0238)
> +#define DISPC_DEFAULT_COLOR2		DISPC_REG(0x03AC)
> +#define DISPC_TRANS_COLOR2		DISPC_REG(0x03B0)
> +#define DISPC_CPR2_COEF_B		DISPC_REG(0x03B4)
> +#define DISPC_CPR2_COEF_G		DISPC_REG(0x03B8)
> +#define DISPC_CPR2_COEF_R		DISPC_REG(0x03BC)
> +#define DISPC_DATA2_CYCLE1		DISPC_REG(0x03C0)
> +#define DISPC_DATA2_CYCLE2		DISPC_REG(0x03C4)
> +#define DISPC_DATA2_CYCLE3		DISPC_REG(0x03C8)
> +#define DISPC_SIZE_LCD2		DISPC_REG(0x03CC)
> +#define DISPC_TIMING_H2		DISPC_REG(0x0400)
> +#define DISPC_TIMING_V2		DISPC_REG(0x0404)
> +#define DISPC_POL_FREQ2		DISPC_REG(0x0408)
> +#define DISPC_DIVISOR2		DISPC_REG(0x040C)
> +#define DISPC_CONFIG2		DISPC_REG(0x0620)
> +
>  #define DISPC_MAX_NR_ISRS		8

Would it be possible to have similar system to these registers as with
for example the VID registers:

DISPC_SIZE_LCD(n) where n is 0 or 1, or possibly the channel.

This would reduce ifs quite a bit in the following patches.

 Tomi

Re: [RFC][PATCH 3/8] OMAP: DSS2: Modify dss_recheck_connections

[Tomi Valkeinen]

On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> From: Sumit Semwal <sumit.semwal@ti.com>
> 
> The addition of the new 2lcd manager requires modifications in the
> dss_recheck_connections patch, this function behaves the same if
> the 2lcd manager doesn't exist

Here (and also in the previous patch) you talk about 2lcd, but the code
uses lcd2.

 Tomi

Re: [PATCH] [RFC][PATCH 2/8] OMAP: DSS2: Add new Overlay Manager

[Tomi Valkeinen]

On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> From: Sumit Semwal <sumit.semwal@ti.com>
> 
> Add new Overlay Manager in manager.c, make secondary channel changes
> and update supported displays for the managers in OMAP4
> 
> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
> Signed-off-by: Mukund Mittal <mmittal@ti.com>
> Signed-off-by: Archit Taneja <archit@ti.com>
> Signed-off-by: Samreen <samreen@ti.com>
> ---

<snip>
 
> @@ -1471,15 +1471,25 @@ int dss_init_overlay_managers(struct platform_device *pdev)
>  		case 0:
>  			mgr->name = "lcd";
>  			mgr->id = OMAP_DSS_CHANNEL_LCD;
> -			mgr->supported_displays =
> -				OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
> -				OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
> +			mgr->supported_displays = OMAP_DISPLAY_TYPE_DBI |
> +				OMAP_DISPLAY_TYPE_DSI;
> +			if (cpu_is_omap34xx())
> +				mgr->supported_displays |=
> +					OMAP_DISPLAY_TYPE_DPI |
> +					OMAP_DISPLAY_TYPE_SDI;

How about OMAP2?

 Tomi

RE: [PATCH] [RFC][PATCH 2/8] OMAP: DSS2: Add new Overlay Manager

[Taneja, Archit]

 
> On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> > From: Sumit Semwal <sumit.semwal@ti.com>
> > 
> > Add new Overlay Manager in manager.c, make secondary 
> channel changes 
> > and update supported displays for the managers in OMAP4
> > 

<snip>

> > @@ -1471,15 +1471,25 @@ int 
> dss_init_overlay_managers(struct platform_device *pdev)
> >  		case 0:
> >  			mgr->name = "lcd";
> >  			mgr->id = OMAP_DSS_CHANNEL_LCD;
> > -			mgr->supported_displays =
> > -				OMAP_DISPLAY_TYPE_DPI | 
> OMAP_DISPLAY_TYPE_DBI |
> > -				OMAP_DISPLAY_TYPE_SDI | 
> OMAP_DISPLAY_TYPE_DSI;
> > +			mgr->supported_displays = 
> OMAP_DISPLAY_TYPE_DBI |
> > +				OMAP_DISPLAY_TYPE_DSI;
> > +			if (cpu_is_omap34xx())
> > +				mgr->supported_displays |=
> > +					OMAP_DISPLAY_TYPE_DPI |
> > +					OMAP_DISPLAY_TYPE_SDI;
> 
> How about OMAP2?

My bad, will fix this. Haven't tested it on omap2 yet.

> 
>  Tomi
> 
> 

RE: [RFC][PATCH 3/8] OMAP: DSS2: Modify dss_recheck_connections

[Taneja, Archit]

> On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> > From: Sumit Semwal <sumit.semwal@ti.com>
> > 
> > The addition of the new 2lcd manager requires modifications in the 
> > dss_recheck_connections patch, this function behaves the 
> same if the 
> > 2lcd manager doesn't exist
> 
> Here (and also in the previous patch) you talk about 2lcd, 
> but the code uses lcd2.

Archit:  The new manager's name defined in manager.c is 2lcd,
The channel's name in the enum is OMAP_DSS_CHANNEL_LCD2, and
the overlay manager enum is OMAP_DSS_OVL_MGR_LCD2.

2lcd as the manager name was taken so that no one makes mistakes
while reading/writing sysfs entries.

Also, in the dss2 code we use strncmp() to compare the manager
names in overlay_manager_store(). Now, if we name the new manager
as "lcd2", consider the following scenario:

Suppose an overlay has its manager presently set as "lcd2". Now
someone does a sysfs entry to make the manager as "lcd". So in this
case the variable buf is "lcd" and and mgr->name is "lcd2". The
variable len is calculated on the basis of buf ("lcd") as 3.

So strncmp just compares the first 3 chars, and in that case "lcd"
and "lcd2" are the same, luckily this doesn't cause an issue as the
first manager fetched by omap_dss_get_overlay_manager() is "lcd". If
the manager_list was filled in some other way then this would have
resulted an issue.

In my opinion, len should be calculated as:

len = max(len, strlen(mgr->name));

This way strncmp would work correctly in all the cases.

In order to take no risks, we named it as "2lcd".

Thanks,

Archit

RE: [RFC][PATCH 3/8] OMAP: DSS2: Modify dss_recheck_connections

[Tomi Valkeinen]

On Thu, 2010-07-01 at 14:28 +0200, ext Taneja, Archit wrote:
> > On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> > > From: Sumit Semwal <sumit.semwal@ti.com>
> > > 
> > > The addition of the new 2lcd manager requires modifications in the 
> > > dss_recheck_connections patch, this function behaves the 
> > same if the 
> > > 2lcd manager doesn't exist
> > 
> > Here (and also in the previous patch) you talk about 2lcd, 
> > but the code uses lcd2.
> 
> Archit:  The new manager's name defined in manager.c is 2lcd,
> The channel's name in the enum is OMAP_DSS_CHANNEL_LCD2, and
> the overlay manager enum is OMAP_DSS_OVL_MGR_LCD2.
> 
> 2lcd as the manager name was taken so that no one makes mistakes
> while reading/writing sysfs entries.
> 
> Also, in the dss2 code we use strncmp() to compare the manager
> names in overlay_manager_store(). Now, if we name the new manager
> as "lcd2", consider the following scenario:
> 
> Suppose an overlay has its manager presently set as "lcd2". Now
> someone does a sysfs entry to make the manager as "lcd". So in this
> case the variable buf is "lcd" and and mgr->name is "lcd2". The
> variable len is calculated on the basis of buf ("lcd") as 3.
> 
> So strncmp just compares the first 3 chars, and in that case "lcd"
> and "lcd2" are the same, luckily this doesn't cause an issue as the
> first manager fetched by omap_dss_get_overlay_manager() is "lcd". If
> the manager_list was filled in some other way then this would have
> resulted an issue.

If the DSS sysfs code if broken, let's rather fix it than name the
manager with a rather strange name, just to circumvent a bug.

> 
> In my opinion, len should be calculated as:
> 
> len = max(len, strlen(mgr->name));
> 
> This way strncmp would work correctly in all the cases.

sysfs_streq() could be used there.

 Tomi

Re: [RFC][PATCH 4/8] OMAP: DSS2: OMAP4 Secondary LCD Channel DISPC Registers

[Paul Walmsley]

On Thu, 1 Jul 2010, Archit Taneja wrote:

> From: Semwal, Sumit <sumit.semwal@ti.com>
> 
> Introduce OMAP4 DISPC base address and Secondary LCD Channel registers, use them
> in register dumps.
> 
> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
> Signed-off-by: Mukund Mittal <mmittal@ti.com>
> Signed-off-by: Archit Taneja <archit@ti.com>
> Signed-off-by: Samreen <samreen@ti.com>
> ---
>  drivers/video/omap2/dss/dispc.c |   42 ++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 41 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index 5ecdc00..08b36d6
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -41,9 +41,13 @@
>  #include "dss.h"
>  
>  /* DISPC */
> +#ifdef CONFIG_ARCH_OMAP4
> +#define DISPC_BASE			0x58001000
> +#define DISPC_SZ_REGS			SZ_16K
> +#else
>  #define DISPC_BASE			0x48050400
> -
>  #define DISPC_SZ_REGS			SZ_1K
> +#endif

This will break multi-OMAP builds.  Instead, get the DISPC_BASE at runtime 
through platform_get_resource*().


- Paul

RE: [RFC][PATCH 3/8] OMAP: DSS2: Modify dss_recheck_connections

[Taneja, Archit]

Hi,

> On Thu, 2010-07-01 at 14:28 +0200, ext Taneja, Archit wrote:
> > > On Thu, 2010-07-01 at 12:31 +0200, ext Archit Taneja wrote:
> > > > From: Sumit Semwal <sumit.semwal@ti.com>
> > > > 
> > > > The addition of the new 2lcd manager requires 
> modifications in the 
> > > > dss_recheck_connections patch, this function behaves the
> > > same if the
> > > > 2lcd manager doesn't exist
> > > 
> > > Here (and also in the previous patch) you talk about 
> 2lcd, but the 
> > > code uses lcd2.
> > 
> > Archit:  The new manager's name defined in manager.c is 2lcd, The 
> > channel's name in the enum is OMAP_DSS_CHANNEL_LCD2, and 
> the overlay 
> > manager enum is OMAP_DSS_OVL_MGR_LCD2.
> > 
> > 2lcd as the manager name was taken so that no one makes 
> mistakes while 
> > reading/writing sysfs entries.
> > 
> > Also, in the dss2 code we use strncmp() to compare the 
> manager names 
> > in overlay_manager_store(). Now, if we name the new manager 
> as "lcd2", 
> > consider the following scenario:
> > 
> > Suppose an overlay has its manager presently set as "lcd2". Now 
> > someone does a sysfs entry to make the manager as "lcd". So in this 
> > case the variable buf is "lcd" and and mgr->name is "lcd2". The 
> > variable len is calculated on the basis of buf ("lcd") as 3.
> > 
> > So strncmp just compares the first 3 chars, and in that case "lcd"
> > and "lcd2" are the same, luckily this doesn't cause an issue as the 
> > first manager fetched by omap_dss_get_overlay_manager() is 
> "lcd". If 
> > the manager_list was filled in some other way then this would have 
> > resulted an issue.
> 
> If the DSS sysfs code if broken, let's rather fix it than 
> name the manager with a rather strange name, just to circumvent a bug.
> 
> > 
> > In my opinion, len should be calculated as:
> > 
> > len = max(len, strlen(mgr->name));
> > 
> > This way strncmp would work correctly in all the cases.
> 
> sysfs_streq() could be used there.

I agree, I will make this change.

Archit