* [PATCH 0/5] OMAP: DSS2: Video3 pipeline support for OMAP4 @ 2010-07-19 11:55 Archit Taneja 2010-07-19 11:55 ` [PATCH 1/5] OMAP: DSS2: Add Video3 pipeline in display.h Archit Taneja 0 siblings, 1 reply; 14+ messages in thread From: Archit Taneja @ 2010-07-19 11:55 UTC (permalink / raw) To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal From: Sumit Semwal <sumit.semwal@ti.com> This patch incorporates the Video3 pipeline of OMAP4 in the exisiting DSS2 framework. It introduces the Video3 pipeline registers and adds a new overlay object to support this pipeline. Apart from this, bit field changes have been introduced for all video pipeline registers on OMAP4. In particular, changes for VID_ACCUi, VID_BUF_THRESHOLD and VID_BUF_SIZE_STATUS have been introduced. Sumit Semwal (4): OMAP: DSS2: Add Video3 pipeline in display.h OMAP: DSS2: Add Video3 pipeline functionality in DISPC OMAP: DSS2: Add new overlay object for Video3 pipeline OMAP: DSS2: Video3 pipeline IRQs Mayuresh Janorkar (1): OMAP: DSS2: Context Save and Restore of Video3 pipeline registers --- arch/arm/plat-omap/include/plat/display.h | 7 +- drivers/video/omap2/dss/dispc.c | 299 ++++++++++++++++++++++++++--- drivers/video/omap2/dss/manager.c | 13 +- drivers/video/omap2/dss/overlay.c | 18 ++- 4 files changed, 302 insertions(+), 35 deletions(-) ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/5] OMAP: DSS2: Add Video3 pipeline in display.h 2010-07-19 11:55 [PATCH 0/5] OMAP: DSS2: Video3 pipeline support for OMAP4 Archit Taneja @ 2010-07-19 11:55 ` Archit Taneja 2010-07-19 11:55 ` [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC Archit Taneja 0 siblings, 1 reply; 14+ messages in thread From: Archit Taneja @ 2010-07-19 11:55 UTC (permalink / raw) To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Archit Taneja From: Sumit Semwal <sumit.semwal@ti.com> Changes in display.h for enabling Video3 pipeline in DSS2 for OMAP4. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> --- arch/arm/plat-omap/include/plat/display.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 56e7045..d1da317 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -62,7 +62,8 @@ enum omap_display_type { enum omap_plane { OMAP_DSS_GFX = 0, OMAP_DSS_VIDEO1 = 1, - OMAP_DSS_VIDEO2 = 2 + OMAP_DSS_VIDEO2 = 2, + OMAP_DSS_VIDEO3 = 3, }; enum omap_channel { @@ -117,6 +118,8 @@ enum omap_color_mode { OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, + + OMAP_DSS_COLOR_VID3_OMAP3 = OMAP_DSS_COLOR_VID2_OMAP3, }; enum omap_lcd_display_type { -- 1.6.3.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC 2010-07-19 11:55 ` [PATCH 1/5] OMAP: DSS2: Add Video3 pipeline in display.h Archit Taneja @ 2010-07-19 11:55 ` Archit Taneja 2010-07-19 11:55 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Archit Taneja 0 siblings, 1 reply; 14+ messages in thread From: Archit Taneja @ 2010-07-19 11:55 UTC (permalink / raw) To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Archit Taneja From: Sumit Semwal <sumit.semwal@ti.com> VID3 and Writeback pipeline registers have a linear relation, this patch introduces these registers and adds Video3 pipeline support for the dispc functions. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> --- drivers/video/omap2/dss/dispc.c | 172 +++++++++++++++++++++++++++++++++----- 1 files changed, 149 insertions(+), 23 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 48167a2..00aad04 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -138,6 +138,33 @@ struct dispc_reg { u16 idx; }; #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) +/* DISPC Video plane, n = 0 for VID3, n = 1 for WB */ +#define DISPC_VID3_WB_REG(n, idx) DISPC_REG(0x0300 + (n)*0x200 + idx) + +#define DISPC_VID3_WB_ACCU0(n) DISPC_VID3_WB_REG(n, 0x0000) +#define DISPC_VID3_WB_ACCU1(n) DISPC_VID3_WB_REG(n, 0x0004) +#define DISPC_VID3_WB_BA0(n) DISPC_VID3_WB_REG(n, 0x0008) +#define DISPC_VID3_WB_BA1(n) DISPC_VID3_WB_REG(n, 0x000C) +#define DISPC_VID3_WB_ATTRIBUTES(n) DISPC_VID3_WB_REG(n, 0x0070) +#define DISPC_VID3_WB_BUF_SIZE_STATUS(n) DISPC_VID3_WB_REG(n, 0x0088) +#define DISPC_VID3_WB_BUF_THRESHOLD(n) DISPC_VID3_WB_REG(n, 0x008C) +#define DISPC_VID3_WB_FIR(n) DISPC_VID3_WB_REG(n, 0x0090) +#define DISPC_VID3_WB_PICTURE_SIZE(n) DISPC_VID3_WB_REG(n, 0x0094) +#define DISPC_VID3_WB_PIXEL_INC(n) DISPC_VID3_WB_REG(n, 0x0098) +#define DISPC_VID3_WB_ROW_INC(n) DISPC_VID3_WB_REG(n, 0x00A4) +#define DISPC_VID3_WB_SIZE(n) DISPC_VID3_WB_REG(n, 0x00A8) + +/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ +#define DISPC_VID3_WB_FIR_COEF_H(n, i) DISPC_REG(0x0310 + (n)*0x200 + (i)*0x8) +/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ +#define DISPC_VID3_WB_FIR_COEF_HV(n, i) DISPC_REG(0x0314 + (n)*0x200 + (i)*0x8) +/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ +#define DISPC_VID3_WB_FIR_COEF_V(n, i) DISPC_REG(0x0350 + (n)*0x200 + (i)*0x4) +/* coef index i = {0, 1, 2, 3, 4} */ +#define DISPC_VID3_WB_CONV_COEF(n, i) DISPC_REG(0x0374 + (n)*0x200 + (i)*0x4) + +#define DISPC_VID3_POSITION DISPC_REG(0x039C) +#define DISPC_VID3_PRELOAD DISPC_REG(0x03A0) #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ DISPC_IRQ_OCP_ERR | \ @@ -164,7 +191,8 @@ struct omap_dispc_isr_data { static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES, DISPC_VID_ATTRIBUTES(0), - DISPC_VID_ATTRIBUTES(1) }; + DISPC_VID_ATTRIBUTES(1), + DISPC_VID3_WB_ATTRIBUTES(0) }; /* VID 3 pipeline */ struct dispc_irq_stats { unsigned long last_reset; @@ -603,21 +631,30 @@ static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); - dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); + if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane)) + dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); + else if (OMAP_DSS_VIDEO3 == plane) + dispc_write_reg(DISPC_VID3_WB_FIR_COEF_H(0, reg), value); } static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); - dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); + if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane)) + dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); + else if (OMAP_DSS_VIDEO3 == plane) + dispc_write_reg(DISPC_VID3_WB_FIR_COEF_HV(0, reg), value); } static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value) { BUG_ON(plane == OMAP_DSS_GFX); - dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value); + if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane)) + dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value); + else if (OMAP_DSS_VIDEO3 == plane) + dispc_write_reg(DISPC_VID3_WB_FIR_COEF_V(0, reg), value); } static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, @@ -801,11 +838,25 @@ static void _dispc_setup_color_conv_coef(void) dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr)); dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by)); dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb)); - + if (cpu_is_omap44xx()) { + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 0), + CVAL(ct->rcr, ct->ry)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 1), + CVAL(ct->gy, ct->rcb)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 2), + CVAL(ct->gcb, ct->gcr)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 3), + CVAL(ct->bcr, ct->by)); + dispc_write_reg(DISPC_VID3_WB_CONV_COEF(0, 4), + CVAL(0, ct->bcb)); + } #undef CVAL REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); + if (cpu_is_omap44xx()) + REG_FLD_MOD(DISPC_VID3_WB_ATTRIBUTES(0), + ct->full_range, 11, 11); } @@ -813,7 +864,8 @@ static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) { const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0, DISPC_VID_BA0(0), - DISPC_VID_BA0(1) }; + DISPC_VID_BA0(1), + DISPC_VID3_WB_BA0(0) }; dispc_write_reg(ba0_reg[plane], paddr); } @@ -821,8 +873,9 @@ static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr) { const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1, - DISPC_VID_BA1(0), - DISPC_VID_BA1(1) }; + DISPC_VID_BA1(0), + DISPC_VID_BA1(1), + DISPC_VID3_WB_BA1(0) }; dispc_write_reg(ba1_reg[plane], paddr); } @@ -831,7 +884,8 @@ static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y) { const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION, DISPC_VID_POSITION(0), - DISPC_VID_POSITION(1) }; + DISPC_VID_POSITION(1), + DISPC_VID3_POSITION }; u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); dispc_write_reg(pos_reg[plane], val); @@ -841,7 +895,9 @@ static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) { const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE, DISPC_VID_PICTURE_SIZE(0), - DISPC_VID_PICTURE_SIZE(1) }; + DISPC_VID_PICTURE_SIZE(1), + DISPC_VID3_WB_PICTURE_SIZE(0) }; + u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); dispc_write_reg(siz_reg[plane], val); } @@ -849,9 +905,9 @@ static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) { u32 val; - const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), - DISPC_VID_SIZE(1) }; - + struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), + DISPC_VID_SIZE(1), + DISPC_VID3_WB_SIZE(0) }; BUG_ON(plane == OMAP_DSS_GFX); val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); @@ -870,13 +926,16 @@ static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); else if (plane == OMAP_DSS_VIDEO2) REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16); + else if (plane == OMAP_DSS_VIDEO3) + REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 31, 24); } static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc) { const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC, DISPC_VID_PIXEL_INC(0), - DISPC_VID_PIXEL_INC(1) }; + DISPC_VID_PIXEL_INC(1), + DISPC_VID3_WB_PIXEL_INC(0) }; dispc_write_reg(ri_reg[plane], inc); } @@ -885,7 +944,8 @@ static void _dispc_set_row_inc(enum omap_plane plane, s32 inc) { const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC, DISPC_VID_ROW_INC(0), - DISPC_VID_ROW_INC(1) }; + DISPC_VID_ROW_INC(1), + DISPC_VID3_WB_ROW_INC(0) }; dispc_write_reg(ri_reg[plane], inc); } @@ -944,6 +1004,7 @@ static void _dispc_set_channel_out(enum omap_plane plane, break; case OMAP_DSS_VIDEO1: case OMAP_DSS_VIDEO2: + case OMAP_DSS_VIDEO3: shift = 16; break; default: @@ -993,6 +1054,7 @@ void dispc_set_burst_size(enum omap_plane plane, break; case OMAP_DSS_VIDEO1: case OMAP_DSS_VIDEO2: + case OMAP_DSS_VIDEO3: shift = 14; break; default: @@ -1056,7 +1118,8 @@ static void dispc_read_plane_fifo_sizes(void) { const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, DISPC_VID_FIFO_SIZE_STATUS(0), - DISPC_VID_FIFO_SIZE_STATUS(1) }; + DISPC_VID_FIFO_SIZE_STATUS(1), + DISPC_VID3_WB_BUF_SIZE_STATUS(0) }; u32 size; int plane; @@ -1067,6 +1130,8 @@ static void dispc_read_plane_fifo_sizes(void) size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0); else if (cpu_is_omap34xx()) size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0); + else if (cpu_is_omap44xx()) + size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 15, 0); else BUG(); @@ -1085,7 +1150,8 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) { const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, DISPC_VID_FIFO_THRESHOLD(0), - DISPC_VID_FIFO_THRESHOLD(1) }; + DISPC_VID_FIFO_THRESHOLD(1), + DISPC_VID3_WB_BUF_THRESHOLD(0) }; enable_clocks(1); DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", @@ -1097,9 +1163,12 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) if (cpu_is_omap24xx()) dispc_write_reg(ftrs_reg[plane], FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0)); - else + else if (cpu_is_omap34xx()) dispc_write_reg(ftrs_reg[plane], FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0)); + else if (cpu_is_omap44xx()) + dispc_write_reg(ftrs_reg[plane], + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); enable_clocks(0); } @@ -1118,7 +1187,8 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) { u32 val; const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0), - DISPC_VID_FIR(1) }; + DISPC_VID_FIR(1), + DISPC_VID3_WB_FIR(0) }; BUG_ON(plane == OMAP_DSS_GFX); @@ -1133,11 +1203,15 @@ static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) { u32 val; const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), - DISPC_VID_ACCU0(1) }; + DISPC_VID_ACCU0(1), + DISPC_VID3_WB_ACCU0(0) }; BUG_ON(plane == OMAP_DSS_GFX); - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); + if (cpu_is_omap44xx()) + val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); + else + val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); dispc_write_reg(ac0_reg[plane-1], val); } @@ -1145,11 +1219,15 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) { u32 val; const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), - DISPC_VID_ACCU1(1) }; + DISPC_VID_ACCU1(1), + DISPC_VID3_WB_ACCU1(0) }; BUG_ON(plane == OMAP_DSS_GFX); - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); + if (cpu_is_omap44xx()) + val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); + else + val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); dispc_write_reg(ac1_reg[plane-1], val); } @@ -2563,6 +2641,21 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_VID_ACCU0(1)); DUMPREG(DISPC_VID_ACCU1(1)); + if (cpu_is_omap44xx()) { + DUMPREG(DISPC_VID3_WB_BA0(0)); + DUMPREG(DISPC_VID3_WB_BA1(0)); + DUMPREG(DISPC_VID3_POSITION); + DUMPREG(DISPC_VID3_WB_SIZE(0)); + DUMPREG(DISPC_VID3_WB_ATTRIBUTES(0)); + DUMPREG(DISPC_VID3_WB_BUF_THRESHOLD(0)); + DUMPREG(DISPC_VID3_WB_BUF_SIZE_STATUS(0)); + DUMPREG(DISPC_VID3_WB_ROW_INC(0)); + DUMPREG(DISPC_VID3_WB_PIXEL_INC(0)); + DUMPREG(DISPC_VID3_WB_FIR(0)); + DUMPREG(DISPC_VID3_WB_PICTURE_SIZE(0)); + DUMPREG(DISPC_VID3_WB_ACCU0(0)); + DUMPREG(DISPC_VID3_WB_ACCU1(0)); + } DUMPREG(DISPC_VID_FIR_COEF_H(0, 0)); DUMPREG(DISPC_VID_FIR_COEF_H(0, 1)); DUMPREG(DISPC_VID_FIR_COEF_H(0, 2)); @@ -2623,8 +2716,41 @@ void dispc_dump_regs(struct seq_file *s) DUMPREG(DISPC_VID_FIR_COEF_V(1, 6)); DUMPREG(DISPC_VID_FIR_COEF_V(1, 7)); + if (cpu_is_omap44xx()) { + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 0)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 1)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 2)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 3)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 5)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 6)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_H(0, 7)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 0)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 1)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 2)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 3)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 5)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 6)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_HV(0, 7)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 0)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 1)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 2)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 3)); + DUMPREG(DISPC_VID3_WB_CONV_COEF(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 0)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 1)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 2)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 3)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 4)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 5)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 6)); + DUMPREG(DISPC_VID3_WB_FIR_COEF_V(0, 7)); + } DUMPREG(DISPC_VID_PRELOAD(0)); DUMPREG(DISPC_VID_PRELOAD(1)); + if (cpu_is_omap44xx()) + DUMPREG(DISPC_VID3_PRELOAD); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); #undef DUMPREG -- 1.5.4.7 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline 2010-07-19 11:55 ` [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC Archit Taneja @ 2010-07-19 11:55 ` Archit Taneja 2010-07-19 11:55 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Archit Taneja 2010-07-23 5:24 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Hiremath, Vaibhav 0 siblings, 2 replies; 14+ messages in thread From: Archit Taneja @ 2010-07-19 11:55 UTC (permalink / raw) To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Archit Taneja From: Sumit Semwal <sumit.semwal@ti.com> Add new overlay object for the Video3 pipeline in overlay.c. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> --- drivers/video/omap2/dss/manager.c | 13 +++++++------ drivers/video/omap2/dss/overlay.c | 18 ++++++++++++++---- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index 96073f5..bccb7b6 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -35,6 +35,7 @@ #include "dss.h" #define MAX_DSS_MANAGERS (cpu_is_omap44xx() ? 3 : 2) +#define MAX_DSS_OVERLAYS (cpu_is_omap44xx() ? 4 : 3) static int num_managers; static struct list_head manager_list; @@ -450,7 +451,7 @@ struct manager_cache_data { static struct { spinlock_t lock; - struct overlay_cache_data overlay_cache[3]; + struct overlay_cache_data overlay_cache[4]; struct manager_cache_data manager_cache[3]; bool irq_enabled; @@ -893,7 +894,7 @@ static int configure_dispc(void) { struct overlay_cache_data *oc; struct manager_cache_data *mc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); + const int num_ovls = MAX_DSS_OVERLAYS; const int num_mgrs = MAX_DSS_MANAGERS; int i; int r; @@ -1000,7 +1001,7 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev, { struct overlay_cache_data *oc; struct manager_cache_data *mc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); + const int num_ovls = MAX_DSS_OVERLAYS; struct omap_overlay_manager *mgr; int i; u16 x, y, w, h; @@ -1132,7 +1133,7 @@ void dss_start_update(struct omap_dss_device *dssdev) { struct manager_cache_data *mc; struct overlay_cache_data *oc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); + const int num_ovls = MAX_DSS_OVERLAYS; const int num_mgrs = MAX_DSS_MANAGERS; struct omap_overlay_manager *mgr; int i; @@ -1162,8 +1163,8 @@ static void dss_apply_irq_handler(void *data, u32 mask) { struct manager_cache_data *mc; struct overlay_cache_data *oc; - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); - const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); + const int num_ovls = MAX_DSS_OVERLAYS; + const int num_mgrs = MAX_DSS_MANAGERS; int i, r; bool mgr_busy[MAX_DSS_MANAGERS]; diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 29aa157..2f8f89c --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -36,6 +36,8 @@ #include "dss.h" +#define MAX_DSS_OVERLAYS (cpu_is_omap44xx() ? 4 : 3) + static int num_overlays; static struct list_head overlay_list; @@ -510,11 +512,11 @@ static void omap_dss_add_overlay(struct omap_overlay *overlay) list_add_tail(&overlay->list, &overlay_list); } -static struct omap_overlay *dispc_overlays[3]; +static struct omap_overlay *dispc_overlays[4]; void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr) { - mgr->num_overlays = 3; + mgr->num_overlays = MAX_DSS_OVERLAYS; mgr->overlays = dispc_overlays; } @@ -535,7 +537,7 @@ void dss_init_overlays(struct platform_device *pdev) num_overlays = 0; - for (i = 0; i < 3; ++i) { + for (i = 0; i < MAX_DSS_OVERLAYS; ++i) { struct omap_overlay *ovl; ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); @@ -571,6 +573,14 @@ void dss_init_overlays(struct platform_device *pdev) OMAP_DSS_OVL_CAP_DISPC; ovl->info.global_alpha = 255; break; + case 3: + ovl->name = "vid3"; + ovl->id = OMAP_DSS_VIDEO3; + ovl->supported_modes = OMAP_DSS_COLOR_VID3_OMAP3; + ovl->caps = OMAP_DSS_OVL_CAP_SCALE | + OMAP_DSS_OVL_CAP_DISPC; + ovl->info.global_alpha = 255; + break; } ovl->set_manager = &omap_dss_set_manager; @@ -661,7 +671,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) } if (mgr) { - for (i = 0; i < 3; i++) { + for (i = 0; i < MAX_DSS_OVERLAYS; i++) { struct omap_overlay *ovl; ovl = omap_dss_get_overlay(i); if (!ovl->manager || force) { -- 1.5.4.7 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs 2010-07-19 11:55 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Archit Taneja @ 2010-07-19 11:55 ` Archit Taneja 2010-07-19 11:55 ` [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers Archit Taneja 2010-07-23 5:40 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Hiremath, Vaibhav 2010-07-23 5:24 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Hiremath, Vaibhav 1 sibling, 2 replies; 14+ messages in thread From: Archit Taneja @ 2010-07-19 11:55 UTC (permalink / raw) To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Archit Taneja From: Sumit Semwal <sumit.semwal@ti.com> Introduce Video3 pipeline IRQS for dumps and error handling Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> --- arch/arm/plat-omap/include/plat/display.h | 2 ++ drivers/video/omap2/dss/dispc.c | 23 ++++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index be83766..91796b6 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -44,6 +44,8 @@ #define DISPC_IRQ_WAKEUP (1 << 16) #define DISPC_IRQ_SYNC_LOST_2 (1 << 17) #define DISPC_IRQ_VSYNC2 (1 << 18) +#define DISPC_IRQ_VID3_END_WIN (1 << 19) +#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) #define DISPC_IRQ_FRAMEDONE2 (1 << 22) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 00aad04..8345ed7 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -173,7 +173,8 @@ struct dispc_reg { u16 idx; }; DISPC_IRQ_SYNC_LOST | \ DISPC_IRQ_SYNC_LOST_DIGIT | \ (cpu_is_omap44xx() ? \ - DISPC_IRQ_SYNC_LOST_2 : 0)) + (DISPC_IRQ_VID3_FIFO_UNDERFLOW | \ + DISPC_IRQ_SYNC_LOST_2) : 0)) #define DISPC_MAX_NR_ISRS 8 @@ -2540,6 +2541,8 @@ void dispc_dump_irqs(struct seq_file *s) PIS(VSYNC2); PIS(ACBIAS_COUNT_STAT2); PIS(SYNC_LOST_2); + PIS(VID3_FIFO_UNDERFLOW); + PIS(VID3_END_WIN); } #undef PIS } @@ -3151,6 +3154,24 @@ static void dispc_error_worker(struct work_struct *work) } } + if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) { + DSSERR("VID3_FIFO_UNDERFLOW, disabling VID2\n"); + for (i = 0; i < omap_dss_get_num_overlays(); ++i) { + struct omap_overlay *ovl; + ovl = omap_dss_get_overlay(i); + + if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) + continue; + + if (ovl->id == 3) { + dispc_enable_plane(ovl->id, 0); + dispc_go(ovl->manager->id); + mdelay(50); + break; + } + } + } + if (errors & DISPC_IRQ_SYNC_LOST) { struct omap_overlay_manager *manager = NULL; bool enable = false; -- 1.5.4.7 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers 2010-07-19 11:55 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Archit Taneja @ 2010-07-19 11:55 ` Archit Taneja 2010-07-23 5:45 ` Hiremath, Vaibhav 2010-07-23 5:40 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Hiremath, Vaibhav 1 sibling, 1 reply; 14+ messages in thread From: Archit Taneja @ 2010-07-19 11:55 UTC (permalink / raw) To: tomi.valkeinen Cc: linux-omap, Mayuresh Janorkar, Mukund Mittal, Archit Taneja From: Mayuresh Janorkar <mayur@ti.com> Context Save and Restore of Video3 pipeline registers. Signed-off-by: Mayuresh Janorkar <mayur@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> --- drivers/video/omap2/dss/dispc.c | 104 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 104 insertions(+), 0 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 8cda961..5a6c10e --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -397,6 +397,58 @@ void dispc_save_context(void) SR(VID_FIR_COEF_V(1, 7)); SR(VID_PRELOAD(1)); + + /* VID3 */ + if (cpu_is_omap44xx()) { + SR(VID3_WB_BA0(0)); + SR(VID3_WB_BA1(0)); + SR(VID3_POSITION); + SR(VID3_WB_SIZE(0)); + SR(VID3_WB_ATTRIBUTES(0)); + SR(VID3_WB_BUF_THRESHOLD(0)); + SR(VID3_WB_BUF_SIZE_STATUS(0)); + SR(VID3_WB_ROW_INC(0)); + SR(VID3_WB_PIXEL_INC(0)); + SR(VID3_WB_FIR(0)); + SR(VID3_WB_PICTURE_SIZE(0)); + SR(VID3_WB_ACCU0(0)); + SR(VID3_WB_ACCU1(0)); + + SR(VID3_WB_FIR_COEF_H(0, 0)); + SR(VID3_WB_FIR_COEF_H(0, 1)); + SR(VID3_WB_FIR_COEF_H(0, 2)); + SR(VID3_WB_FIR_COEF_H(0, 3)); + SR(VID3_WB_FIR_COEF_H(0, 4)); + SR(VID3_WB_FIR_COEF_H(0, 5)); + SR(VID3_WB_FIR_COEF_H(0, 6)); + SR(VID3_WB_FIR_COEF_H(0, 7)); + + SR(VID3_WB_FIR_COEF_HV(0, 0)); + SR(VID3_WB_FIR_COEF_HV(0, 1)); + SR(VID3_WB_FIR_COEF_HV(0, 2)); + SR(VID3_WB_FIR_COEF_HV(0, 3)); + SR(VID3_WB_FIR_COEF_HV(0, 4)); + SR(VID3_WB_FIR_COEF_HV(0, 5)); + SR(VID3_WB_FIR_COEF_HV(0, 6)); + SR(VID3_WB_FIR_COEF_HV(0, 7)); + + SR(VID3_WB_CONV_COEF(0, 0)); + SR(VID3_WB_CONV_COEF(0, 1)); + SR(VID3_WB_CONV_COEF(0, 2)); + SR(VID3_WB_CONV_COEF(0, 3)); + SR(VID3_WB_CONV_COEF(0, 4)); + + SR(VID3_WB_FIR_COEF_V(0, 0)); + SR(VID3_WB_FIR_COEF_V(0, 1)); + SR(VID3_WB_FIR_COEF_V(0, 2)); + SR(VID3_WB_FIR_COEF_V(0, 3)); + SR(VID3_WB_FIR_COEF_V(0, 4)); + SR(VID3_WB_FIR_COEF_V(0, 5)); + SR(VID3_WB_FIR_COEF_V(0, 6)); + SR(VID3_WB_FIR_COEF_V(0, 7)); + + SR(VID3_PRELOAD); + } } void dispc_restore_context(void) @@ -553,6 +605,58 @@ void dispc_restore_context(void) RR(VID_PRELOAD(1)); + /* VID3 */ + if (cpu_is_omap44xx()) { + SR(VID3_WB_BA0(0)); + SR(VID3_WB_BA1(0)); + SR(VID3_POSITION); + SR(VID3_WB_SIZE(0)); + SR(VID3_WB_ATTRIBUTES(0)); + SR(VID3_WB_BUF_THRESHOLD(0)); + SR(VID3_WB_BUF_SIZE_STATUS(0)); + SR(VID3_WB_ROW_INC(0)); + SR(VID3_WB_PIXEL_INC(0)); + SR(VID3_WB_FIR(0)); + SR(VID3_WB_PICTURE_SIZE(0)); + SR(VID3_WB_ACCU0(0)); + SR(VID3_WB_ACCU1(0)); + + SR(VID3_WB_FIR_COEF_H(0, 0)); + SR(VID3_WB_FIR_COEF_H(0, 1)); + SR(VID3_WB_FIR_COEF_H(0, 2)); + SR(VID3_WB_FIR_COEF_H(0, 3)); + SR(VID3_WB_FIR_COEF_H(0, 4)); + SR(VID3_WB_FIR_COEF_H(0, 5)); + SR(VID3_WB_FIR_COEF_H(0, 6)); + SR(VID3_WB_FIR_COEF_H(0, 7)); + + SR(VID3_WB_FIR_COEF_HV(0, 0)); + SR(VID3_WB_FIR_COEF_HV(0, 1)); + SR(VID3_WB_FIR_COEF_HV(0, 2)); + SR(VID3_WB_FIR_COEF_HV(0, 3)); + SR(VID3_WB_FIR_COEF_HV(0, 4)); + SR(VID3_WB_FIR_COEF_HV(0, 5)); + SR(VID3_WB_FIR_COEF_HV(0, 6)); + SR(VID3_WB_FIR_COEF_HV(0, 7)); + + SR(VID3_WB_CONV_COEF(0, 0)); + SR(VID3_WB_CONV_COEF(0, 1)); + SR(VID3_WB_CONV_COEF(0, 2)); + SR(VID3_WB_CONV_COEF(0, 3)); + SR(VID3_WB_CONV_COEF(0, 4)); + + SR(VID3_WB_FIR_COEF_V(0, 0)); + SR(VID3_WB_FIR_COEF_V(0, 1)); + SR(VID3_WB_FIR_COEF_V(0, 2)); + SR(VID3_WB_FIR_COEF_V(0, 3)); + SR(VID3_WB_FIR_COEF_V(0, 4)); + SR(VID3_WB_FIR_COEF_V(0, 5)); + SR(VID3_WB_FIR_COEF_V(0, 6)); + SR(VID3_WB_FIR_COEF_V(0, 7)); + + SR(VID3_PRELOAD); + } + /* enable last, because LCD & DIGIT enable are here */ RR(CONTROL(0)); if (cpu_is_omap44xx()) -- 1.5.4.7 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* RE: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers 2010-07-19 11:55 ` [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers Archit Taneja @ 2010-07-23 5:45 ` Hiremath, Vaibhav 2010-07-23 5:55 ` Taneja, Archit 0 siblings, 1 reply; 14+ messages in thread From: Hiremath, Vaibhav @ 2010-07-23 5:45 UTC (permalink / raw) To: Taneja, Archit, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Janorkar, Mayuresh, Mittal, Mukund > -----Original Message----- > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap- > owner@vger.kernel.org] On Behalf Of Taneja, Archit > Sent: Monday, July 19, 2010 5:26 PM > To: tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Janorkar, Mayuresh; Mittal, Mukund; Taneja, > Archit > Subject: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline > registers > > From: Mayuresh Janorkar <mayur@ti.com> > > Context Save and Restore of Video3 pipeline registers. [Hiremath, Vaibhav] I still fill, we are un-necessary dividing the patch here. This patch can very well be part of another patch, [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC In-fact, for me this should be consolidated single patch, something like, OMAP: DSS2: Add Video-3 pipeline functionality I don't see any reason why we are fragmenting this into multiple patches. Thanks, Vaibhav > > Signed-off-by: Mayuresh Janorkar <mayur@ti.com> > Signed-off-by: Mukund Mittal <mmittal@ti.com> > Signed-off-by: Archit Taneja <archit@ti.com> > --- > drivers/video/omap2/dss/dispc.c | 104 > +++++++++++++++++++++++++++++++++++++++ > 1 files changed, 104 insertions(+), 0 deletions(-) > > diff --git a/drivers/video/omap2/dss/dispc.c > b/drivers/video/omap2/dss/dispc.c > index 8cda961..5a6c10e > --- a/drivers/video/omap2/dss/dispc.c > +++ b/drivers/video/omap2/dss/dispc.c > @@ -397,6 +397,58 @@ void dispc_save_context(void) > SR(VID_FIR_COEF_V(1, 7)); > > SR(VID_PRELOAD(1)); > + > + /* VID3 */ > + if (cpu_is_omap44xx()) { > + SR(VID3_WB_BA0(0)); > + SR(VID3_WB_BA1(0)); > + SR(VID3_POSITION); > + SR(VID3_WB_SIZE(0)); > + SR(VID3_WB_ATTRIBUTES(0)); > + SR(VID3_WB_BUF_THRESHOLD(0)); > + SR(VID3_WB_BUF_SIZE_STATUS(0)); > + SR(VID3_WB_ROW_INC(0)); > + SR(VID3_WB_PIXEL_INC(0)); > + SR(VID3_WB_FIR(0)); > + SR(VID3_WB_PICTURE_SIZE(0)); > + SR(VID3_WB_ACCU0(0)); > + SR(VID3_WB_ACCU1(0)); > + > + SR(VID3_WB_FIR_COEF_H(0, 0)); > + SR(VID3_WB_FIR_COEF_H(0, 1)); > + SR(VID3_WB_FIR_COEF_H(0, 2)); > + SR(VID3_WB_FIR_COEF_H(0, 3)); > + SR(VID3_WB_FIR_COEF_H(0, 4)); > + SR(VID3_WB_FIR_COEF_H(0, 5)); > + SR(VID3_WB_FIR_COEF_H(0, 6)); > + SR(VID3_WB_FIR_COEF_H(0, 7)); > + > + SR(VID3_WB_FIR_COEF_HV(0, 0)); > + SR(VID3_WB_FIR_COEF_HV(0, 1)); > + SR(VID3_WB_FIR_COEF_HV(0, 2)); > + SR(VID3_WB_FIR_COEF_HV(0, 3)); > + SR(VID3_WB_FIR_COEF_HV(0, 4)); > + SR(VID3_WB_FIR_COEF_HV(0, 5)); > + SR(VID3_WB_FIR_COEF_HV(0, 6)); > + SR(VID3_WB_FIR_COEF_HV(0, 7)); > + > + SR(VID3_WB_CONV_COEF(0, 0)); > + SR(VID3_WB_CONV_COEF(0, 1)); > + SR(VID3_WB_CONV_COEF(0, 2)); > + SR(VID3_WB_CONV_COEF(0, 3)); > + SR(VID3_WB_CONV_COEF(0, 4)); > + > + SR(VID3_WB_FIR_COEF_V(0, 0)); > + SR(VID3_WB_FIR_COEF_V(0, 1)); > + SR(VID3_WB_FIR_COEF_V(0, 2)); > + SR(VID3_WB_FIR_COEF_V(0, 3)); > + SR(VID3_WB_FIR_COEF_V(0, 4)); > + SR(VID3_WB_FIR_COEF_V(0, 5)); > + SR(VID3_WB_FIR_COEF_V(0, 6)); > + SR(VID3_WB_FIR_COEF_V(0, 7)); > + > + SR(VID3_PRELOAD); > + } > } > > void dispc_restore_context(void) > @@ -553,6 +605,58 @@ void dispc_restore_context(void) > > RR(VID_PRELOAD(1)); > > + /* VID3 */ > + if (cpu_is_omap44xx()) { > + SR(VID3_WB_BA0(0)); > + SR(VID3_WB_BA1(0)); > + SR(VID3_POSITION); > + SR(VID3_WB_SIZE(0)); > + SR(VID3_WB_ATTRIBUTES(0)); > + SR(VID3_WB_BUF_THRESHOLD(0)); > + SR(VID3_WB_BUF_SIZE_STATUS(0)); > + SR(VID3_WB_ROW_INC(0)); > + SR(VID3_WB_PIXEL_INC(0)); > + SR(VID3_WB_FIR(0)); > + SR(VID3_WB_PICTURE_SIZE(0)); > + SR(VID3_WB_ACCU0(0)); > + SR(VID3_WB_ACCU1(0)); > + > + SR(VID3_WB_FIR_COEF_H(0, 0)); > + SR(VID3_WB_FIR_COEF_H(0, 1)); > + SR(VID3_WB_FIR_COEF_H(0, 2)); > + SR(VID3_WB_FIR_COEF_H(0, 3)); > + SR(VID3_WB_FIR_COEF_H(0, 4)); > + SR(VID3_WB_FIR_COEF_H(0, 5)); > + SR(VID3_WB_FIR_COEF_H(0, 6)); > + SR(VID3_WB_FIR_COEF_H(0, 7)); > + > + SR(VID3_WB_FIR_COEF_HV(0, 0)); > + SR(VID3_WB_FIR_COEF_HV(0, 1)); > + SR(VID3_WB_FIR_COEF_HV(0, 2)); > + SR(VID3_WB_FIR_COEF_HV(0, 3)); > + SR(VID3_WB_FIR_COEF_HV(0, 4)); > + SR(VID3_WB_FIR_COEF_HV(0, 5)); > + SR(VID3_WB_FIR_COEF_HV(0, 6)); > + SR(VID3_WB_FIR_COEF_HV(0, 7)); > + > + SR(VID3_WB_CONV_COEF(0, 0)); > + SR(VID3_WB_CONV_COEF(0, 1)); > + SR(VID3_WB_CONV_COEF(0, 2)); > + SR(VID3_WB_CONV_COEF(0, 3)); > + SR(VID3_WB_CONV_COEF(0, 4)); > + > + SR(VID3_WB_FIR_COEF_V(0, 0)); > + SR(VID3_WB_FIR_COEF_V(0, 1)); > + SR(VID3_WB_FIR_COEF_V(0, 2)); > + SR(VID3_WB_FIR_COEF_V(0, 3)); > + SR(VID3_WB_FIR_COEF_V(0, 4)); > + SR(VID3_WB_FIR_COEF_V(0, 5)); > + SR(VID3_WB_FIR_COEF_V(0, 6)); > + SR(VID3_WB_FIR_COEF_V(0, 7)); > + > + SR(VID3_PRELOAD); > + } > + > /* enable last, because LCD & DIGIT enable are here */ > RR(CONTROL(0)); > if (cpu_is_omap44xx()) > -- > 1.5.4.7 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers 2010-07-23 5:45 ` Hiremath, Vaibhav @ 2010-07-23 5:55 ` Taneja, Archit 2010-07-23 5:57 ` Hiremath, Vaibhav 0 siblings, 1 reply; 14+ messages in thread From: Taneja, Archit @ 2010-07-23 5:55 UTC (permalink / raw) To: Hiremath, Vaibhav, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Janorkar, Mayuresh, Mittal, Mukund > > -----Original Message----- > > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap- > > owner@vger.kernel.org] On Behalf Of Taneja, Archit > > Sent: Monday, July 19, 2010 5:26 PM > > To: tomi.valkeinen@nokia.com > > Cc: linux-omap@vger.kernel.org; Janorkar, Mayuresh; Mittal, Mukund; > > Taneja, Archit > > Subject: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 > > pipeline registers > > > > From: Mayuresh Janorkar <mayur@ti.com> > > > > Context Save and Restore of Video3 pipeline registers. > [Hiremath, Vaibhav] I still fill, we are un-necessary > dividing the patch here. This patch can very well be part of > another patch, > > [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC > > In-fact, for me this should be consolidated single patch, > something like, > > OMAP: DSS2: Add Video-3 pipeline functionality > > > I don't see any reason why we are fragmenting this into > multiple patches. > > Thanks, > Vaibhav > > > [Archit] Okay, Does the following split sound good?: -OMAP: DSS2: [1/2]Add Video-3 pipeline functionality in dispc - This patch will have all dispc related changes -OMAP: DSS2: [2/2]Add Video-3 pipeline overlay object - This patch will add the new overlay and changes required in manager, irqs etc Or does a single patch make more sense? Thanks, Archit ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers 2010-07-23 5:55 ` Taneja, Archit @ 2010-07-23 5:57 ` Hiremath, Vaibhav 0 siblings, 0 replies; 14+ messages in thread From: Hiremath, Vaibhav @ 2010-07-23 5:57 UTC (permalink / raw) To: Taneja, Archit, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Janorkar, Mayuresh, Mittal, Mukund > -----Original Message----- > From: Taneja, Archit > Sent: Friday, July 23, 2010 11:26 AM > To: Hiremath, Vaibhav; tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Janorkar, Mayuresh; Mittal, Mukund > Subject: RE: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 > pipeline registers > > > > > -----Original Message----- > > > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap- > > > owner@vger.kernel.org] On Behalf Of Taneja, Archit > > > Sent: Monday, July 19, 2010 5:26 PM > > > To: tomi.valkeinen@nokia.com > > > Cc: linux-omap@vger.kernel.org; Janorkar, Mayuresh; Mittal, Mukund; > > > Taneja, Archit > > > Subject: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 > > > pipeline registers > > > > > > From: Mayuresh Janorkar <mayur@ti.com> > > > > > > Context Save and Restore of Video3 pipeline registers. > > [Hiremath, Vaibhav] I still fill, we are un-necessary > > dividing the patch here. This patch can very well be part of > > another patch, > > > > [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC > > > > In-fact, for me this should be consolidated single patch, > > something like, > > > > OMAP: DSS2: Add Video-3 pipeline functionality > > > > > > I don't see any reason why we are fragmenting this into > > multiple patches. > > > > Thanks, > > Vaibhav > > > > > > [Archit] Okay, Does the following split sound good?: > -OMAP: DSS2: [1/2]Add Video-3 pipeline functionality in dispc > - This patch will have all dispc related changes > -OMAP: DSS2: [2/2]Add Video-3 pipeline overlay object > - This patch will add the new overlay and changes > required in manager, irqs etc > > Or does a single patch make more sense? > [Hiremath, Vaibhav] I still feel single patch makes more sense here. Thanks, Vaibhav > Thanks, > > Archit ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs 2010-07-19 11:55 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Archit Taneja 2010-07-19 11:55 ` [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers Archit Taneja @ 2010-07-23 5:40 ` Hiremath, Vaibhav 2010-07-23 5:46 ` Taneja, Archit 1 sibling, 1 reply; 14+ messages in thread From: Hiremath, Vaibhav @ 2010-07-23 5:40 UTC (permalink / raw) To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund, Taneja, Archit > -----Original Message----- > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap- > owner@vger.kernel.org] On Behalf Of Archit Taneja > Sent: Monday, July 19, 2010 5:26 PM > To: tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Semwal, Sumit; Mittal, Mukund; Taneja, > Archit > Subject: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs > > From: Sumit Semwal <sumit.semwal@ti.com> > > Introduce Video3 pipeline IRQS for dumps and error handling > > Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> > Signed-off-by: Mukund Mittal <mmittal@ti.com> > Signed-off-by: Archit Taneja <archit@ti.com> > --- > arch/arm/plat-omap/include/plat/display.h | 2 ++ > drivers/video/omap2/dss/dispc.c | 23 ++++++++++++++++++++++- > 2 files changed, 24 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat- > omap/include/plat/display.h > index be83766..91796b6 > --- a/arch/arm/plat-omap/include/plat/display.h > +++ b/arch/arm/plat-omap/include/plat/display.h > @@ -44,6 +44,8 @@ > #define DISPC_IRQ_WAKEUP (1 << 16) > #define DISPC_IRQ_SYNC_LOST_2 (1 << 17) > #define DISPC_IRQ_VSYNC2 (1 << 18) > +#define DISPC_IRQ_VID3_END_WIN (1 << 19) > +#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) > #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) > #define DISPC_IRQ_FRAMEDONE2 (1 << 22) > > diff --git a/drivers/video/omap2/dss/dispc.c > b/drivers/video/omap2/dss/dispc.c > index 00aad04..8345ed7 > --- a/drivers/video/omap2/dss/dispc.c > +++ b/drivers/video/omap2/dss/dispc.c > @@ -173,7 +173,8 @@ struct dispc_reg { u16 idx; }; > DISPC_IRQ_SYNC_LOST | \ > DISPC_IRQ_SYNC_LOST_DIGIT | \ > (cpu_is_omap44xx() ? \ > - DISPC_IRQ_SYNC_LOST_2 : 0)) > + (DISPC_IRQ_VID3_FIFO_UNDERFLOW | \ > + DISPC_IRQ_SYNC_LOST_2) : 0)) [Hiremath, Vaibhav] This looks bit suspicious to me, against which tree this patch has been generated? I think you have missed some of the patches in between. > > #define DISPC_MAX_NR_ISRS 8 > > @@ -2540,6 +2541,8 @@ void dispc_dump_irqs(struct seq_file *s) > PIS(VSYNC2); > PIS(ACBIAS_COUNT_STAT2); > PIS(SYNC_LOST_2); > + PIS(VID3_FIFO_UNDERFLOW); > + PIS(VID3_END_WIN); > } > #undef PIS > } > @@ -3151,6 +3154,24 @@ static void dispc_error_worker(struct work_struct > *work) > } > } > > + if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) { > + DSSERR("VID3_FIFO_UNDERFLOW, disabling VID2\n"); [Hiremath, Vaibhav] typo mistake VID2 => VID3 Thanks, Vaibhav > + for (i = 0; i < omap_dss_get_num_overlays(); ++i) { > + struct omap_overlay *ovl; > + ovl = omap_dss_get_overlay(i); > + > + if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) > + continue; > + > + if (ovl->id == 3) { > + dispc_enable_plane(ovl->id, 0); > + dispc_go(ovl->manager->id); > + mdelay(50); > + break; > + } > + } > + } > + > if (errors & DISPC_IRQ_SYNC_LOST) { > struct omap_overlay_manager *manager = NULL; > bool enable = false; > -- > 1.5.4.7 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs 2010-07-23 5:40 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Hiremath, Vaibhav @ 2010-07-23 5:46 ` Taneja, Archit 2010-07-23 5:52 ` Hiremath, Vaibhav 0 siblings, 1 reply; 14+ messages in thread From: Taneja, Archit @ 2010-07-23 5:46 UTC (permalink / raw) To: Hiremath, Vaibhav, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund > -----Original Message----- > From: Hiremath, Vaibhav > Sent: Friday, July 23, 2010 11:10 AM > To: Taneja, Archit; tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Semwal, Sumit; Mittal, > Mukund; Taneja, Archit > Subject: RE: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs > <snap> > > @@ -173,7 +173,8 @@ struct dispc_reg { u16 idx; }; > > DISPC_IRQ_SYNC_LOST | \ > > DISPC_IRQ_SYNC_LOST_DIGIT | \ > > (cpu_is_omap44xx() ? \ > > - DISPC_IRQ_SYNC_LOST_2 : 0)) > > + > (DISPC_IRQ_VID3_FIFO_UNDERFLOW | \ > > + DISPC_IRQ_SYNC_LOST_2) : 0)) > [Hiremath, Vaibhav] This looks bit suspicious to me, against > which tree this patch has been generated? I think you have > missed some of the patches in between. [Archit] This patch series sits over a previously sent RFC: https://patchwork.kernel.org/patch/111901/ > > > > > #define DISPC_MAX_NR_ISRS 8 > > > > @@ -2540,6 +2541,8 @@ void dispc_dump_irqs(struct seq_file *s) > > PIS(VSYNC2); > > PIS(ACBIAS_COUNT_STAT2); > > PIS(SYNC_LOST_2); > > + PIS(VID3_FIFO_UNDERFLOW); > > + PIS(VID3_END_WIN); > > } > > #undef PIS > > } > > @@ -3151,6 +3154,24 @@ static void dispc_error_worker(struct > > work_struct > > *work) > > } > > } > > > > + if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) { > > + DSSERR("VID3_FIFO_UNDERFLOW, disabling VID2\n"); > [Hiremath, Vaibhav] typo mistake VID2 => VID3 > > Thanks, > Vaibhav Will fix this. Thanks, Archit ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs 2010-07-23 5:46 ` Taneja, Archit @ 2010-07-23 5:52 ` Hiremath, Vaibhav 0 siblings, 0 replies; 14+ messages in thread From: Hiremath, Vaibhav @ 2010-07-23 5:52 UTC (permalink / raw) To: Taneja, Archit, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund > -----Original Message----- > From: Taneja, Archit > Sent: Friday, July 23, 2010 11:17 AM > To: Hiremath, Vaibhav; tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Semwal, Sumit; Mittal, Mukund > Subject: RE: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs > > > > > -----Original Message----- > > From: Hiremath, Vaibhav > > Sent: Friday, July 23, 2010 11:10 AM > > To: Taneja, Archit; tomi.valkeinen@nokia.com > > Cc: linux-omap@vger.kernel.org; Semwal, Sumit; Mittal, > > Mukund; Taneja, Archit > > Subject: RE: [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs > > > > <snap> > > > > @@ -173,7 +173,8 @@ struct dispc_reg { u16 idx; }; > > > DISPC_IRQ_SYNC_LOST | \ > > > DISPC_IRQ_SYNC_LOST_DIGIT | \ > > > (cpu_is_omap44xx() ? \ > > > - DISPC_IRQ_SYNC_LOST_2 : 0)) > > > + > > (DISPC_IRQ_VID3_FIFO_UNDERFLOW | \ > > > + DISPC_IRQ_SYNC_LOST_2) : 0)) > > [Hiremath, Vaibhav] This looks bit suspicious to me, against > > which tree this patch has been generated? I think you have > > missed some of the patches in between. > > [Archit] This patch series sits over a previously sent RFC: > > https://patchwork.kernel.org/patch/111901/ > [Hiremath, Vaibhav] Ohhh, I missed it completely. Perhaps it would be good if you could mention this dependency in you PATCH [0/x]. I think Sanjeev has already provided some comments, so I would rather prefer to review latest version (when you post it again). Thanks, Vaibhav > > > > > > > > #define DISPC_MAX_NR_ISRS 8 > > > > > > @@ -2540,6 +2541,8 @@ void dispc_dump_irqs(struct seq_file *s) > > > PIS(VSYNC2); > > > PIS(ACBIAS_COUNT_STAT2); > > > PIS(SYNC_LOST_2); > > > + PIS(VID3_FIFO_UNDERFLOW); > > > + PIS(VID3_END_WIN); > > > } > > > #undef PIS > > > } > > > @@ -3151,6 +3154,24 @@ static void dispc_error_worker(struct > > > work_struct > > > *work) > > > } > > > } > > > > > > + if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) { > > > + DSSERR("VID3_FIFO_UNDERFLOW, disabling VID2\n"); > > [Hiremath, Vaibhav] typo mistake VID2 => VID3 > > > > Thanks, > > Vaibhav > > Will fix this. > > Thanks, > > Archit ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline 2010-07-19 11:55 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Archit Taneja 2010-07-19 11:55 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Archit Taneja @ 2010-07-23 5:24 ` Hiremath, Vaibhav 2010-07-23 5:38 ` Taneja, Archit 1 sibling, 1 reply; 14+ messages in thread From: Hiremath, Vaibhav @ 2010-07-23 5:24 UTC (permalink / raw) To: Taneja, Archit, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund > -----Original Message----- > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap- > owner@vger.kernel.org] On Behalf Of Taneja, Archit > Sent: Monday, July 19, 2010 5:26 PM > To: tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Semwal, Sumit; Mittal, Mukund; Taneja, > Archit > Subject: [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline > > From: Sumit Semwal <sumit.semwal@ti.com> > > Add new overlay object for the Video3 pipeline in overlay.c. > > Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> > Signed-off-by: Mukund Mittal <mmittal@ti.com> > Signed-off-by: Archit Taneja <archit@ti.com> > --- > drivers/video/omap2/dss/manager.c | 13 +++++++------ > drivers/video/omap2/dss/overlay.c | 18 ++++++++++++++---- > 2 files changed, 21 insertions(+), 10 deletions(-) > > diff --git a/drivers/video/omap2/dss/manager.c > b/drivers/video/omap2/dss/manager.c > index 96073f5..bccb7b6 > --- a/drivers/video/omap2/dss/manager.c > +++ b/drivers/video/omap2/dss/manager.c > @@ -35,6 +35,7 @@ > #include "dss.h" > > #define MAX_DSS_MANAGERS (cpu_is_omap44xx() ? 3 : 2) > +#define MAX_DSS_OVERLAYS (cpu_is_omap44xx() ? 4 : 3) > > static int num_managers; > static struct list_head manager_list; > @@ -450,7 +451,7 @@ struct manager_cache_data { > > static struct { > spinlock_t lock; > - struct overlay_cache_data overlay_cache[3]; > + struct overlay_cache_data overlay_cache[4]; > struct manager_cache_data manager_cache[3]; > > bool irq_enabled; > @@ -893,7 +894,7 @@ static int configure_dispc(void) > { > struct overlay_cache_data *oc; > struct manager_cache_data *mc; > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > + const int num_ovls = MAX_DSS_OVERLAYS; [Hiremath, Vaibhav] You may want to clean this up, since now you have global definition MAX_DSS_OVERLAYS. Applies to everywhere its being used. > const int num_mgrs = MAX_DSS_MANAGERS; > int i; > int r; > @@ -1000,7 +1001,7 @@ void dss_setup_partial_planes(struct omap_dss_device > *dssdev, > { > struct overlay_cache_data *oc; > struct manager_cache_data *mc; > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > + const int num_ovls = MAX_DSS_OVERLAYS; [Hiremath, Vaibhav] Ditto. > struct omap_overlay_manager *mgr; > int i; > u16 x, y, w, h; > @@ -1132,7 +1133,7 @@ void dss_start_update(struct omap_dss_device *dssdev) > { > struct manager_cache_data *mc; > struct overlay_cache_data *oc; > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > + const int num_ovls = MAX_DSS_OVERLAYS; [Hiremath, Vaibhav] Ditto. > const int num_mgrs = MAX_DSS_MANAGERS; > struct omap_overlay_manager *mgr; > int i; > @@ -1162,8 +1163,8 @@ static void dss_apply_irq_handler(void *data, u32 > mask) > { > struct manager_cache_data *mc; > struct overlay_cache_data *oc; > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > - const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); > + const int num_ovls = MAX_DSS_OVERLAYS; > + const int num_mgrs = MAX_DSS_MANAGERS; > int i, r; > bool mgr_busy[MAX_DSS_MANAGERS]; > > diff --git a/drivers/video/omap2/dss/overlay.c > b/drivers/video/omap2/dss/overlay.c > index 29aa157..2f8f89c > --- a/drivers/video/omap2/dss/overlay.c > +++ b/drivers/video/omap2/dss/overlay.c > @@ -36,6 +36,8 @@ > > #include "dss.h" > > +#define MAX_DSS_OVERLAYS (cpu_is_omap44xx() ? 4 : 3) > + [Hiremath, Vaibhav] Since this definition is being used in multiple file, consider moving this to dss.h file so that we have one place to see/modify in the future. Thanks, Vaibhav > static int num_overlays; > static struct list_head overlay_list; > > @@ -510,11 +512,11 @@ static void omap_dss_add_overlay(struct omap_overlay > *overlay) > list_add_tail(&overlay->list, &overlay_list); > } > > -static struct omap_overlay *dispc_overlays[3]; > +static struct omap_overlay *dispc_overlays[4]; > > void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr) > { > - mgr->num_overlays = 3; > + mgr->num_overlays = MAX_DSS_OVERLAYS; > mgr->overlays = dispc_overlays; > } > > @@ -535,7 +537,7 @@ void dss_init_overlays(struct platform_device *pdev) > > num_overlays = 0; > > - for (i = 0; i < 3; ++i) { > + for (i = 0; i < MAX_DSS_OVERLAYS; ++i) { > struct omap_overlay *ovl; > ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); > > @@ -571,6 +573,14 @@ void dss_init_overlays(struct platform_device *pdev) > OMAP_DSS_OVL_CAP_DISPC; > ovl->info.global_alpha = 255; > break; > + case 3: > + ovl->name = "vid3"; > + ovl->id = OMAP_DSS_VIDEO3; > + ovl->supported_modes = OMAP_DSS_COLOR_VID3_OMAP3; > + ovl->caps = OMAP_DSS_OVL_CAP_SCALE | > + OMAP_DSS_OVL_CAP_DISPC; > + ovl->info.global_alpha = 255; > + break; > } > > ovl->set_manager = &omap_dss_set_manager; > @@ -661,7 +671,7 @@ void dss_recheck_connections(struct omap_dss_device > *dssdev, bool force) > } > > if (mgr) { > - for (i = 0; i < 3; i++) { > + for (i = 0; i < MAX_DSS_OVERLAYS; i++) { > struct omap_overlay *ovl; > ovl = omap_dss_get_overlay(i); > if (!ovl->manager || force) { > -- > 1.5.4.7 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline 2010-07-23 5:24 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Hiremath, Vaibhav @ 2010-07-23 5:38 ` Taneja, Archit 0 siblings, 0 replies; 14+ messages in thread From: Taneja, Archit @ 2010-07-23 5:38 UTC (permalink / raw) To: Hiremath, Vaibhav, tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund Hi, > -----Original Message----- > From: Hiremath, Vaibhav > Sent: Friday, July 23, 2010 10:54 AM > To: Taneja, Archit; tomi.valkeinen@nokia.com > Cc: linux-omap@vger.kernel.org; Semwal, Sumit; Mittal, Mukund > Subject: RE: [PATCH 3/5] OMAP: DSS2: Add new overlay object > for Video3 pipeline > > <snap> > > struct overlay_cache_data *oc; > > struct manager_cache_data *mc; > > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > > + const int num_ovls = MAX_DSS_OVERLAYS; > [Hiremath, Vaibhav] You may want to clean this up, since now > you have global definition MAX_DSS_OVERLAYS. > Applies to everywhere its being used. > > > const int num_mgrs = MAX_DSS_MANAGERS; > > int i; > > int r; > > @@ -1000,7 +1001,7 @@ void dss_setup_partial_planes(struct > > omap_dss_device *dssdev, { > > struct overlay_cache_data *oc; > > struct manager_cache_data *mc; > > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > > + const int num_ovls = MAX_DSS_OVERLAYS; > [Hiremath, Vaibhav] Ditto. > > > struct omap_overlay_manager *mgr; > > int i; > > u16 x, y, w, h; > > @@ -1132,7 +1133,7 @@ void dss_start_update(struct omap_dss_device > > *dssdev) { > > struct manager_cache_data *mc; > > struct overlay_cache_data *oc; > > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > > + const int num_ovls = MAX_DSS_OVERLAYS; > [Hiremath, Vaibhav] Ditto. > > > const int num_mgrs = MAX_DSS_MANAGERS; > > struct omap_overlay_manager *mgr; > > int i; > > @@ -1162,8 +1163,8 @@ static void dss_apply_irq_handler(void *data, > > u32 > > mask) > > { > > struct manager_cache_data *mc; > > struct overlay_cache_data *oc; > > - const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); > > - const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); > > + const int num_ovls = MAX_DSS_OVERLAYS; > > + const int num_mgrs = MAX_DSS_MANAGERS; > > int i, r; > > bool mgr_busy[MAX_DSS_MANAGERS]; > > > > diff --git a/drivers/video/omap2/dss/overlay.c > > b/drivers/video/omap2/dss/overlay.c > > index 29aa157..2f8f89c > > --- a/drivers/video/omap2/dss/overlay.c > > +++ b/drivers/video/omap2/dss/overlay.c > > @@ -36,6 +36,8 @@ > > > > #include "dss.h" > > > > +#define MAX_DSS_OVERLAYS (cpu_is_omap44xx() ? 4 : 3) > > + > > [Hiremath, Vaibhav] Since this definition is being used in > multiple file, consider moving this to dss.h file so that we > have one place to see/modify in the future. > > Thanks, > Vaibhav > Thanks for the comments, I will incorporate the following changes: -remove const int num_mgrs and num_ovls variables as they are replaced by the new globals everywhere. -shift the MAX_DSS_OVERLAYS and MAX_DSS_MANAGERS to dss.h Archit ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2010-07-23 5:57 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-07-19 11:55 [PATCH 0/5] OMAP: DSS2: Video3 pipeline support for OMAP4 Archit Taneja 2010-07-19 11:55 ` [PATCH 1/5] OMAP: DSS2: Add Video3 pipeline in display.h Archit Taneja 2010-07-19 11:55 ` [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC Archit Taneja 2010-07-19 11:55 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Archit Taneja 2010-07-19 11:55 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Archit Taneja 2010-07-19 11:55 ` [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers Archit Taneja 2010-07-23 5:45 ` Hiremath, Vaibhav 2010-07-23 5:55 ` Taneja, Archit 2010-07-23 5:57 ` Hiremath, Vaibhav 2010-07-23 5:40 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Hiremath, Vaibhav 2010-07-23 5:46 ` Taneja, Archit 2010-07-23 5:52 ` Hiremath, Vaibhav 2010-07-23 5:24 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Hiremath, Vaibhav 2010-07-23 5:38 ` Taneja, Archit
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