From: Archit Taneja <archit@ti.com>
To: tomi.valkeinen@nokia.com
Cc: linux-omap@vger.kernel.org, Mayuresh Janorkar <mayur@ti.com>,
Mukund Mittal <mmittal@ti.com>, Archit Taneja <archit@ti.com>
Subject: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers
Date: Mon, 19 Jul 2010 17:25:44 +0530 [thread overview]
Message-ID: <1279540544-12682-6-git-send-email-archit@ti.com> (raw)
In-Reply-To: <1279540544-12682-5-git-send-email-archit@ti.com>
From: Mayuresh Janorkar <mayur@ti.com>
Context Save and Restore of Video3 pipeline registers.
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 104 +++++++++++++++++++++++++++++++++++++++
1 files changed, 104 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 8cda961..5a6c10e
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -397,6 +397,58 @@ void dispc_save_context(void)
SR(VID_FIR_COEF_V(1, 7));
SR(VID_PRELOAD(1));
+
+ /* VID3 */
+ if (cpu_is_omap44xx()) {
+ SR(VID3_WB_BA0(0));
+ SR(VID3_WB_BA1(0));
+ SR(VID3_POSITION);
+ SR(VID3_WB_SIZE(0));
+ SR(VID3_WB_ATTRIBUTES(0));
+ SR(VID3_WB_BUF_THRESHOLD(0));
+ SR(VID3_WB_BUF_SIZE_STATUS(0));
+ SR(VID3_WB_ROW_INC(0));
+ SR(VID3_WB_PIXEL_INC(0));
+ SR(VID3_WB_FIR(0));
+ SR(VID3_WB_PICTURE_SIZE(0));
+ SR(VID3_WB_ACCU0(0));
+ SR(VID3_WB_ACCU1(0));
+
+ SR(VID3_WB_FIR_COEF_H(0, 0));
+ SR(VID3_WB_FIR_COEF_H(0, 1));
+ SR(VID3_WB_FIR_COEF_H(0, 2));
+ SR(VID3_WB_FIR_COEF_H(0, 3));
+ SR(VID3_WB_FIR_COEF_H(0, 4));
+ SR(VID3_WB_FIR_COEF_H(0, 5));
+ SR(VID3_WB_FIR_COEF_H(0, 6));
+ SR(VID3_WB_FIR_COEF_H(0, 7));
+
+ SR(VID3_WB_FIR_COEF_HV(0, 0));
+ SR(VID3_WB_FIR_COEF_HV(0, 1));
+ SR(VID3_WB_FIR_COEF_HV(0, 2));
+ SR(VID3_WB_FIR_COEF_HV(0, 3));
+ SR(VID3_WB_FIR_COEF_HV(0, 4));
+ SR(VID3_WB_FIR_COEF_HV(0, 5));
+ SR(VID3_WB_FIR_COEF_HV(0, 6));
+ SR(VID3_WB_FIR_COEF_HV(0, 7));
+
+ SR(VID3_WB_CONV_COEF(0, 0));
+ SR(VID3_WB_CONV_COEF(0, 1));
+ SR(VID3_WB_CONV_COEF(0, 2));
+ SR(VID3_WB_CONV_COEF(0, 3));
+ SR(VID3_WB_CONV_COEF(0, 4));
+
+ SR(VID3_WB_FIR_COEF_V(0, 0));
+ SR(VID3_WB_FIR_COEF_V(0, 1));
+ SR(VID3_WB_FIR_COEF_V(0, 2));
+ SR(VID3_WB_FIR_COEF_V(0, 3));
+ SR(VID3_WB_FIR_COEF_V(0, 4));
+ SR(VID3_WB_FIR_COEF_V(0, 5));
+ SR(VID3_WB_FIR_COEF_V(0, 6));
+ SR(VID3_WB_FIR_COEF_V(0, 7));
+
+ SR(VID3_PRELOAD);
+ }
}
void dispc_restore_context(void)
@@ -553,6 +605,58 @@ void dispc_restore_context(void)
RR(VID_PRELOAD(1));
+ /* VID3 */
+ if (cpu_is_omap44xx()) {
+ SR(VID3_WB_BA0(0));
+ SR(VID3_WB_BA1(0));
+ SR(VID3_POSITION);
+ SR(VID3_WB_SIZE(0));
+ SR(VID3_WB_ATTRIBUTES(0));
+ SR(VID3_WB_BUF_THRESHOLD(0));
+ SR(VID3_WB_BUF_SIZE_STATUS(0));
+ SR(VID3_WB_ROW_INC(0));
+ SR(VID3_WB_PIXEL_INC(0));
+ SR(VID3_WB_FIR(0));
+ SR(VID3_WB_PICTURE_SIZE(0));
+ SR(VID3_WB_ACCU0(0));
+ SR(VID3_WB_ACCU1(0));
+
+ SR(VID3_WB_FIR_COEF_H(0, 0));
+ SR(VID3_WB_FIR_COEF_H(0, 1));
+ SR(VID3_WB_FIR_COEF_H(0, 2));
+ SR(VID3_WB_FIR_COEF_H(0, 3));
+ SR(VID3_WB_FIR_COEF_H(0, 4));
+ SR(VID3_WB_FIR_COEF_H(0, 5));
+ SR(VID3_WB_FIR_COEF_H(0, 6));
+ SR(VID3_WB_FIR_COEF_H(0, 7));
+
+ SR(VID3_WB_FIR_COEF_HV(0, 0));
+ SR(VID3_WB_FIR_COEF_HV(0, 1));
+ SR(VID3_WB_FIR_COEF_HV(0, 2));
+ SR(VID3_WB_FIR_COEF_HV(0, 3));
+ SR(VID3_WB_FIR_COEF_HV(0, 4));
+ SR(VID3_WB_FIR_COEF_HV(0, 5));
+ SR(VID3_WB_FIR_COEF_HV(0, 6));
+ SR(VID3_WB_FIR_COEF_HV(0, 7));
+
+ SR(VID3_WB_CONV_COEF(0, 0));
+ SR(VID3_WB_CONV_COEF(0, 1));
+ SR(VID3_WB_CONV_COEF(0, 2));
+ SR(VID3_WB_CONV_COEF(0, 3));
+ SR(VID3_WB_CONV_COEF(0, 4));
+
+ SR(VID3_WB_FIR_COEF_V(0, 0));
+ SR(VID3_WB_FIR_COEF_V(0, 1));
+ SR(VID3_WB_FIR_COEF_V(0, 2));
+ SR(VID3_WB_FIR_COEF_V(0, 3));
+ SR(VID3_WB_FIR_COEF_V(0, 4));
+ SR(VID3_WB_FIR_COEF_V(0, 5));
+ SR(VID3_WB_FIR_COEF_V(0, 6));
+ SR(VID3_WB_FIR_COEF_V(0, 7));
+
+ SR(VID3_PRELOAD);
+ }
+
/* enable last, because LCD & DIGIT enable are here */
RR(CONTROL(0));
if (cpu_is_omap44xx())
--
1.5.4.7
next prev parent reply other threads:[~2010-07-19 11:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-07-19 11:55 [PATCH 0/5] OMAP: DSS2: Video3 pipeline support for OMAP4 Archit Taneja
2010-07-19 11:55 ` [PATCH 1/5] OMAP: DSS2: Add Video3 pipeline in display.h Archit Taneja
2010-07-19 11:55 ` [PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC Archit Taneja
2010-07-19 11:55 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Archit Taneja
2010-07-19 11:55 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Archit Taneja
2010-07-19 11:55 ` Archit Taneja [this message]
2010-07-23 5:45 ` [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline registers Hiremath, Vaibhav
2010-07-23 5:55 ` Taneja, Archit
2010-07-23 5:57 ` Hiremath, Vaibhav
2010-07-23 5:40 ` [PATCH 4/5] OMAP: DSS2: Video3 pipeline IRQs Hiremath, Vaibhav
2010-07-23 5:46 ` Taneja, Archit
2010-07-23 5:52 ` Hiremath, Vaibhav
2010-07-23 5:24 ` [PATCH 3/5] OMAP: DSS2: Add new overlay object for Video3 pipeline Hiremath, Vaibhav
2010-07-23 5:38 ` Taneja, Archit
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