[PATCH 1/5] OMAP4: runtime: Enable PM runtime core for OMAP4

[PATCH 1/5] OMAP4: runtime: Enable PM runtime core for OMAP4

[Rajendra Nayak]

The PM runtime core functions are implemented in pm_bus.c
which needs to be compiled for CONFIG_ARCH_OMAP4 for
runtime api's to work.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/Makefile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 800b430..18db759 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -50,7 +50,7 @@ ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
-- 
1.5.4.7

[PATCH 2/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Rajendra Nayak]

From: Paul Walmsley <paul@pwsan.com>

Add hwmod structures for I2C controllers on OMAP2420/2430.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |  134 ++++++++++++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |  140 +++++++++++++++++++++++++++-
 2 files changed, 270 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e..892e733 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,9 +15,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/i2c.h>
+#include <plat/omap24xx.h>
 
 #include "omap_hwmod_common_data.h"
 
+#include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
 
 /*
@@ -71,6 +74,8 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
+static struct omap_hwmod omap2420_i2c1_hwmod;
+static struct omap_hwmod omap2420_i2c2_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -79,6 +84,45 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN		128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+	.master		= &omap2420_l4_core_hwmod,
+	.slave		= &omap2420_i2c1_hwmod,
+	.clk		= "i2c1_ick",
+	.addr		= omap2420_i2c1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2420_i2c1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+	.master		= &omap2420_l4_core_hwmod,
+	.slave		= &omap2420_i2c2_hwmod,
+	.clk		= "i2c2_ick",
+	.addr		= omap2420_i2c2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2420_i2c2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 	&omap2420_l3_main__l4_core,
@@ -87,6 +131,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 	&omap2420_l4_core__l4_wkup,
+	&omap2420_l4_core__i2c1,
+	&omap2420_l4_core__i2c2
 };
 
 /* L4 CORE */
@@ -165,6 +211,92 @@ static struct omap_hwmod omap2420_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+	.rev_offs	= 0x00,
+	.sysc_offs	= 0x20,
+	.syss_offs	= 0x10,
+	.sysc_flags	= SYSC_HAS_SOFTRESET,
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name		= "i2c",
+	.sysc		= &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP24XX_DMA_I2C1_TX },
+	{ .name = "rx", .dma_ch = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+	&omap2420_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
+	.sdma_chs	= i2c1_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c1_sdma_chs),
+	.main_clk	= "i2c1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2420_EN_I2C1_SHIFT,
+		},
+	},
+	.slaves		= omap2420_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_i2c1_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP24XX_DMA_I2C2_TX },
+	{ .name = "rx", .dma_ch = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+	&omap2420_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+	.name		= "i2c2",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
+	.sdma_chs	= i2c2_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c2_sdma_chs),
+	.main_clk	= "i2c2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2420_EN_I2C2_SHIFT,
+		},
+	},
+	.slaves		= omap2420_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_i2c2_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 	&omap2420_l3_main_hwmod,
 	&omap2420_l4_core_hwmod,
@@ -178,5 +310,3 @@ int __init omap2420_hwmod_init(void)
 {
 	return omap_hwmod_init(omap2420_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628..1f75a21 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,10 +15,13 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/i2c.h>
+#include <plat/omap24xx.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
 
 /*
  * OMAP2430 hardware module integration data
@@ -71,6 +74,47 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_i2c1_hwmod;
+static struct omap_hwmod omap2430_i2c2_hwmod;
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN		128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_i2c1_hwmod,
+	.clk		= "i2c1_ick",
+	.addr		= omap2430_i2c1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_i2c1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_i2c2_hwmod,
+	.clk		= "i2c2_ick",
+	.addr		= omap2430_i2c2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_i2c2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -165,6 +209,100 @@ static struct omap_hwmod omap2430_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+	.rev_offs	= 0x00,
+	.sysc_offs	= 0x20,
+	.syss_offs	= 0x10,
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name		= "i2c",
+	.sysc		= &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP24XX_DMA_I2C1_TX },
+	{ .name = "rx", .dma_ch = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+	&omap2430_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2430_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
+	.sdma_chs	= i2c1_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c1_sdma_chs),
+	.main_clk	= "i2c1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
+		},
+	},
+	.slaves		= omap2430_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c1_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c1_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP24XX_DMA_I2C2_TX },
+	{ .name = "rx", .dma_ch = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+	&omap2430_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2430_i2c2_hwmod = {
+	.name		= "i2c2_hwmod",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
+	.sdma_chs	= i2c2_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c2_sdma_chs),
+	.main_clk	= "i2c2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
+		},
+	},
+	.slaves		= omap2430_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c2_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c2_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 	&omap2430_l3_main_hwmod,
 	&omap2430_l4_core_hwmod,
@@ -178,5 +316,3 @@ int __init omap2430_hwmod_init(void)
 {
 	return omap_hwmod_init(omap2430_hwmods);
 }
-
-
-- 
1.5.4.7

[PATCH 3/5] OMAP3: hwmod: add I2C hwmods for OMAP3430

[Rajendra Nayak]

Add hwmod structures for I2C controllers on OMAP3430.

This patch was developed in collaboration with Paul Walmsley <paul@pwsan.com>.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  232 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm-regbits-34xx.h     |    3 +
 arch/arm/plat-omap/include/plat/i2c.h      |   13 ++
 arch/arm/plat-omap/include/plat/l4_3xxx.h  |   24 +++
 4 files changed, 272 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/l4_3xxx.h

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58..7ef093f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,6 +17,9 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/l4_3xxx.h>
+#include <plat/i2c.h>
+#include <plat/omap34xx.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -36,6 +39,9 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
 static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
+static struct omap_hwmod omap3xxx_i2c1_hwmod;
+static struct omap_hwmod omap3xxx_i2c2_hwmod;
+static struct omap_hwmod omap3xxx_i2c3_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -90,6 +96,85 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN		128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+	{
+		.pa_start	= 0x48070000,
+		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_i2c1_hwmod,
+	.clk		= "i2c1_ick",
+	.addr		= omap3xxx_i2c1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
+			.l4_prot_group = 7,
+			.flags	= OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+	{
+		.pa_start	= 0x48072000,
+		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_i2c2_hwmod,
+	.clk		= "i2c2_ick",
+	.addr		= omap3xxx_i2c2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
+			.l4_prot_group = 7,
+			.flags = OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+	{
+		.pa_start	= 0x48060000,
+		.pa_end		= 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_i2c3_hwmod,
+	.clk		= "i2c3_ick",
+	.addr		= omap3xxx_i2c3_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c3_addr_space),
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
+			.l4_prot_group = 7,
+			.flags = OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 	&omap3xxx_l3_main__l4_core,
@@ -98,6 +183,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 	&omap3xxx_l4_core__l4_wkup,
+	&omap3_l4_core__i2c1,
+	&omap3_l4_core__i2c2,
+	&omap3_l4_core__i2c3,
 };
 
 /* L4 CORE */
@@ -197,6 +285,147 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+	.rev_offs	= 0x00,
+	.sysc_offs	= 0x20,
+	.syss_offs	= 0x10,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+			   SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name = "i2c",
+	.sysc = &i2c_sysc,
+};
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP24XX_DMA_I2C1_TX },
+	{ .name = "rx", .dma_ch = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+	&omap3_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
+	.sdma_chs	= i2c1_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c1_sdma_chs),
+	.main_clk	= "i2c1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_GRPSEL_I2C1_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c1_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c1_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+	.fifo_depth	= 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP24XX_DMA_I2C2_TX },
+	{ .name = "rx", .dma_ch = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+	&omap3_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+	.name		= "i2c2",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
+	.sdma_chs	= i2c2_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c2_sdma_chs),
+	.main_clk	= "i2c2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_GRPSEL_I2C2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_GRPSEL_I2C2_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c2_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c2_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C3 */
+
+static struct omap_i2c_dev_attr i2c3_dev_attr = {
+	.fifo_depth	= 64, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+	{ .irq = INT_34XX_I2C3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c3_sdma_chs[] = {
+	{ .name = "tx", .dma_ch = OMAP34XX_DMA_I2C3_TX },
+	{ .name = "rx", .dma_ch = OMAP34XX_DMA_I2C3_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+	&omap3_l4_core__i2c3,
+};
+
+static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+	.name		= "i2c3",
+	.mpu_irqs	= i2c3_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(i2c3_mpu_irqs),
+	.sdma_chs	= i2c3_sdma_chs,
+	.sdma_chs_cnt	= ARRAY_SIZE(i2c3_sdma_chs),
+	.main_clk	= "i2c3_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_GRPSEL_I2C3_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_GRPSEL_I2C3_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_i2c3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c3_slaves),
+	.class		= &i2c_class,
+	.dev_attr	= &i2c3_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l3_main_hwmod,
 	&omap3xxx_l4_core_hwmod,
@@ -204,6 +433,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l4_wkup_hwmod,
 	&omap3xxx_mpu_hwmod,
 	&omap3xxx_iva_hwmod,
+	&omap3xxx_i2c1_hwmod,
+	&omap3xxx_i2c2_hwmod,
+	&omap3xxx_i2c3_hwmod,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 7fd6023..51c354e 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -101,8 +101,11 @@
 #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
 #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
 #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
+#define OMAP3430_GRPSEL_I2C3_SHIFT			17
 #define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
+#define OMAP3430_GRPSEL_I2C2_SHIFT			16
 #define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
+#define OMAP3430_GRPSEL_I2C1_SHIFT			15
 #define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
 #define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
 #define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2..255c756 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -34,5 +34,18 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+	u8	fifo_depth;
+	u8	flags;
+};
+
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
new file mode 100644
index 0000000..5e19493
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+
+/* L4 CORE */
+#define OMAP3_L4_CORE_FW_I2C1_REGION				21
+#define OMAP3_L4_CORE_FW_I2C1_TA_REGION				22
+#define OMAP3_L4_CORE_FW_I2C2_REGION				23
+#define OMAP3_L4_CORE_FW_I2C2_TA_REGION				24
+#define OMAP3_L4_CORE_FW_I2C3_REGION				73
+#define OMAP3_L4_CORE_FW_I2C3_TA_REGION				74
+
+#endif
-- 
1.5.4.7

[PATCH 4/5] OMAP: I2C: split device registration; convert OMAP2+ to omap_device

[Rajendra Nayak]

From: Paul Walmsley <paul@pwsan.com>

Split the OMAP1 and OMAP2+ platform_device build and register code.
Convert the OMAP2+ variant to use omap_device.

This patch was developed in collaboration with Rajendra Nayak
<rnayak@ti.com>.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/plat-omap/i2c.c |  161 +++++++++++++++++++++++++---------------------
 include/linux/i2c-omap.h |    5 ++
 2 files changed, 93 insertions(+), 73 deletions(-)

diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5ce4f0..f58b425 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,18 +27,18 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/i2c-omap.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/i2c.h>
 #include <plat/omap-pm.h>
+#include <plat/omap_device.h>
 
 #define OMAP_I2C_SIZE		0x3f
 #define OMAP1_I2C_BASE		0xfffb3800
-#define OMAP2_I2C_BASE1		0x48070000
-#define OMAP2_I2C_BASE2		0x48072000
-#define OMAP2_I2C_BASE3		0x48060000
-#define OMAP4_I2C_BASE4		0x48350000
 
 static const char name[] = "i2c_omap";
 
@@ -55,15 +55,6 @@ static const char name[] = "i2c_omap";
 
 static struct resource i2c_resources[][2] = {
 	{ I2C_RESOURCE_BUILDER(0, 0) },
-#if	defined(CONFIG_ARCH_OMAP2PLUS)
-	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
-#endif
-#if	defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
-#endif
-#if	defined(CONFIG_ARCH_OMAP4)
-	{ I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
-#endif
 };
 
 #define I2C_DEV_BUILDER(bus_id, res, data)		\
@@ -77,22 +68,19 @@ static struct resource i2c_resources[][2] = {
 		},					\
 	}
 
-static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN	16
+#define OMAP_I2C_MAX_CONTROLLERS 4
+static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
 static struct platform_device omap_i2c_devices[] = {
 	I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-#if	defined(CONFIG_ARCH_OMAP2PLUS)
-	I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
-#endif
-#if	defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-	I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
-#endif
-#if	defined(CONFIG_ARCH_OMAP4)
-	I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
-#endif
 };
 
 #define OMAP_I2C_CMDLINE_SETUP	(BIT(31))
 
+#define I2C_ICLK	0
+#define I2C_FCLK	1
+static struct clk *omap_i2c_clks[ARRAY_SIZE(omap_i2c_devices)][2];
+
 static int __init omap_i2c_nr_ports(void)
 {
 	int ports = 0;
@@ -109,35 +97,57 @@ static int __init omap_i2c_nr_ports(void)
 	return ports;
 }
 
-/* Shared between omap2 and 3 */
-static resource_size_t omap2_i2c_irq[3] __initdata = {
-	INT_24XX_I2C1_IRQ,
-	INT_24XX_I2C2_IRQ,
-	INT_34XX_I2C3_IRQ,
-};
+static int omap1_i2c_device_enable(struct platform_device *pdev)
+{
+	struct clk *c;
+	c = omap_i2c_clks[pdev->id - 1][I2C_ICLK];
+	if (c && !IS_ERR(c))
+		clk_enable(c);
 
-static resource_size_t omap4_i2c_irq[4] __initdata = {
-	OMAP44XX_IRQ_I2C1,
-	OMAP44XX_IRQ_I2C2,
-	OMAP44XX_IRQ_I2C3,
-	OMAP44XX_IRQ_I2C4,
-};
+	c = omap_i2c_clks[pdev->id - 1][I2C_FCLK];
+	if (c && !IS_ERR(c))
+		clk_enable(c);
+
+	return 0;
+}
+
+static int omap1_i2c_device_idle(struct platform_device *pdev)
+{
+	struct clk *c;
+
+	c = omap_i2c_clks[pdev->id - 1][I2C_FCLK];
+	if (c && !IS_ERR(c))
+		clk_disable(c);
 
-static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
+	c = omap_i2c_clks[pdev->id - 1][I2C_ICLK];
+	if (c && !IS_ERR(c))
+		clk_disable(c);
+
+	return 0;
+}
+
+static inline int omap1_i2c_add_bus(int bus_id)
 {
-	struct omap_i2c_bus_platform_data *pd;
-	struct resource *res;
-
-	pd = pdev->dev.platform_data;
-	res = pdev->resource;
-	res[0].start = OMAP1_I2C_BASE;
-	res[0].end = res[0].start + OMAP_I2C_SIZE;
-	res[1].start = INT_I2C;
+	struct platform_device *pdev;
+	struct omap_i2c_bus_platform_data *pdata;
+
 	omap1_i2c_mux_pins(bus_id);
 
+	pdev = &omap_i2c_devices[bus_id - 1];
+	pdata = &i2c_pdata[bus_id - 1];
+
+	/* idle and shutdown share the same code */
+	pdata->device_enable = omap1_i2c_device_enable;
+	pdata->device_idle = omap1_i2c_device_idle;
+	pdata->device_shutdown = omap1_i2c_device_idle;
+
+	omap_i2c_clks[bus_id - 1][I2C_ICLK] = clk_get(&pdev->dev, "ick");
+	omap_i2c_clks[bus_id - 1][I2C_FCLK] = clk_get(&pdev->dev, "fck");
+
 	return platform_device_register(pdev);
 }
 
+
 /*
  * XXX This function is a temporary compatibility wrapper - only
  * needed until the I2C driver can be converted to call
@@ -148,52 +158,57 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
 	omap_pm_set_max_mpu_wakeup_lat(dev, t);
 }
 
-static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
-{
-	struct resource *res;
-	resource_size_t *irq;
+static struct omap_device_pm_latency omap_i2c_latency[] = {
+	[0] = {
+		.deactivate_func	= omap_device_idle_hwmods,
+		.activate_func		= omap_device_enable_hwmods,
+		.flags			= OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+	},
+};
 
-	res = pdev->resource;
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+	int l;
+	struct omap_hwmod *oh;
+	struct omap_device *od;
+	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+	struct omap_i2c_bus_platform_data *pdata;
 
-	if (!cpu_is_omap44xx())
-		irq = omap2_i2c_irq;
-	else
-		irq = omap4_i2c_irq;
+	omap2_i2c_mux_pins(bus_id);
 
-	if (bus_id == 1) {
-		res[0].start = OMAP2_I2C_BASE1;
-		res[0].end = res[0].start + OMAP_I2C_SIZE;
+	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+		"String buffer overflow in I2C%d device setup\n", bus_id);
+	oh = omap_hwmod_lookup(oh_name);
+	if (!oh) {
+			pr_err("Could not look up %s\n", oh_name);
+			return -EEXIST;
 	}
 
-	res[1].start = irq[bus_id - 1];
-	omap2_i2c_mux_pins(bus_id);
-
+	pdata = &i2c_pdata[bus_id - 1];
 	/*
 	 * When waiting for completion of a i2c transfer, we need to
 	 * set a wake up latency constraint for the MPU. This is to
 	 * ensure quick enough wakeup from idle, when transfer
 	 * completes.
+	 * Only omap3 has support for constraints
 	 */
-	if (cpu_is_omap34xx()) {
-		struct omap_i2c_bus_platform_data *pd;
-
-		pd = pdev->dev.platform_data;
-		pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-	}
-
-	return platform_device_register(pdev);
+	if (cpu_is_omap34xx())
+		pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+	od = omap_device_build(name, bus_id, oh, pdata,
+			sizeof(struct omap_i2c_bus_platform_data),
+			omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
+	WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
+
+	return PTR_ERR(od);
 }
 
 static int __init omap_i2c_add_bus(int bus_id)
 {
-	struct platform_device *pdev;
-
-	pdev = &omap_i2c_devices[bus_id - 1];
-
 	if (cpu_class_is_omap1())
-		return omap1_i2c_add_bus(pdev, bus_id);
+		return omap1_i2c_add_bus(bus_id);
 	else
-		return omap2_i2c_add_bus(pdev, bus_id);
+		return omap2_i2c_add_bus(bus_id);
 }
 
 /**
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index 78ebf50..7472449 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -1,9 +1,14 @@
 #ifndef __I2C_OMAP_H__
 #define __I2C_OMAP_H__
 
+#include <linux/platform_device.h>
+
 struct omap_i2c_bus_platform_data {
 	u32		clkrate;
 	void		(*set_mpu_wkup_lat)(struct device *dev, long set);
+	int		(*device_enable) (struct platform_device *pdev);
+	int		(*device_shutdown) (struct platform_device *pdev);
+	int		(*device_idle) (struct platform_device *pdev);
 };
 
 #endif
-- 
1.5.4.7

[PATCH 5/5] OMAP: I2C: Convert i2c driver to use PM runtime api's

[Rajendra Nayak]

This patch converts the i2c driver to use PM runtime apis for OMAP2+
and omap_device api's for OMAP1

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
---
 drivers/i2c/busses/i2c-omap.c |   81 ++++++++++++++++++-----------------------
 1 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 7674efb..387f9c6 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -39,6 +39,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/i2c-omap.h>
+#include <linux/pm_runtime.h>
 
 /* I2C controller revisions */
 #define OMAP_I2C_REV_2			0x20
@@ -175,8 +176,6 @@ struct omap_i2c_dev {
 	void __iomem		*base;		/* virtual */
 	int			irq;
 	int			reg_shift;      /* bit shift for I2C register addresses */
-	struct clk		*iclk;		/* Interface clock */
-	struct clk		*fclk;		/* Functional clock */
 	struct completion	cmd_complete;
 	struct resource		*ioarea;
 	u32			latency;	/* maximum mpu wkup latency */
@@ -265,45 +264,25 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
 }
 
-static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
+static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 {
-	int ret;
-
-	dev->iclk = clk_get(dev->dev, "ick");
-	if (IS_ERR(dev->iclk)) {
-		ret = PTR_ERR(dev->iclk);
-		dev->iclk = NULL;
-		return ret;
-	}
-
-	dev->fclk = clk_get(dev->dev, "fck");
-	if (IS_ERR(dev->fclk)) {
-		ret = PTR_ERR(dev->fclk);
-		if (dev->iclk != NULL) {
-			clk_put(dev->iclk);
-			dev->iclk = NULL;
-		}
-		dev->fclk = NULL;
-		return ret;
-	}
+	struct platform_device *pdev;
+	struct omap_i2c_bus_platform_data *pdata;
 
-	return 0;
-}
+	WARN_ON(!dev->idle);
 
-static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
-{
-	clk_put(dev->fclk);
-	dev->fclk = NULL;
-	clk_put(dev->iclk);
-	dev->iclk = NULL;
-}
+	pdev = container_of(dev->dev, struct platform_device, dev);
+	pdata = pdev->dev.platform_data;
 
-static void omap_i2c_unidle(struct omap_i2c_dev *dev)
-{
-	WARN_ON(!dev->idle);
+	pm_runtime_get_sync(&pdev->dev);
+	/*
+	 * This is needed for now to have OMAP1
+	 * working as PM runtime is not yet
+	 * supported on OMAP1
+	 */
+	if (pdata->device_enable)
+		pdata->device_enable(pdev);
 
-	clk_enable(dev->iclk);
-	clk_enable(dev->fclk);
 	if (cpu_is_omap34xx()) {
 		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
@@ -326,10 +305,15 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 
 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 {
+	struct platform_device *pdev;
+	struct omap_i2c_bus_platform_data *pdata;
 	u16 iv;
 
 	WARN_ON(dev->idle);
 
+	pdev = container_of(dev->dev, struct platform_device, dev);
+	pdata = pdev->dev.platform_data;
+
 	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 	if (dev->rev >= OMAP_I2C_REV_ON_4430)
 		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
@@ -345,8 +329,15 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
 		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 	}
 	dev->idle = 1;
-	clk_disable(dev->fclk);
-	clk_disable(dev->iclk);
+
+	pm_runtime_put_sync(&pdev->dev);
+	/*
+	 * This is needed for now to have OMAP1
+	 * working as PM runtime is not yet
+	 * supported on OMAP1
+	 */
+	if (pdata->device_idle)
+		pdata->device_idle(pdev);
 }
 
 static int omap_i2c_init(struct omap_i2c_dev *dev)
@@ -356,6 +347,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	unsigned long fclk_rate = 12000000;
 	unsigned long timeout;
 	unsigned long internal_clk = 0;
+	struct clk *fclk;
 
 	if (dev->rev >= OMAP_I2C_REV_2) {
 		/* Disable I2C controller before soft reset */
@@ -414,7 +406,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 		 * always returns 12MHz for the functional clock, we can
 		 * do this bit unconditionally.
 		 */
-		fclk_rate = clk_get_rate(dev->fclk);
+		fclk = clk_get(dev->dev, "fck");
+		fclk_rate = clk_get_rate(fclk);
 
 		/* TRM for 5912 says the I2C clock must be prescaled to be
 		 * between 7 - 12 MHz. The XOR input clock is typically
@@ -443,7 +436,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			internal_clk = 9600;
 		else
 			internal_clk = 4000;
-		fclk_rate = clk_get_rate(dev->fclk) / 1000;
+		fclk = clk_get(dev->dev, "fck");
+		fclk_rate = clk_get_rate(fclk) / 1000;
 
 		/* Compute prescaler divisor */
 		psc = fclk_rate / internal_clk;
@@ -1046,14 +1040,12 @@ omap_i2c_probe(struct platform_device *pdev)
 	else
 		dev->reg_shift = 2;
 
-	if ((r = omap_i2c_get_clocks(dev)) != 0)
-		goto err_iounmap;
-
 	if (cpu_is_omap44xx())
 		dev->regs = (u8 *) omap4_reg_map;
 	else
 		dev->regs = (u8 *) reg_map;
 
+	pm_runtime_enable(&pdev->dev);
 	omap_i2c_unidle(dev);
 
 	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
@@ -1125,8 +1117,6 @@ err_free_irq:
 err_unuse_clocks:
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	omap_i2c_idle(dev);
-	omap_i2c_put_clocks(dev);
-err_iounmap:
 	iounmap(dev->base);
 err_free_mem:
 	platform_set_drvdata(pdev, NULL);
@@ -1148,7 +1138,6 @@ omap_i2c_remove(struct platform_device *pdev)
 	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
-	omap_i2c_put_clocks(dev);
 	iounmap(dev->base);
 	kfree(dev);
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- 
1.5.4.7

Re: [PATCH 1/5] OMAP4: runtime: Enable PM runtime core for OMAP4

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> The PM runtime core functions are implemented in pm_bus.c
> which needs to be compiled for CONFIG_ARCH_OMAP4 for
> runtime api's to work.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>

I'll fold this one into the OMAP runtime PM core series (pm-wip/runtime
branch) so this goes upstream with the core code.

Thanks,

Kevin

> ---
>  arch/arm/mach-omap2/Makefile |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 800b430..18db759 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -50,7 +50,7 @@ ifeq ($(CONFIG_PM),y)
>  obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
>  obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
>  obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o
> -obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o
> +obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
>  obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
>  
>  AFLAGS_sleep24xx.o			:=-Wa,-march=armv6

Re: [PATCH 2/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> From: Paul Walmsley <paul@pwsan.com>
>
> Add hwmod structures for I2C controllers on OMAP2420/2430.
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_2420_data.c |  134 ++++++++++++++++++++++++++-
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c |  140 +++++++++++++++++++++++++++-
>  2 files changed, 270 insertions(+), 4 deletions(-)
>

[...]

> +static struct omap_hwmod omap2420_i2c1_hwmod = {
> +	.name		= "i2c1",
> +	.mpu_irqs	= i2c1_mpu_irqs,
> +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> +	.sdma_chs	= i2c1_sdma_chs,
> +	.sdma_chs_cnt	= ARRAY_SIZE(i2c1_sdma_chs),
> +	.main_clk	= "i2c1_fck",
> +	.prcm		= {
> +		.omap2 = {
> +			.prcm_reg_id = 1,
> +			.module_bit = OMAP2420_EN_I2C1_SHIFT,
> +		},
> +	},

This needs to be validated on OMAP2.

I think the enable will fail without the .idlest* fields filled out.

Kevin


> +

Re: [PATCH 5/5] OMAP: I2C: Convert i2c driver to use PM runtime api's

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> This patch converts the i2c driver to use PM runtime apis for OMAP2+
> and omap_device api's for OMAP1
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Paul Walmsley <paul@pwsan.com>

Some minor comments below, but otherwise looks like the right direction.

Kevin

> ---
>  drivers/i2c/busses/i2c-omap.c |   81 ++++++++++++++++++-----------------------
>  1 files changed, 35 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 7674efb..387f9c6 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -39,6 +39,7 @@
>  #include <linux/io.h>
>  #include <linux/slab.h>
>  #include <linux/i2c-omap.h>
> +#include <linux/pm_runtime.h>
>  
>  /* I2C controller revisions */
>  #define OMAP_I2C_REV_2			0x20
> @@ -175,8 +176,6 @@ struct omap_i2c_dev {
>  	void __iomem		*base;		/* virtual */
>  	int			irq;
>  	int			reg_shift;      /* bit shift for I2C register addresses */
> -	struct clk		*iclk;		/* Interface clock */
> -	struct clk		*fclk;		/* Functional clock */
>  	struct completion	cmd_complete;
>  	struct resource		*ioarea;
>  	u32			latency;	/* maximum mpu wkup latency */
> @@ -265,45 +264,25 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
>  				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
>  }
>  
> -static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
> +static void omap_i2c_unidle(struct omap_i2c_dev *dev)
>  {
> -	int ret;
> -
> -	dev->iclk = clk_get(dev->dev, "ick");
> -	if (IS_ERR(dev->iclk)) {
> -		ret = PTR_ERR(dev->iclk);
> -		dev->iclk = NULL;
> -		return ret;
> -	}
> -
> -	dev->fclk = clk_get(dev->dev, "fck");
> -	if (IS_ERR(dev->fclk)) {
> -		ret = PTR_ERR(dev->fclk);
> -		if (dev->iclk != NULL) {
> -			clk_put(dev->iclk);
> -			dev->iclk = NULL;
> -		}
> -		dev->fclk = NULL;
> -		return ret;
> -	}
> +	struct platform_device *pdev;
> +	struct omap_i2c_bus_platform_data *pdata;
>  
> -	return 0;
> -}
> +	WARN_ON(!dev->idle);
>  
> -static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
> -{
> -	clk_put(dev->fclk);
> -	dev->fclk = NULL;
> -	clk_put(dev->iclk);
> -	dev->iclk = NULL;
> -}
> +	pdev = container_of(dev->dev, struct platform_device, dev);

<linux/platform_device.h> provides to_platform_device() for this

> +	pdata = pdev->dev.platform_data;
>  
> -static void omap_i2c_unidle(struct omap_i2c_dev *dev)
> -{
> -	WARN_ON(!dev->idle);
> +	pm_runtime_get_sync(&pdev->dev);
> +	/*
> +	 * This is needed for now to have OMAP1
> +	 * working as PM runtime is not yet
> +	 * supported on OMAP1
> +	 */
> +	if (pdata->device_enable)
> +		pdata->device_enable(pdev);

OMAP1 should work fine on the pm-wip/rutime branch as there is a simple
runtime PM core for OMAP1 implemented that just manages clocks.

> -	clk_enable(dev->iclk);
> -	clk_enable(dev->fclk);
>  	if (cpu_is_omap34xx()) {
>  		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
>  		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
> @@ -326,10 +305,15 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
>  
>  static void omap_i2c_idle(struct omap_i2c_dev *dev)
>  {
> +	struct platform_device *pdev;
> +	struct omap_i2c_bus_platform_data *pdata;
>  	u16 iv;
>  
>  	WARN_ON(dev->idle);
>  
> +	pdev = container_of(dev->dev, struct platform_device, dev);
> +	pdata = pdev->dev.platform_data;
> +
>  	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
>  	if (dev->rev >= OMAP_I2C_REV_ON_4430)
>  		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
> @@ -345,8 +329,15 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
>  		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
>  	}
>  	dev->idle = 1;
> -	clk_disable(dev->fclk);
> -	clk_disable(dev->iclk);
> +
> +	pm_runtime_put_sync(&pdev->dev);
> +	/*
> +	 * This is needed for now to have OMAP1
> +	 * working as PM runtime is not yet
> +	 * supported on OMAP1
> +	 */
> +	if (pdata->device_idle)
> +		pdata->device_idle(pdev);

ditto

>  }
>  
>  static int omap_i2c_init(struct omap_i2c_dev *dev)
> @@ -356,6 +347,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  	unsigned long fclk_rate = 12000000;
>  	unsigned long timeout;
>  	unsigned long internal_clk = 0;
> +	struct clk *fclk;
>  
>  	if (dev->rev >= OMAP_I2C_REV_2) {
>  		/* Disable I2C controller before soft reset */
> @@ -414,7 +406,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  		 * always returns 12MHz for the functional clock, we can
>  		 * do this bit unconditionally.
>  		 */
> -		fclk_rate = clk_get_rate(dev->fclk);
> +		fclk = clk_get(dev->dev, "fck");
> +		fclk_rate = clk_get_rate(fclk);
>  
>  		/* TRM for 5912 says the I2C clock must be prescaled to be
>  		 * between 7 - 12 MHz. The XOR input clock is typically
> @@ -443,7 +436,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  			internal_clk = 9600;
>  		else
>  			internal_clk = 4000;
> -		fclk_rate = clk_get_rate(dev->fclk) / 1000;
> +		fclk = clk_get(dev->dev, "fck");
> +		fclk_rate = clk_get_rate(fclk) / 1000;
>  
>  		/* Compute prescaler divisor */
>  		psc = fclk_rate / internal_clk;
> @@ -1046,14 +1040,12 @@ omap_i2c_probe(struct platform_device *pdev)
>  	else
>  		dev->reg_shift = 2;
>  
> -	if ((r = omap_i2c_get_clocks(dev)) != 0)
> -		goto err_iounmap;
> -
>  	if (cpu_is_omap44xx())
>  		dev->regs = (u8 *) omap4_reg_map;
>  	else
>  		dev->regs = (u8 *) reg_map;
>  
> +	pm_runtime_enable(&pdev->dev);
>  	omap_i2c_unidle(dev);
>  
>  	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
> @@ -1125,8 +1117,6 @@ err_free_irq:
>  err_unuse_clocks:
>  	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
>  	omap_i2c_idle(dev);
> -	omap_i2c_put_clocks(dev);
> -err_iounmap:
>  	iounmap(dev->base);
>  err_free_mem:
>  	platform_set_drvdata(pdev, NULL);
> @@ -1148,7 +1138,6 @@ omap_i2c_remove(struct platform_device *pdev)
>  	free_irq(dev->irq, dev);
>  	i2c_del_adapter(&dev->adapter);
>  	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
> -	omap_i2c_put_clocks(dev);
>  	iounmap(dev->base);
>  	kfree(dev);
>  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

RE: [PATCH 2/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430

[Nayak, Rajendra]

> -----Original Message-----
> From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> Sent: Tuesday, August 24, 2010 3:49 AM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org; Paul Walmsley
> Subject: Re: [PATCH 2/5] OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430
> 
> Rajendra Nayak <rnayak@ti.com> writes:
> 
> > From: Paul Walmsley <paul@pwsan.com>
> >
> > Add hwmod structures for I2C controllers on OMAP2420/2430.
> >
> > Signed-off-by: Paul Walmsley <paul@pwsan.com>
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> > Cc: Kevin Hilman <khilman@deeprootsystems.com>
> > ---
> >  arch/arm/mach-omap2/omap_hwmod_2420_data.c |  134
> ++++++++++++++++++++++++++-
> >  arch/arm/mach-omap2/omap_hwmod_2430_data.c |  140
> +++++++++++++++++++++++++++-
> >  2 files changed, 270 insertions(+), 4 deletions(-)
> >
> 
> [...]
> 
> > +static struct omap_hwmod omap2420_i2c1_hwmod = {
> > +	.name		= "i2c1",
> > +	.mpu_irqs	= i2c1_mpu_irqs,
> > +	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
> > +	.sdma_chs	= i2c1_sdma_chs,
> > +	.sdma_chs_cnt	= ARRAY_SIZE(i2c1_sdma_chs),
> > +	.main_clk	= "i2c1_fck",
> > +	.prcm		= {
> > +		.omap2 = {
> > +			.prcm_reg_id = 1,
> > +			.module_bit = OMAP2420_EN_I2C1_SHIFT,
> > +		},
> > +	},
> 
> This needs to be validated on OMAP2.
> 
> I think the enable will fail without the .idlest* fields filled out.

Hi Kevin,

I'll make sure I boot test on a N800 before I post the next version
of this series.

Thanks,
Rajendra


> 
> Kevin
> 
> 
> > +

RE: [PATCH 5/5] OMAP: I2C: Convert i2c driver to use PM runtime api's

[Nayak, Rajendra]

> -----Original Message-----
> From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> Sent: Tuesday, August 24, 2010 3:53 AM
> To: Nayak, Rajendra
> Cc: linux-omap@vger.kernel.org; Paul Walmsley
> Subject: Re: [PATCH 5/5] OMAP: I2C: Convert i2c driver to use PM runtime api's
> 
> Rajendra Nayak <rnayak@ti.com> writes:
> 
> > This patch converts the i2c driver to use PM runtime apis for OMAP2+
> > and omap_device api's for OMAP1
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> > Cc: Kevin Hilman <khilman@deeprootsystems.com>
> > Cc: Paul Walmsley <paul@pwsan.com>
> 
> Some minor comments below, but otherwise looks like the right direction.

Hi Kevin,

Thanks, I'll fix these in the next version.
Rajendra
> 
> Kevin
> 
> > ---
> >  drivers/i2c/busses/i2c-omap.c |   81 ++++++++++++++++++-------------------
> ----
> >  1 files changed, 35 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> > index 7674efb..387f9c6 100644
> > --- a/drivers/i2c/busses/i2c-omap.c
> > +++ b/drivers/i2c/busses/i2c-omap.c
> > @@ -39,6 +39,7 @@
> >  #include <linux/io.h>
> >  #include <linux/slab.h>
> >  #include <linux/i2c-omap.h>
> > +#include <linux/pm_runtime.h>
> >
> >  /* I2C controller revisions */
> >  #define OMAP_I2C_REV_2			0x20
> > @@ -175,8 +176,6 @@ struct omap_i2c_dev {
> >  	void __iomem		*base;		/* virtual */
> >  	int			irq;
> >  	int			reg_shift;      /* bit shift for I2C register addresses */
> > -	struct clk		*iclk;		/* Interface clock */
> > -	struct clk		*fclk;		/* Functional clock */
> >  	struct completion	cmd_complete;
> >  	struct resource		*ioarea;
> >  	u32			latency;	/* maximum mpu wkup latency */
> > @@ -265,45 +264,25 @@ static inline u16 omap_i2c_read_reg(struct
> omap_i2c_dev *i2c_dev, int reg)
> >  				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
> >  }
> >
> > -static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
> > +static void omap_i2c_unidle(struct omap_i2c_dev *dev)
> >  {
> > -	int ret;
> > -
> > -	dev->iclk = clk_get(dev->dev, "ick");
> > -	if (IS_ERR(dev->iclk)) {
> > -		ret = PTR_ERR(dev->iclk);
> > -		dev->iclk = NULL;
> > -		return ret;
> > -	}
> > -
> > -	dev->fclk = clk_get(dev->dev, "fck");
> > -	if (IS_ERR(dev->fclk)) {
> > -		ret = PTR_ERR(dev->fclk);
> > -		if (dev->iclk != NULL) {
> > -			clk_put(dev->iclk);
> > -			dev->iclk = NULL;
> > -		}
> > -		dev->fclk = NULL;
> > -		return ret;
> > -	}
> > +	struct platform_device *pdev;
> > +	struct omap_i2c_bus_platform_data *pdata;
> >
> > -	return 0;
> > -}
> > +	WARN_ON(!dev->idle);
> >
> > -static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
> > -{
> > -	clk_put(dev->fclk);
> > -	dev->fclk = NULL;
> > -	clk_put(dev->iclk);
> > -	dev->iclk = NULL;
> > -}
> > +	pdev = container_of(dev->dev, struct platform_device, dev);
> 
> <linux/platform_device.h> provides to_platform_device() for this
> 
> > +	pdata = pdev->dev.platform_data;
> >
> > -static void omap_i2c_unidle(struct omap_i2c_dev *dev)
> > -{
> > -	WARN_ON(!dev->idle);
> > +	pm_runtime_get_sync(&pdev->dev);
> > +	/*
> > +	 * This is needed for now to have OMAP1
> > +	 * working as PM runtime is not yet
> > +	 * supported on OMAP1
> > +	 */
> > +	if (pdata->device_enable)
> > +		pdata->device_enable(pdev);
> 
> OMAP1 should work fine on the pm-wip/rutime branch as there is a simple
> runtime PM core for OMAP1 implemented that just manages clocks.
> 
> > -	clk_enable(dev->iclk);
> > -	clk_enable(dev->fclk);
> >  	if (cpu_is_omap34xx()) {
> >  		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
> >  		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
> > @@ -326,10 +305,15 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
> >
> >  static void omap_i2c_idle(struct omap_i2c_dev *dev)
> >  {
> > +	struct platform_device *pdev;
> > +	struct omap_i2c_bus_platform_data *pdata;
> >  	u16 iv;
> >
> >  	WARN_ON(dev->idle);
> >
> > +	pdev = container_of(dev->dev, struct platform_device, dev);
> > +	pdata = pdev->dev.platform_data;
> > +
> >  	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
> >  	if (dev->rev >= OMAP_I2C_REV_ON_4430)
> >  		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
> > @@ -345,8 +329,15 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
> >  		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
> >  	}
> >  	dev->idle = 1;
> > -	clk_disable(dev->fclk);
> > -	clk_disable(dev->iclk);
> > +
> > +	pm_runtime_put_sync(&pdev->dev);
> > +	/*
> > +	 * This is needed for now to have OMAP1
> > +	 * working as PM runtime is not yet
> > +	 * supported on OMAP1
> > +	 */
> > +	if (pdata->device_idle)
> > +		pdata->device_idle(pdev);
> 
> ditto
> 
> >  }
> >
> >  static int omap_i2c_init(struct omap_i2c_dev *dev)
> > @@ -356,6 +347,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> >  	unsigned long fclk_rate = 12000000;
> >  	unsigned long timeout;
> >  	unsigned long internal_clk = 0;
> > +	struct clk *fclk;
> >
> >  	if (dev->rev >= OMAP_I2C_REV_2) {
> >  		/* Disable I2C controller before soft reset */
> > @@ -414,7 +406,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> >  		 * always returns 12MHz for the functional clock, we can
> >  		 * do this bit unconditionally.
> >  		 */
> > -		fclk_rate = clk_get_rate(dev->fclk);
> > +		fclk = clk_get(dev->dev, "fck");
> > +		fclk_rate = clk_get_rate(fclk);
> >
> >  		/* TRM for 5912 says the I2C clock must be prescaled to be
> >  		 * between 7 - 12 MHz. The XOR input clock is typically
> > @@ -443,7 +436,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> >  			internal_clk = 9600;
> >  		else
> >  			internal_clk = 4000;
> > -		fclk_rate = clk_get_rate(dev->fclk) / 1000;
> > +		fclk = clk_get(dev->dev, "fck");
> > +		fclk_rate = clk_get_rate(fclk) / 1000;
> >
> >  		/* Compute prescaler divisor */
> >  		psc = fclk_rate / internal_clk;
> > @@ -1046,14 +1040,12 @@ omap_i2c_probe(struct platform_device *pdev)
> >  	else
> >  		dev->reg_shift = 2;
> >
> > -	if ((r = omap_i2c_get_clocks(dev)) != 0)
> > -		goto err_iounmap;
> > -
> >  	if (cpu_is_omap44xx())
> >  		dev->regs = (u8 *) omap4_reg_map;
> >  	else
> >  		dev->regs = (u8 *) reg_map;
> >
> > +	pm_runtime_enable(&pdev->dev);
> >  	omap_i2c_unidle(dev);
> >
> >  	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
> > @@ -1125,8 +1117,6 @@ err_free_irq:
> >  err_unuse_clocks:
> >  	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
> >  	omap_i2c_idle(dev);
> > -	omap_i2c_put_clocks(dev);
> > -err_iounmap:
> >  	iounmap(dev->base);
> >  err_free_mem:
> >  	platform_set_drvdata(pdev, NULL);
> > @@ -1148,7 +1138,6 @@ omap_i2c_remove(struct platform_device *pdev)
> >  	free_irq(dev->irq, dev);
> >  	i2c_del_adapter(&dev->adapter);
> >  	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
> > -	omap_i2c_put_clocks(dev);
> >  	iounmap(dev->base);
> >  	kfree(dev);
> >  	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);