[PATCH v2 00/11] OMAP4: Smartreflex and Voltage layer support

[PATCH v2 00/11] OMAP4: Smartreflex and Voltage layer support

[Thara Gopinath]

This patch series adds support for OMAP4 support in the
smartreflex and voltage layer. The series involves extensions
to voltage layer and smartreflex layer for supporting OMAP4.
In addition it involves changes to pm debugfs layer to support
OMAP4 so that smartreflex and voltage debug entries can be
viewed, changes in opp layer so that opp layer gets enabled
for OMAP4, some changes in OMAP4 clock database and finally
addition of OMAP4 opp tables.
All these patches might not be dependent on voltage and
smartreflex layer but is required for the correct
functionality of these layers for OMAP4.

This series in based off origin/pm-core and origin/pm-opp
branches off Kevin Hilman' PM tree. But for this series to compile
and work properly one will have to apply the following
additional patches also.
	http://dev.omapzoom.org/?p=santosh/kernel-omap4-base.git;a=summary
		branch - omap4_scm_2.6.37
	http://marc.info/?l=linux-omap&m=128516673609816&w=2

All these patches are also available at 
	http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=summary
	head: thara-pm-sr

This patch series has been tested on OMAP4430 SDP with omap3_defconfig
and omap_4430dsp_defconfig with the following menuconfig options enabled
        System type -> TI OMAP Implementations -> Smartreflex Support
        System type -> TI OMAP Implementations ->
                Class 3 mode of Smartreflex Implementation

Benoit Cousson (1):
  OMAP4: hwmod: Add inital data for smartreflex modules.

Thara Gopinath (10):
  OMAP4: PM debugfs support
  OMAP4: OPP framework support
  OMAP4: Add the new voltage to vsel calculation formula
  OMAP4: Extend clock data.
  OMAP4: Adding voltage driver support
  OMAP4: PM: Program correct init voltages for scalable VDDs
  OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data
  OMAP4: Smartreflex framework extensions
  OMAP4: Enabling smartrefles class 3 driver.
  OMAP4: Add opp tables.

 arch/arm/mach-omap2/Makefile               |    3 +-
 arch/arm/mach-omap2/board-4430sdp.c        |    2 +
 arch/arm/mach-omap2/clock44xx_data.c       |   40 ++++-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  219 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/opp44xx_data.c         |   99 +++++++++++++
 arch/arm/mach-omap2/pm-debug.c             |   28 ++--
 arch/arm/mach-omap2/pm.c                   |    5 +
 arch/arm/mach-omap2/pm.h                   |    1 +
 arch/arm/mach-omap2/smartreflex.c          |    8 +-
 arch/arm/mach-omap2/sr_device.c            |   15 ++-
 arch/arm/mach-omap2/voltage.c              |  211 ++++++++++++++++++++++++++-
 arch/arm/plat-omap/Kconfig                 |    2 +-
 arch/arm/plat-omap/Makefile                |    1 +
 arch/arm/plat-omap/include/plat/control.h  |   12 ++
 arch/arm/plat-omap/include/plat/voltage.h  |   20 +++-
 arch/arm/plat-omap/opp_twl_tps.c           |   71 +++++++++
 16 files changed, 707 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/mach-omap2/opp44xx_data.c

[PATCH v2 01/11] OMAP4: PM debugfs support

[Thara Gopinath]

This patch extends pm debugfs to support OMAP4 debug entries
also. Currently PM register dump support is not added for OMAP4.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm-debug.c |   28 +++++++++++++++-------------
 1 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 7d95112..29ca4b4 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -617,7 +617,7 @@ static int __init pm_dbg_init(void)
 
 	if (cpu_is_omap34xx())
 		pm_dbg_reg_modules = omap3_pm_reg_modules;
-	else {
+	else if (!cpu_is_omap44xx()) {
 		printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
 		return -ENODEV;
 	}
@@ -633,20 +633,22 @@ static int __init pm_dbg_init(void)
 
 	pwrdm_for_each(pwrdms_setup, (void *)d);
 
-	pm_dbg_dir = debugfs_create_dir("registers", d);
-	if (IS_ERR(pm_dbg_dir))
-		return PTR_ERR(pm_dbg_dir);
+	if (cpu_is_omap34xx()) {
+		pm_dbg_dir = debugfs_create_dir("registers", d);
+		if (IS_ERR(pm_dbg_dir))
+			return PTR_ERR(pm_dbg_dir);
 
-	(void) debugfs_create_file("current", S_IRUGO,
-		pm_dbg_dir, (void *)0, &debug_reg_fops);
+		(void) debugfs_create_file("current", S_IRUGO,
+			pm_dbg_dir, (void *)0, &debug_reg_fops);
 
-	for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
-		if (pm_dbg_reg_set[i] != NULL) {
-			sprintf(name, "%d", i+1);
-			(void) debugfs_create_file(name, S_IRUGO,
-				pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
-
-		}
+		for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
+			if (pm_dbg_reg_set[i] != NULL) {
+				sprintf(name, "%d", i+1);
+				(void) debugfs_create_file(name, S_IRUGO,
+					pm_dbg_dir, (void *)(i+1),
+					&debug_reg_fops);
+			}
+	}
 
 	(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
 				   &enable_off_mode, &pm_dbg_option_fops);
-- 
1.7.0.4

[PATCH v2 02/11] OMAP4: OPP framework support

[Thara Gopinath]

This patch allows the compilation of the generic
opp layer for OMAP4 also.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/plat-omap/Makefile |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 852fa33..cbf8f2e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 # OPP support in (OMAP3+ only at the moment)
 ifdef CONFIG_PM
 obj-$(CONFIG_ARCH_OMAP3) += opp.o
+obj-$(CONFIG_ARCH_OMAP4) += opp.o
 obj-$(CONFIG_TWL4030_CORE) += opp_twl_tps.o
 endif
 
-- 
1.7.0.4

[PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula

[Thara Gopinath]

TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs,
blaze boards and panda boards has a different formula
from that of TWL4030 for voltage to vsel and
vsel to voltage calculation. This patch implements the new
formula depending on the PMIC type.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/plat-omap/opp_twl_tps.c |   71 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/opp_twl_tps.c b/arch/arm/plat-omap/opp_twl_tps.c
index 4448fc5..358b67b 100644
--- a/arch/arm/plat-omap/opp_twl_tps.c
+++ b/arch/arm/plat-omap/opp_twl_tps.c
@@ -15,9 +15,16 @@
 
 #include <linux/module.h>
 
+#include <linux/i2c/twl.h>
+
 #include <plat/opp_twl_tps.h>
 #include <plat/voltage.h>
 
+static bool is_offset_valid;
+static u8 smps_offset;
+
+#define REG_SMPS_OFFSET         0xE0
+
 /**
  * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
  * @vsel: TWL/TPS VSEL value to convert
@@ -27,6 +34,38 @@
  */
 unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 {
+	if (twl_class_is_6030()) {
+		/*
+		 * In TWL6030 depending on the value of SMPS_OFFSET
+		 * efuse register the voltage range supported in
+		 * standard mode can be either between 0.6V - 1.3V or
+		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+		 * is programmed to all 0's where as starting from
+		 * TWL6030 ES1.1 the efuse is programmed to 1
+		 */
+		if (!is_offset_valid) {
+			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, 0xE0);
+			is_offset_valid = true;
+		}
+
+		if (smps_offset & 0x8) {
+			return ((((vsel - 1) * 125) + 7000)) * 100;
+		} else {
+			/*
+			 * In case of the supported voltage range being
+			 * between 0.6V - 1.3V, there is not specific
+			 * formula for voltage to vsel conversion above
+			 * 1.3V. There are special hardcoded values for
+			 * voltages above 1.3V. Currently we are hardcodig
+			 * only for 1.35 V which is used for 1GH OPP for
+			 * OMAP4430.
+			 */
+			if (vsel == 0x3A)
+				return 1350000;
+			return ((((vsel - 1) * 125) + 6000)) * 100;
+		}
+	}
+
 	return (((vsel * 125) + 6000)) * 100;
 }
 
@@ -40,6 +79,38 @@ unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 u8 omap_twl_uv_to_vsel(unsigned long uv)
 {
 	/* Round up to higher voltage */
+	if (twl_class_is_6030()) {
+		/*
+		 * In TWL6030 depending on the value of SMPS_OFFSET
+		 * efuse register the voltage range supported in
+		 * standard mode can be either between 0.6V - 1.3V or
+		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+		 * is programmed to all 0's where as starting from
+		 * TWL6030 ES1.1 the efuse is programmed to 1
+		 */
+		if (!is_offset_valid) {
+			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, 0xE0);
+			is_offset_valid = true;
+		}
+
+		if (smps_offset & 0x8) {
+			return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+		} else {
+			/*
+			 * In case of the supported voltage range being
+			 * between 0.6V - 1.3V, there is not specific
+			 * formula for voltage to vsel conversion above
+			 * 1.3V. There are special hardcoded values for
+			 * voltages above 1.3V. Currently we are hardcodig
+			 * only for 1.35 V which is used for 1GH OPP for
+			 * OMAP4430.
+			 */
+			if (uv == 1350000)
+				return 0x3A;
+			return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+		}
+	}
+
 	return DIV_ROUND_UP(uv - 600000, 12500);
 }
 
-- 
1.7.0.4

[PATCH v2 04/11] OMAP4: Extend clock data.

[Thara Gopinath]

This patch extends the OMAP4 clock data to include
various x2 clockc nodes as the clock framework
skips a *2 whie calculating the dpll locked frequency.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/clock44xx_data.c |   40 +++++++++++++++++++++++++++------
 1 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index edf2c28..3652fda 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -481,14 +481,21 @@ static struct clk dpll_core_m5_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_core_m5x2_ck = {
+	.name		= "dpll_core_m5x2_ck",
+	.parent		= &dpll_core_m5_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 static const struct clksel div_core_div[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 	{ .parent = NULL },
 };
 
 static struct clk div_core_ck = {
 	.name		= "div_core_ck",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_core_div,
 	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
 	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,
@@ -507,13 +514,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
 };
 
 static const struct clksel div_iva_hs_clk_div[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 	{ .parent = NULL },
 };
 
 static struct clk div_iva_hs_clk = {
 	.name		= "div_iva_hs_clk",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_iva_hs_clk_div,
 	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
 	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
@@ -525,7 +532,7 @@ static struct clk div_iva_hs_clk = {
 
 static struct clk div_mpu_hs_clk = {
 	.name		= "div_mpu_hs_clk",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_iva_hs_clk_div,
 	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
 	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
@@ -651,6 +658,13 @@ static struct clk dpll_iva_m4_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_iva_m4x2_ck = {
+	.name		= "dpll_iva_m4x2_ck",
+	.parent		= &dpll_iva_m4_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 static struct clk dpll_iva_m5_ck = {
 	.name		= "dpll_iva_m5_ck",
 	.parent		= &dpll_iva_ck,
@@ -663,6 +677,13 @@ static struct clk dpll_iva_m5_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_iva_m5x2_ck = {
+	.name		= "dpll_iva_m5x2_ck",
+	.parent		= &dpll_iva_m5_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 /* DPLL_MPU */
 static struct dpll_data dpll_mpu_dd = {
 	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
@@ -1350,7 +1371,7 @@ static struct clk dsp_fck = {
 	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "tesla_clkdm",
-	.parent		= &dpll_iva_m4_ck,
+	.parent		= &dpll_iva_m4x2_ck,
 	.recalc		= &followparent_recalc,
 };
 
@@ -1725,7 +1746,7 @@ static struct clk iva_fck = {
 	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5_ck,
+	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
 };
 
@@ -2089,7 +2110,7 @@ static struct clk sl2if_ick = {
 	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5_ck,
+	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
 };
 
@@ -2782,6 +2803,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck,	CK_443X),
 	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck,	CK_443X),
 	CLK(NULL,	"dpll_core_m5_ck",		&dpll_core_m5_ck,	CK_443X),
+	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck,	CK_443X),
 	CLK(NULL,	"div_core_ck",			&div_core_ck,	CK_443X),
 	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk,	CK_443X),
 	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk,	CK_443X),
@@ -2793,7 +2815,9 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_m4_ck",		&dpll_iva_m4_ck,	CK_443X),
+	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_m5_ck",		&dpll_iva_m5_ck,	CK_443X),
+	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck,	CK_443X),
 	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck,	CK_443X),
 	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck,	CK_443X),
 	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck,	CK_443X),
-- 
1.7.0.4

[PATCH v2 05/11] OMAP4: Adding voltage driver support

[Thara Gopinath]

OMAP4 has three scalable voltage domains vdd_mpu, vdd_iva
and vdd_core. This patch adds the voltage tables and other
configurable voltage processor and voltage controller
settings to control these three scalable domains in OMAP4.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/Makefile              |    2 +-
 arch/arm/mach-omap2/voltage.c             |  211 ++++++++++++++++++++++++++++-
 arch/arm/plat-omap/include/plat/voltage.h |   20 +++-
 3 files changed, 229 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 38458b7..b18d171 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o voltage.o \
 					   cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 5375bf9..03cfd7d 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -29,6 +29,8 @@
 #include <plat/voltage.h>
 
 #include "prm-regbits-34xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
 #include "pm.h"
 
 #define VP_IDLE_TIMEOUT		200
@@ -148,7 +150,50 @@ static struct omap_vdd_info omap3_vdd_info[] = {
 
 #define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
 
-/* TODO: OMAP4 register offsets */
+/* OMAP4 VDD sturctures */
+static struct omap_vdd_info omap4_vdd_info[] = {
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "mpu",
+		},
+	},
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "iva",
+		},
+	},
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "core",
+		},
+	},
+};
+
+#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
 
 /*
  * Default voltage controller settings.
@@ -212,6 +257,29 @@ static struct omap_volt_data omap36xx_vdd2_volt_data[] = {
 	{.volt_nominal = 1137500, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
 };
 
+/*
+ * Structures containing OMAP4430 voltage supported and various
+ * data associated with it per voltage domain basis. Smartreflex Ntarget
+ * values are left as 0 as they have to be populated by smartreflex
+ * driver after reading the efuse.
+ */
+static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
+	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
+	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
+	{.volt_nominal = 1350000, .sr_errminlimit = 0xFA, .vp_errgain = 0x27},
+};
+
+static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
+	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
+	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
+};
+
+static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
+	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
+};
 
 /* By default VPFORCEUPDATE is the chosen method of voltage scaling */
 static bool voltscale_vpforceupdate = true;
@@ -489,6 +557,130 @@ static void __init omap3_vdd_data_configure(struct omap_vdd_info *vdd)
 	vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT;
 }
 
+/* OMAP4 specific voltage init functions */
+static void __init omap4_init_voltagecontroller(void)
+{
+	voltage_write_reg(OMAP4_PRM_VC_SMPS_SA_OFFSET,
+			(OMAP4_SRI2C_SLAVE_ADDR <<
+			 OMAP4430_SA_VDD_CORE_L_0_6_SHIFT) |
+			(OMAP4_SRI2C_SLAVE_ADDR <<
+			 OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT) |
+			(OMAP4_SRI2C_SLAVE_ADDR <<
+			 OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT));
+	voltage_write_reg(OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+			(OMAP4_VDD_MPU_SR_VOLT_REG <<
+			 OMAP4430_VOLRA_VDD_MPU_L_SHIFT) |
+			(OMAP4_VDD_IVA_SR_VOLT_REG <<
+			 OMAP4430_VOLRA_VDD_IVA_L_SHIFT) |
+			(OMAP4_VDD_CORE_SR_VOLT_REG <<
+			 OMAP4430_VOLRA_VDD_CORE_L_SHIFT));
+	voltage_write_reg(OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
+			OMAP4430_RAV_VDD_MPU_L_MASK |
+			OMAP4430_CMD_VDD_MPU_L_MASK |
+			OMAP4430_RAV_VDD_IVA_L_MASK |
+			OMAP4430_CMD_VDD_IVA_L_MASK |
+			OMAP4430_RAV_VDD_CORE_L_MASK |
+			OMAP4430_CMD_VDD_CORE_L_MASK);
+
+	voltage_write_reg(OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET,
+			(0x60 << OMAP4430_SCLL_SHIFT |
+			0x26 << OMAP4430_SCLH_SHIFT));
+	/* TODO: Configure setup times and CMD_VAL values*/
+}
+
+/* Sets up all the VDD related info for OMAP4 */
+static void __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
+{
+	struct clk *sys_ck;
+	u32 sys_clk_speed, timeout_val, waittime;
+
+	if (!strcmp(vdd->voltdm.name, "mpu")) {
+		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN;
+		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX;
+		vdd->volt_data = omap44xx_vdd_mpu_volt_data;
+		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_mpu_volt_data);
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
+		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
+		vdd->vdd_sr_reg = OMAP4_VDD_MPU_SR_VOLT_REG;
+	} else if (!strcmp(vdd->voltdm.name, "core")) {
+		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN;
+		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX;
+		vdd->volt_data = omap44xx_vdd_core_volt_data;
+		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_core_volt_data);
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
+		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
+		vdd->vdd_sr_reg = OMAP4_VDD_CORE_SR_VOLT_REG;
+	} else if (!strcmp(vdd->voltdm.name, "iva")) {
+		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN;
+		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX;
+		vdd->volt_data = omap44xx_vdd_iva_volt_data;
+		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_iva_volt_data);
+		vdd->vp_reg.tranxdone_status =
+			OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
+		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
+		vdd->vdd_sr_reg = OMAP4_VDD_IVA_SR_VOLT_REG;
+	} else {
+		pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
+			__func__, vdd->voltdm.name);
+		return;
+	}
+
+	/*
+	 * Sys clk rate is require to calculate vp timeout value and
+	 * smpswaittimemin and smpswaittimemax.
+	 */
+	sys_ck = clk_get(NULL, "sys_clkin_ck");
+	if (IS_ERR(sys_ck)) {
+		pr_warning("%s: Could not get the sys clk to calculate"
+			"various vdd_%s params\n", __func__, vdd->voltdm.name);
+		return;
+	}
+	sys_clk_speed = clk_get_rate(sys_ck);
+	clk_put(sys_ck);
+
+	/* Divide to avoid overflow */
+	sys_clk_speed /= 1000;
+
+	/* Nominal/Reset voltage of the VDD */
+	vdd->nominal_volt = vdd->curr_volt = 1200000;
+
+	/* VPCONFIG bit fields */
+	vdd->vp_reg.vpconfig_erroroffset =
+				(OMAP4_VP_CONFIG_ERROROFFSET <<
+				 OMAP4430_ERROROFFSET_SHIFT);
+	vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
+	vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
+	vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
+	vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
+	vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
+	vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
+	vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
+	vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
+
+	/* VSTEPMIN VSTEPMAX bit fields */
+	waittime = ((volt_pmic_info.step_size / volt_pmic_info.slew_rate) *
+				sys_clk_speed) / 1000;
+	vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+	vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+	vdd->vp_reg.vstepmin_stepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN;
+	vdd->vp_reg.vstepmax_stepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX;
+	vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+		OMAP4430_SMPSWAITTIMEMIN_SHIFT;
+	vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+		OMAP4430_SMPSWAITTIMEMAX_SHIFT;
+	vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
+	vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
+
+	/* VLIMITTO bit fields */
+	timeout_val = (sys_clk_speed * OMAP4_VP_VLIMITTO_TIMEOUT_US) / 1000;
+	vdd->vp_reg.vlimitto_timeout = timeout_val;
+	vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
+	vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
+	vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
+}
+
 /* Generic voltage init functions */
 static void __init init_voltageprocessor(struct omap_vdd_info *vdd)
 {
@@ -526,6 +718,8 @@ static void __init vdd_data_configure(struct omap_vdd_info *vdd)
 {
 	if (cpu_is_omap34xx())
 		omap3_vdd_data_configure(vdd);
+	else if (cpu_is_omap44xx())
+		omap4_vdd_data_configure(vdd);
 }
 
 static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
@@ -587,6 +781,8 @@ static void __init init_voltagecontroller(void)
 {
 	if (cpu_is_omap34xx())
 		omap3_init_voltagecontroller();
+	else if (cpu_is_omap44xx())
+		omap4_init_voltagecontroller();
 }
 
 /* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
@@ -720,6 +916,14 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
 		vc_cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
 		prm_irqst_reg_offs = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
 		ocp_mod = OCP_MOD;
+	} else if (cpu_is_omap44xx()) {
+		vc_cmd_on_shift = OMAP4430_ON_SHIFT;
+		vc_cmd_on_mask = OMAP4430_ON_MASK;
+		if (!strcmp(vdd->voltdm.name, "mpu"))
+			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
+		else
+			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+		ocp_mod = OMAP4430_PRM_OCP_SOCKET_MOD;
 	} else {
 		pr_warning("%s: Voltage scaling not yet enabled for"
 			"this chip\n", __func__);
@@ -1265,12 +1469,15 @@ static int __init omap_voltage_init(void)
 		volt_mod = OMAP3430_GR_MOD;
 		vdd_info = omap3_vdd_info;
 		nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
+	} else if (cpu_is_omap44xx()) {
+		volt_mod = OMAP4430_PRM_DEVICE_MOD;
+		vdd_info = omap4_vdd_info;
+		nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
 	} else {
 		pr_warning("%s: voltage driver support not added\n", __func__);
 		return 0;
 	}
 
-
 	init_voltagecontroller();
 	for (i = 0; i < nr_scalable_vdd; i++) {
 		vdd_data_configure(&vdd_info[i]);
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 41d6f3d..de5b48e 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -27,6 +27,12 @@ extern struct dentry *pm_dbg_main_dir;
 #define OMAP3_VDD1_SR_CONTROL_REG		0x00
 #define OMAP3_VDD2_SR_CONTROL_REG		0x01
 
+/* Voltage SR parameters for OMAP4 */
+#define OMAP4_SRI2C_SLAVE_ADDR			0x12
+#define OMAP4_VDD_MPU_SR_VOLT_REG		0x55
+#define OMAP4_VDD_IVA_SR_VOLT_REG		0x5B
+#define OMAP4_VDD_CORE_SR_VOLT_REG		0x61
+
 /*
  * Omap3 VP register specific values. Maybe these need to come from
  * board file or PMIC data structure
@@ -56,7 +62,19 @@ extern struct dentry *pm_dbg_main_dir;
 #define OMAP3630_VP2_VLIMITTO_VDDMIN		0x18
 #define OMAP3630_VP2_VLIMITTO_VDDMAX		0x30
 
-/* TODO OMAP4 VP register values if the same file is used for OMAP4*/
+/* OMAP4 VP register values */
+#define OMAP4_VP_CONFIG_ERROROFFSET		0x00
+#define	OMAP4_VP_VSTEPMIN_SMPSWAITTIMEMIN	0x3C
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN		0x1
+#define OMAP4_VP_VSTEPMAX_SMPSWAITTIMEMAX	0x3C
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX		0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US		0x200
+#define OMAP4_VP_MPU_VLIMITTO_VDDMIN		0x18
+#define OMAP4_VP_MPU_VLIMITTO_VDDMAX		0x3C
+#define OMAP4_VP_IVA_VLIMITTO_VDDMIN		0x18
+#define OMAP4_VP_IVA_VLIMITTO_VDDMAX		0x3C
+#define OMAP4_VP_CORE_VLIMITTO_VDDMIN		0x18
+#define OMAP4_VP_CORE_VLIMITTO_VDDMAX		0x30
 
 /**
  * voltagedomain - omap voltage domain global structure
-- 
1.7.0.4

[PATCH v2 06/11] OMAP4: PM: Program correct init voltages for scalable VDDs

[Thara Gopinath]

By default the system boots up at nominal voltage for every
voltage domain in the system. This patch puts vdd_mpu, vdd_iva
and vdd_core to the correct boot up voltage as per the opp tables
specified. This patch implements this by matching the rate of
the main clock of the voltage domain with the opp table and
picking up the correct voltage.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9ba2c5f..0e03ea0 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -207,6 +207,10 @@ static int __init omap2_common_pm_init(void)
 		omap3_pm_init_opp_table();
 		omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
 		omap2_set_init_voltage("core", "l3_ick", l3_dev);
+	} else if (cpu_is_omap44xx()) {
+		omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
+		omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
+		omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
 	}
 
 	omap_pm_if_init();
-- 
1.7.0.4

[PATCH v2 07/11] OMAP4: hwmod: Add inital data for smartreflex modules.

[Thara Gopinath]

From: Benoit Cousson <b-cousson@ti.com>

This patch adds the hwmod details for OMAP4 smartreflex modules.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  163 ++++++++++++++++++++++++++++
 1 files changed, 163 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e20b0ee..ba3c215 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -452,6 +452,165 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+	.sidle_shift	= 24,
+	.enwkup_shift	= 26,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+	.sysc_offs	= 0x0038,
+	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+	.name = "smartreflex",
+	.sysc = &omap44xx_smartreflex_sysc,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+	{
+		.pa_start	= 0x4a0dd000,
+		.pa_end		= 0x4a0dd03f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_core_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_core_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_core slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_core,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+	.name		= "smartreflex_core",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+	.main_clk	= "smartreflex_core_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_core_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_iva */
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+	{
+		.pa_start	= 0x4a0db000,
+		.pa_end		= 0x4a0db03f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_iva_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_iva_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_iva,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+	.name		= "smartreflex_iva",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+	.main_clk	= "smartreflex_iva_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_iva_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+	{
+		.pa_start	= 0x4a0d9000,
+		.pa_end		= 0x4a0d903f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_mpu_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_mpu_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_mpu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_mpu,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+	.name		= "smartreflex_mpu",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
+	.main_clk	= "smartreflex_mpu_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_mpu_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	/* dmm class */
 	&omap44xx_dmm_hwmod,
@@ -472,6 +631,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 	/* mpu class */
 	&omap44xx_mpu_hwmod,
+
+	&omap44xx_smartreflex_core_hwmod,
+	&omap44xx_smartreflex_iva_hwmod,
+	&omap44xx_smartreflex_mpu_hwmod,
 	NULL,
 };
 
-- 
1.7.0.4

[PATCH v2 08/11] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Thara Gopinath]

This patch adds dev attributes for smartreflex modules
in the OMAP4 hwmod database. This patch also updates the
smartreflex rev in the smartreflex class data structure
in the OMAP4 hwmod database.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
 2 files changed, 68 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ba3c215..82657b5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,6 +22,8 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
+#include <plat/smartreflex.h>
+#include <plat/control.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
 	.name = "smartreflex",
 	.sysc = &omap44xx_smartreflex_sysc,
+	.rev  = 2,
 };
 
 /* smartreflex_core */
@@ -505,6 +508,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
 	&omap44xx_l4_cfg__smartreflex_core,
 };
 
+static u32 omap44xx_sr_core_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
+};
+
+static u32 omap44xx_sr_core_test_nvalues[] = {
+	0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_core_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_core_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_core_test_nvalues,
+	.vdd_name		= "core"
+};
+
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 	.name		= "smartreflex_core",
 	.class		= &omap44xx_smartreflex_hwmod_class,
@@ -518,6 +537,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 	},
 	.slaves		= omap44xx_smartreflex_core_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+	.dev_attr	= &omap44xx_sr_core_dev_attr,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -550,6 +570,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
 	&omap44xx_l4_cfg__smartreflex_iva,
 };
 
+static u32 omap44xx_sr_iva_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_IVA_OPP50, OMAP44XX_CONTROL_FUSE_IVA_OPP100,
+	OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO,
+};
+
+static u32 omap44xx_sr_iva_test_nvalues[] = {
+	0x0, 0x0, 0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_iva_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_iva_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_iva_test_nvalues,
+	.vdd_name		= "iva"
+};
+
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 	.name		= "smartreflex_iva",
 	.class		= &omap44xx_smartreflex_hwmod_class,
@@ -563,6 +600,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 	},
 	.slaves		= omap44xx_smartreflex_iva_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+	.dev_attr	= &omap44xx_sr_iva_dev_attr,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -595,6 +633,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
 	&omap44xx_l4_cfg__smartreflex_mpu,
 };
 
+static u32 omap44xx_sr_mpu_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_MPU_OPP50, OMAP44XX_CONTROL_FUSE_MPU_OPP100,
+	OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO,
+};
+
+static u32 omap44xx_sr_mpu_test_nvalues[] = {
+	0x0, 0x0, 0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_mpu_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_mpu_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_mpu_test_nvalues,
+	.vdd_name		= "mpu"
+};
+
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 	.name		= "smartreflex_mpu",
 	.class		= &omap44xx_smartreflex_hwmod_class,
@@ -608,6 +663,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 	},
 	.slaves		= omap44xx_smartreflex_mpu_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+	.dev_attr	= &omap44xx_sr_mpu_dev_attr,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 042eb6e..1e8f6ec 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -181,6 +181,18 @@
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
 
+/* 44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
-- 
1.7.0.4

[PATCH v2 09/11] OMAP4: Smartreflex framework extensions

[Thara Gopinath]

This patch extends the smartreflex framework to support
OMAP4. The changes are minor like compiling smartreflex Kconfig
option for OMAP4 also, and a couple of OMAP4 checks in
the smartreflex framework.

The change in sr_device.c where new logic has to be introduced
for reading the efuse registers is due to the fact that in OMAP4
the efuse registers are 24 bit aligned. A __raw_readl will
fail for non-32 bit aligned address and hence the 8-bit read
and shift.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |    8 ++++++--
 arch/arm/mach-omap2/sr_device.c   |   15 +++++++++++++--
 arch/arm/plat-omap/Kconfig        |    2 +-
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index b5a7878..e41be58 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -152,7 +152,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
 	struct clk *sys_ck;
 	u32 sys_clk_speed;
 
-	sys_ck = clk_get(NULL, "sys_ck");
+	if (cpu_is_omap34xx())
+		sys_ck = clk_get(NULL, "sys_ck");
+	else
+		sys_ck = clk_get(NULL, "sys_clkin_ck");
+
 	if (IS_ERR(sys_ck)) {
 		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
 			__func__);
@@ -192,7 +196,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 	 * file or pmic specific data structure. In that case these structure
 	 * fields will have to be populated using the pdata or pmic structure.
 	 */
-	if (cpu_is_omap34xx()) {
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 606da59..ef28d63 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -20,6 +20,7 @@
 
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 
 #include <plat/control.h>
 #include <plat/omap_device.h>
@@ -98,9 +99,19 @@ static void __init sr_set_nvalues(struct omap_sr_dev_data *dev_data,
 				dev_data->senpenable_shift);
 	}
 
-	for (i = 0; i < dev_data->volts_supported; i++)
-		dev_data->volt_data[i].sr_nvalue = omap_ctrl_readl(
+	for (i = 0; i < dev_data->volts_supported; i++) {
+		if (cpu_is_omap44xx()) {
+			u16 offset = dev_data->efuse_nvalues_offs[i];
+
+			dev_data->volt_data[i].sr_nvalue =
+				omap_ctrl_readb(offset) |
+				omap_ctrl_readb(offset + 1) << 8 |
+				omap_ctrl_readb(offset + 2) << 16;
+		} else {
+			dev_data->volt_data[i].sr_nvalue = omap_ctrl_readl(
 				dev_data->efuse_nvalues_offs[i]);
+		}
+	}
 }
 #endif
 
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 89dc30e..67b1395 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -37,7 +37,7 @@ config OMAP_DEBUG_LEDS
 
 config OMAP_SMARTREFLEX
 	bool "SmartReflex support"
-	depends on ARCH_OMAP3 && PM
+	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
 	help
 	  Say Y if you want to enable SmartReflex.
 
-- 
1.7.0.4

[PATCH v2 10/11] OMAP4: Enabling smartrefles class 3 driver.

[Thara Gopinath]

This patch enables smartreflex class3 mode of operation for OMAP4430 SDP board.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 9447644..3395e61 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -36,6 +36,7 @@
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include "hsmmc.h"
+#include "smartreflex-class3.h"
 
 #define ETH_KS8851_IRQ			34
 #define ETH_KS8851_POWER_ON		48
@@ -182,6 +183,7 @@ static void __init omap_4430sdp_init_irq(void)
 #endif
 	gic_init_irq();
 	omap_gpio_init();
+	sr_class3_init();
 }
 
 static struct omap_musb_board_data musb_board_data = {
-- 
1.7.0.4

[PATCH v2 11/11] OMAP4: Add opp tables.

[Thara Gopinath]

This patch adds OPP tables for OMAP4. A new file
opp44xx_data.c has been introduced to keep the OMAP4
opp tables and the registeration of these tables with
the generic opp framework.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/Makefile       |    3 +-
 arch/arm/mach-omap2/opp44xx_data.c |   99 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm.c           |    1 +
 arch/arm/mach-omap2/pm.h           |    1 +
 4 files changed, 103 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/opp44xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b18d171..dce7e3b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -52,7 +52,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o voltage.o \
 					   cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o pm_bus.o \
+					   opp44xx_data.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/opp44xx_data.c b/arch/arm/mach-omap2/opp44xx_data.c
new file mode 100644
index 0000000..90aa4c4
--- /dev/null
+++ b/arch/arm/mach-omap2/opp44xx_data.c
@@ -0,0 +1,99 @@
+/*
+ * OMAP4 OPP table definitions.
+ *
+ * Copyright (C) 2009 - 2010 Texas Instruments Incorporated.
+ *	Nishanth Menon
+ * Copyright (C) 2009 - 2010 Deep Root Systems, LLC.
+ *	Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ * Copyright (C) 2010 Texas Instruments Incorporated.
+ *	Thara Gopinath
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ * History:
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+
+#include <plat/opp.h>
+#include <plat/cpu.h>
+#include <plat/omap_device.h>
+
+static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+	/* MPU OPP1 - OPP50 */
+	OMAP_OPP_DEF("mpu", true, 300000000, 930000),
+	/* MPU OPP2 - OPP100 */
+	OMAP_OPP_DEF("mpu", true, 600000000, 1100000),
+	/* MPU OPP3 - OPP-Turbo */
+	OMAP_OPP_DEF("mpu", true, 800000000, 1260000),
+	/* MPU OPP4 - OPP-SB */
+	OMAP_OPP_DEF("mpu", true, 1008000000, 1350000),
+	/* IVA OPP1 - OPP50 */
+	OMAP_OPP_DEF("iva", true,  133000000, 930000),
+	/* IVA OPP2 - OPP100 */
+	OMAP_OPP_DEF("iva", true,  266000000, 1100000),
+	/* IVA OPP3 - OPP-Turbo */
+	OMAP_OPP_DEF("iva", false, 332000000, 1260000),
+	/* L3 OPP1 - OPP50 */
+	OMAP_OPP_DEF("l3_main_1", true, 100000000, 930000),
+	/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+	OMAP_OPP_DEF("l3_main_1", true, 200000000, 1100000),
+};
+
+static u32 omap44xx_opp_def_size = ARRAY_SIZE(omap44xx_opp_def_list);
+
+/* Temp variable to allow multiple calls */
+static u8 __initdata omap4_table_init;
+
+
+int __init omap4_pm_init_opp_table(void)
+{
+	struct omap_opp_def *opp_def;
+	int i, r;
+
+	/*
+	 * Allow multiple calls, but initialize only if not already initalized
+	 * even if the previous call failed, coz, no reason we'd succeed again
+	 */
+	if (omap4_table_init)
+		return 0;
+
+	omap4_table_init = 1;
+
+	opp_def = omap44xx_opp_def_list;
+
+	for (i = 0; i < omap44xx_opp_def_size; i++) {
+		struct omap_hwmod *oh;
+		struct device *dev;
+
+		if (!opp_def->hwmod_name) {
+			pr_err("%s: missing name of omap_hwmod in opp data\n",
+				__func__);
+			opp_def++;
+			continue;
+		}
+
+		oh = omap_hwmod_lookup(opp_def->hwmod_name);
+		if (!oh || !oh->od) {
+			pr_warn("%s: no hwmod or odev for %s.Cannot add OPP\n",
+				__func__, opp_def->hwmod_name);
+			opp_def++;
+			continue;
+		}
+
+		dev = &oh->od->pdev.dev;
+		r = opp_add(dev, opp_def++);
+		if (r)
+			pr_err("unable to add OPP %ld Hz for %s\n",
+				opp_def->freq, opp_def->hwmod_name);
+	}
+	return 0;
+}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 0e03ea0..ba5d8b2 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -208,6 +208,7 @@ static int __init omap2_common_pm_init(void)
 		omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
 		omap2_set_init_voltage("core", "l3_ick", l3_dev);
 	} else if (cpu_is_omap44xx()) {
+		omap4_pm_init_opp_table();
 		omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
 		omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
 		omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index c06cedd..54d18b5 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -23,6 +23,7 @@ extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 extern int omap3_pm_init_opp_table(void);
+extern int omap4_pm_init_opp_table(void);
 
 struct cpuidle_params {
 	u8  valid;
-- 
1.7.0.4

RE: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula

[Lesly Arackal Manuel]

Hi Thara,


> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Thara Gopinath
> Sent: Saturday, September 25, 2010 6:21 PM
> To: linux-omap@vger.kernel.org
> Cc: khilman@deeprootsystems.com; paul@pwsan.com; b-cousson@ti.com;
> vishwanath.bs@ti.com; sawant@ti.com; Thara Gopinath
> Subject: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation
> formula
> 
> TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs,
> blaze boards and panda boards has a different formula
> from that of TWL4030 for voltage to vsel and
> vsel to voltage calculation. This patch implements the new
> formula depending on the PMIC type.
> 
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/plat-omap/opp_twl_tps.c |   71
> ++++++++++++++++++++++++++++++++++++++
>  1 files changed, 71 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/opp_twl_tps.c b/arch/arm/plat-
> omap/opp_twl_tps.c
> index 4448fc5..358b67b 100644
> --- a/arch/arm/plat-omap/opp_twl_tps.c
> +++ b/arch/arm/plat-omap/opp_twl_tps.c
> @@ -15,9 +15,16 @@
> 
>  #include <linux/module.h>
> 
> +#include <linux/i2c/twl.h>
> +
>  #include <plat/opp_twl_tps.h>
>  #include <plat/voltage.h>
> 
> +static bool is_offset_valid;
> +static u8 smps_offset;
> +
> +#define REG_SMPS_OFFSET         0xE0
> +
>  /**
>   * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
>   * @vsel: TWL/TPS VSEL value to convert
> @@ -27,6 +34,38 @@
>   */
>  unsigned long omap_twl_vsel_to_uv(const u8 vsel)
>  {
> +	if (twl_class_is_6030()) {
> +		/*
> +		 * In TWL6030 depending on the value of SMPS_OFFSET
> +		 * efuse register the voltage range supported in
> +		 * standard mode can be either between 0.6V - 1.3V or
> +		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
> +		 * is programmed to all 0's where as starting from
> +		 * TWL6030 ES1.1 the efuse is programmed to 1
> +		 */
> +		if (!is_offset_valid) {
> +			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
0xE0);
> +			is_offset_valid = true;
> +		}

Is it necessary to do the i2c read each time to check the smps_offset?
OR it can be done one time initially. 

> +
> +		if (smps_offset & 0x8) {
> +			return ((((vsel - 1) * 125) + 7000)) * 100;
> +		} else {
> +			/*
> +			 * In case of the supported voltage range being
> +			 * between 0.6V - 1.3V, there is not specific
> +			 * formula for voltage to vsel conversion above
> +			 * 1.3V. There are special hardcoded values for
> +			 * voltages above 1.3V. Currently we are hardcodig
> +			 * only for 1.35 V which is used for 1GH OPP for
> +			 * OMAP4430.
> +			 */
> +			if (vsel == 0x3A)
> +				return 1350000;
> +			return ((((vsel - 1) * 125) + 6000)) * 100;
> +		}
> +	}
> +
>  	return (((vsel * 125) + 6000)) * 100;
>  }
> 
> @@ -40,6 +79,38 @@ unsigned long omap_twl_vsel_to_uv(const u8 vsel)
>  u8 omap_twl_uv_to_vsel(unsigned long uv)
>  {
>  	/* Round up to higher voltage */
> +	if (twl_class_is_6030()) {
> +		/*
> +		 * In TWL6030 depending on the value of SMPS_OFFSET
> +		 * efuse register the voltage range supported in
> +		 * standard mode can be either between 0.6V - 1.3V or
> +		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
> +		 * is programmed to all 0's where as starting from
> +		 * TWL6030 ES1.1 the efuse is programmed to 1
> +		 */
> +		if (!is_offset_valid) {
> +			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
0xE0);
> +			is_offset_valid = true;
> +		}

Prev. comment +
And this will be called each time when we do voltage scaling.

- Lesly

> +
> +		if (smps_offset & 0x8) {
> +			return DIV_ROUND_UP(uv - 700000, 12500) + 1;
> +		} else {
> +			/*
> +			 * In case of the supported voltage range being
> +			 * between 0.6V - 1.3V, there is not specific
> +			 * formula for voltage to vsel conversion above
> +			 * 1.3V. There are special hardcoded values for
> +			 * voltages above 1.3V. Currently we are hardcodig
> +			 * only for 1.35 V which is used for 1GH OPP for
> +			 * OMAP4430.
> +			 */
> +			if (uv == 1350000)
> +				return 0x3A;
> +			return DIV_ROUND_UP(uv - 600000, 12500) + 1;
> +		}
> +	}
> +
>  	return DIV_ROUND_UP(uv - 600000, 12500);
>  }
> 
> --
> 1.7.0.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula

[Gopinath, Thara]

>>-----Original Message-----
>>From: Manuel, Lesly Arackal
>>Sent: Monday, September 27, 2010 9:44 AM
>>To: Gopinath, Thara; linux-omap@vger.kernel.org
>>Cc: khilman@deeprootsystems.com; paul@pwsan.com; Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand
>>Subject: RE: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula
>>
>>Hi Thara,
>>
>>
>>> -----Original Message-----
>>> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
>>> owner@vger.kernel.org] On Behalf Of Thara Gopinath
>>> Sent: Saturday, September 25, 2010 6:21 PM
>>> To: linux-omap@vger.kernel.org
>>> Cc: khilman@deeprootsystems.com; paul@pwsan.com; b-cousson@ti.com;
>>> vishwanath.bs@ti.com; sawant@ti.com; Thara Gopinath
>>> Subject: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation
>>> formula
>>>
>>> TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs,
>>> blaze boards and panda boards has a different formula
>>> from that of TWL4030 for voltage to vsel and
>>> vsel to voltage calculation. This patch implements the new
>>> formula depending on the PMIC type.
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>> ---
>>>  arch/arm/plat-omap/opp_twl_tps.c |   71
>>> ++++++++++++++++++++++++++++++++++++++
>>>  1 files changed, 71 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/plat-omap/opp_twl_tps.c b/arch/arm/plat-
>>> omap/opp_twl_tps.c
>>> index 4448fc5..358b67b 100644
>>> --- a/arch/arm/plat-omap/opp_twl_tps.c
>>> +++ b/arch/arm/plat-omap/opp_twl_tps.c
>>> @@ -15,9 +15,16 @@
>>>
>>>  #include <linux/module.h>
>>>
>>> +#include <linux/i2c/twl.h>
>>> +
>>>  #include <plat/opp_twl_tps.h>
>>>  #include <plat/voltage.h>
>>>
>>> +static bool is_offset_valid;
>>> +static u8 smps_offset;
>>> +
>>> +#define REG_SMPS_OFFSET         0xE0
>>> +
>>>  /**
>>>   * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
>>>   * @vsel: TWL/TPS VSEL value to convert
>>> @@ -27,6 +34,38 @@
>>>   */
>>>  unsigned long omap_twl_vsel_to_uv(const u8 vsel)
>>>  {
>>> +	if (twl_class_is_6030()) {
>>> +		/*
>>> +		 * In TWL6030 depending on the value of SMPS_OFFSET
>>> +		 * efuse register the voltage range supported in
>>> +		 * standard mode can be either between 0.6V - 1.3V or
>>> +		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
>>> +		 * is programmed to all 0's where as starting from
>>> +		 * TWL6030 ES1.1 the efuse is programmed to 1
>>> +		 */
>>> +		if (!is_offset_valid) {
>>> +			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
>>0xE0);
>>> +			is_offset_valid = true;
>>> +		}
>>
>>Is it necessary to do the i2c read each time to check the smps_offset?
>>OR it can be done one time initially.
Hello Lesly,

It is not done every time. It is only done the first time omap_twl_vsel_to_uv
or omap_twl_uv_to_vsel is called. If is_offset_valid, we do not read the register
via i2c interface.

Regards
Thara

Re: [PATCH v2 04/11] OMAP4: Extend clock data.

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> This patch extends the OMAP4 clock data to include
> various x2 clockc nodes as the clock framework
> skips a *2 whie calculating the dpll locked frequency.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>

Acked-by: Kevin Hilman <khilman@deeprootsystems.com>

Please post this as a separate patch, and Paul can queue for 2.6.37.

Thanks,

Kevin

> ---
>  arch/arm/mach-omap2/clock44xx_data.c |   40 +++++++++++++++++++++++++++------
>  1 files changed, 32 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index edf2c28..3652fda 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -481,14 +481,21 @@ static struct clk dpll_core_m5_ck = {
>  	.set_rate	= &omap2_clksel_set_rate,
>  };
>  
> +static struct clk dpll_core_m5x2_ck = {
> +	.name		= "dpll_core_m5x2_ck",
> +	.parent		= &dpll_core_m5_ck,
> +	.ops		= &clkops_null,
> +	.recalc		= &omap3_clkoutx2_recalc,
> +};
> +
>  static const struct clksel div_core_div[] = {
> -	{ .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
> +	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
>  	{ .parent = NULL },
>  };
>  
>  static struct clk div_core_ck = {
>  	.name		= "div_core_ck",
> -	.parent		= &dpll_core_m5_ck,
> +	.parent		= &dpll_core_m5x2_ck,
>  	.clksel		= div_core_div,
>  	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
>  	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,
> @@ -507,13 +514,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
>  };
>  
>  static const struct clksel div_iva_hs_clk_div[] = {
> -	{ .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
> +	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
>  	{ .parent = NULL },
>  };
>  
>  static struct clk div_iva_hs_clk = {
>  	.name		= "div_iva_hs_clk",
> -	.parent		= &dpll_core_m5_ck,
> +	.parent		= &dpll_core_m5x2_ck,
>  	.clksel		= div_iva_hs_clk_div,
>  	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
>  	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
> @@ -525,7 +532,7 @@ static struct clk div_iva_hs_clk = {
>  
>  static struct clk div_mpu_hs_clk = {
>  	.name		= "div_mpu_hs_clk",
> -	.parent		= &dpll_core_m5_ck,
> +	.parent		= &dpll_core_m5x2_ck,
>  	.clksel		= div_iva_hs_clk_div,
>  	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
>  	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
> @@ -651,6 +658,13 @@ static struct clk dpll_iva_m4_ck = {
>  	.set_rate	= &omap2_clksel_set_rate,
>  };
>  
> +static struct clk dpll_iva_m4x2_ck = {
> +	.name		= "dpll_iva_m4x2_ck",
> +	.parent		= &dpll_iva_m4_ck,
> +	.ops		= &clkops_null,
> +	.recalc		= &omap3_clkoutx2_recalc,
> +};
> +
>  static struct clk dpll_iva_m5_ck = {
>  	.name		= "dpll_iva_m5_ck",
>  	.parent		= &dpll_iva_ck,
> @@ -663,6 +677,13 @@ static struct clk dpll_iva_m5_ck = {
>  	.set_rate	= &omap2_clksel_set_rate,
>  };
>  
> +static struct clk dpll_iva_m5x2_ck = {
> +	.name		= "dpll_iva_m5x2_ck",
> +	.parent		= &dpll_iva_m5_ck,
> +	.ops		= &clkops_null,
> +	.recalc		= &omap3_clkoutx2_recalc,
> +};
> +
>  /* DPLL_MPU */
>  static struct dpll_data dpll_mpu_dd = {
>  	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
> @@ -1350,7 +1371,7 @@ static struct clk dsp_fck = {
>  	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
>  	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
>  	.clkdm_name	= "tesla_clkdm",
> -	.parent		= &dpll_iva_m4_ck,
> +	.parent		= &dpll_iva_m4x2_ck,
>  	.recalc		= &followparent_recalc,
>  };
>  
> @@ -1725,7 +1746,7 @@ static struct clk iva_fck = {
>  	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
>  	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
>  	.clkdm_name	= "ivahd_clkdm",
> -	.parent		= &dpll_iva_m5_ck,
> +	.parent		= &dpll_iva_m5x2_ck,
>  	.recalc		= &followparent_recalc,
>  };
>  
> @@ -2089,7 +2110,7 @@ static struct clk sl2if_ick = {
>  	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
>  	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
>  	.clkdm_name	= "ivahd_clkdm",
> -	.parent		= &dpll_iva_m5_ck,
> +	.parent		= &dpll_iva_m5x2_ck,
>  	.recalc		= &followparent_recalc,
>  };
>  
> @@ -2782,6 +2803,7 @@ static struct omap_clk omap44xx_clks[] = {
>  	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck,	CK_443X),
>  	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck,	CK_443X),
>  	CLK(NULL,	"dpll_core_m5_ck",		&dpll_core_m5_ck,	CK_443X),
> +	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck,	CK_443X),
>  	CLK(NULL,	"div_core_ck",			&div_core_ck,	CK_443X),
>  	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk,	CK_443X),
>  	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk,	CK_443X),
> @@ -2793,7 +2815,9 @@ static struct omap_clk omap44xx_clks[] = {
>  	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck,	CK_443X),
>  	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck,	CK_443X),
>  	CLK(NULL,	"dpll_iva_m4_ck",		&dpll_iva_m4_ck,	CK_443X),
> +	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck,	CK_443X),
>  	CLK(NULL,	"dpll_iva_m5_ck",		&dpll_iva_m5_ck,	CK_443X),
> +	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck,	CK_443X),
>  	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck,	CK_443X),
>  	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck,	CK_443X),
>  	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck,	CK_443X),

RE: [PATCH v2 04/11] OMAP4: Extend clock data.

[Gopinath, Thara]

>>-----Original Message-----
>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>Sent: Wednesday, September 29, 2010 4:39 AM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; Cousson, Benoit; Sripathy,
>>Vishwanath; Sawant, Anand
>>Subject: Re: [PATCH v2 04/11] OMAP4: Extend clock data.
>>
>>Thara Gopinath <thara@ti.com> writes:
>>
>>> This patch extends the OMAP4 clock data to include
>>> various x2 clockc nodes as the clock framework
>>> skips a *2 whie calculating the dpll locked frequency.
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>
>>Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
>>
>>Please post this as a separate patch, and Paul can queue for 2.6.37.

Ok I will post this as a separate patch. 

Regards
Thara
>>
>>Thanks,
>>
>>Kevin
>>
>>> ---
>>>  arch/arm/mach-omap2/clock44xx_data.c |   40 +++++++++++++++++++++++++++---
>>---
>>>  1 files changed, 32 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-
>>omap2/clock44xx_data.c
>>> index edf2c28..3652fda 100644
>>> --- a/arch/arm/mach-omap2/clock44xx_data.c
>>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
>>> @@ -481,14 +481,21 @@ static struct clk dpll_core_m5_ck = {
>>>  	.set_rate	= &omap2_clksel_set_rate,
>>>  };
>>>
>>> +static struct clk dpll_core_m5x2_ck = {
>>> +	.name		= "dpll_core_m5x2_ck",
>>> +	.parent		= &dpll_core_m5_ck,
>>> +	.ops		= &clkops_null,
>>> +	.recalc		= &omap3_clkoutx2_recalc,
>>> +};
>>> +
>>>  static const struct clksel div_core_div[] = {
>>> -	{ .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
>>> +	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
>>>  	{ .parent = NULL },
>>>  };
>>>
>>>  static struct clk div_core_ck = {
>>>  	.name		= "div_core_ck",
>>> -	.parent		= &dpll_core_m5_ck,
>>> +	.parent		= &dpll_core_m5x2_ck,
>>>  	.clksel		= div_core_div,
>>>  	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
>>>  	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,
>>> @@ -507,13 +514,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
>>>  };
>>>
>>>  static const struct clksel div_iva_hs_clk_div[] = {
>>> -	{ .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
>>> +	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
>>>  	{ .parent = NULL },
>>>  };
>>>
>>>  static struct clk div_iva_hs_clk = {
>>>  	.name		= "div_iva_hs_clk",
>>> -	.parent		= &dpll_core_m5_ck,
>>> +	.parent		= &dpll_core_m5x2_ck,
>>>  	.clksel		= div_iva_hs_clk_div,
>>>  	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
>>>  	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
>>> @@ -525,7 +532,7 @@ static struct clk div_iva_hs_clk = {
>>>
>>>  static struct clk div_mpu_hs_clk = {
>>>  	.name		= "div_mpu_hs_clk",
>>> -	.parent		= &dpll_core_m5_ck,
>>> +	.parent		= &dpll_core_m5x2_ck,
>>>  	.clksel		= div_iva_hs_clk_div,
>>>  	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
>>>  	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
>>> @@ -651,6 +658,13 @@ static struct clk dpll_iva_m4_ck = {
>>>  	.set_rate	= &omap2_clksel_set_rate,
>>>  };
>>>
>>> +static struct clk dpll_iva_m4x2_ck = {
>>> +	.name		= "dpll_iva_m4x2_ck",
>>> +	.parent		= &dpll_iva_m4_ck,
>>> +	.ops		= &clkops_null,
>>> +	.recalc		= &omap3_clkoutx2_recalc,
>>> +};
>>> +
>>>  static struct clk dpll_iva_m5_ck = {
>>>  	.name		= "dpll_iva_m5_ck",
>>>  	.parent		= &dpll_iva_ck,
>>> @@ -663,6 +677,13 @@ static struct clk dpll_iva_m5_ck = {
>>>  	.set_rate	= &omap2_clksel_set_rate,
>>>  };
>>>
>>> +static struct clk dpll_iva_m5x2_ck = {
>>> +	.name		= "dpll_iva_m5x2_ck",
>>> +	.parent		= &dpll_iva_m5_ck,
>>> +	.ops		= &clkops_null,
>>> +	.recalc		= &omap3_clkoutx2_recalc,
>>> +};
>>> +
>>>  /* DPLL_MPU */
>>>  static struct dpll_data dpll_mpu_dd = {
>>>  	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
>>> @@ -1350,7 +1371,7 @@ static struct clk dsp_fck = {
>>>  	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
>>>  	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
>>>  	.clkdm_name	= "tesla_clkdm",
>>> -	.parent		= &dpll_iva_m4_ck,
>>> +	.parent		= &dpll_iva_m4x2_ck,
>>>  	.recalc		= &followparent_recalc,
>>>  };
>>>
>>> @@ -1725,7 +1746,7 @@ static struct clk iva_fck = {
>>>  	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
>>>  	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
>>>  	.clkdm_name	= "ivahd_clkdm",
>>> -	.parent		= &dpll_iva_m5_ck,
>>> +	.parent		= &dpll_iva_m5x2_ck,
>>>  	.recalc		= &followparent_recalc,
>>>  };
>>>
>>> @@ -2089,7 +2110,7 @@ static struct clk sl2if_ick = {
>>>  	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
>>>  	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
>>>  	.clkdm_name	= "ivahd_clkdm",
>>> -	.parent		= &dpll_iva_m5_ck,
>>> +	.parent		= &dpll_iva_m5x2_ck,
>>>  	.recalc		= &followparent_recalc,
>>>  };
>>>
>>> @@ -2782,6 +2803,7 @@ static struct omap_clk omap44xx_clks[] = {
>>>  	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck,	CK_443X),
>>>  	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck,	CK_443X),
>>>  	CLK(NULL,	"dpll_core_m5_ck",		&dpll_core_m5_ck,	CK_443X),
>>> +	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck,
>>	CK_443X),
>>>  	CLK(NULL,	"div_core_ck",			&div_core_ck,	CK_443X),
>>>  	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk,	CK_443X),
>>>  	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk,	CK_443X),
>>> @@ -2793,7 +2815,9 @@ static struct omap_clk omap44xx_clks[] = {
>>>  	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck,
>>	CK_443X),
>>>  	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck,	CK_443X),
>>>  	CLK(NULL,	"dpll_iva_m4_ck",		&dpll_iva_m4_ck,	CK_443X),
>>> +	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck,
>>	CK_443X),
>>>  	CLK(NULL,	"dpll_iva_m5_ck",		&dpll_iva_m5_ck,	CK_443X),
>>> +	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck,
>>	CK_443X),
>>>  	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck,	CK_443X),
>>>  	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck,	CK_443X),
>>>  	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck,
>>	CK_443X),

Re: [PATCH v2 08/11] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Kevin Hilman]

On Sat, 2010-09-25 at 18:21 +0530, Thara Gopinath wrote:
> diff --git a/arch/arm/plat-omap/include/plat/control.h
> b/arch/arm/plat-omap/include/plat/control.h
> index 042eb6e..1e8f6ec 100644
> --- a/arch/arm/plat-omap/include/plat/control.h
> +++ b/arch/arm/plat-omap/include/plat/control.h
> @@ -181,6 +181,18 @@
>  #define OMAP3630_CONTROL_FUSE_OPP50_VDD2
> (OMAP2_CONTROL_GENERAL + 0x0128)
>  #define OMAP3630_CONTROL_FUSE_OPP100_VDD2
> (OMAP2_CONTROL_GENERAL + 0x012C)
>  
> +/* 44xx control efuse offsets */
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP50                0x22C
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP100       0x22F
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO     0x232
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO     0x235
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP50                0x240
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP100       0x243
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO     0x246
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO     0x249
> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP50       0x254
> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP100      0x257
> +

These names are not consistent with the TRM (ES2.x NDA TRM vL).  e.g.
rather than MPU_OPP50, OPP1, the TRM has MPU_0, MPU_1.  However, the 
TRM is confusing here too since the register names are MPU_0,
MPU_1, etc. but the field names in the register descriptions use   
OPP50, OPP100, etc.  What a mess.  We need a consistent naming for these.

Benoit?

Also, based on the TRM, the offsets here don't look quite right.  
e.g. there is no MPU OPP at 0x240, so the OMAP4 the code reading these is 
using reserved/undocumented bits for the first OPP.

Also, the single byte offsets here could use a better explanation, not
necessarily here but in the omap4 code that reads the nvalues.  I expected that these
would be single byte aligned to compact the address space and remove some unused
space, but no, they seem to be arbitrarily shifted around.  

Kevin

Re: [PATCH v2 08/11] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Cousson, Benoit]

Hi Kevin,

Sorry for that late reply, I missed that email a little bit.

On 10/14/2010 8:56 PM, Kevin Hilman wrote:
> On Sat, 2010-09-25 at 18:21 +0530, Thara Gopinath wrote:
>> diff --git a/arch/arm/plat-omap/include/plat/control.h
>> b/arch/arm/plat-omap/include/plat/control.h
>> index 042eb6e..1e8f6ec 100644
>> --- a/arch/arm/plat-omap/include/plat/control.h
>> +++ b/arch/arm/plat-omap/include/plat/control.h
>> @@ -181,6 +181,18 @@
>>   #define OMAP3630_CONTROL_FUSE_OPP50_VDD2
>> (OMAP2_CONTROL_GENERAL + 0x0128)
>>   #define OMAP3630_CONTROL_FUSE_OPP100_VDD2
>> (OMAP2_CONTROL_GENERAL + 0x012C)
>>
>> +/* 44xx control efuse offsets */
>> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP50                0x22C
>> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP100       0x22F
>> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO     0x232
>> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO     0x235
>> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP50                0x240
>> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP100       0x243
>> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO     0x246
>> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO     0x249
>> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP50       0x254
>> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP100      0x257
>> +
>
> These names are not consistent with the TRM (ES2.x NDA TRM vL).  e.g.
> rather than MPU_OPP50, OPP1, the TRM has MPU_0, MPU_1.  However, the
> TRM is confusing here too since the register names are MPU_0,
> MPU_1, etc. but the field names in the register descriptions use
> OPP50, OPP100, etc.  What a mess.  We need a consistent naming for these.
>
> Benoit?

It is indeed a mess... these names are the latest ones used in the HW 
spec. But we are still wondering how to name that in the future.
OPP_LOW, OPP_MID, OPP_HIGH, OPP_TURBO and OPP_NITRO are now considered 
but I'm not sure it is really better.

Honestly I do prefer the OPP50, OPP100, OPP130, OPP166 that are 
providing the percentage wrt nominal frequency and that can scale 
easily. If we do introduce a OPP between OPP_MID and OPP_HIGH, I'm not 
sure anybody will be able to find a proper name whereas OPP_80 is 
straightforward.

In anycase, that will never match the HW spec or the TRM :-(

Benoit

>
> Also, based on the TRM, the offsets here don't look quite right.
> e.g. there is no MPU OPP at 0x240, so the OMAP4 the code reading these is
> using reserved/undocumented bits for the first OPP.
>
> Also, the single byte offsets here could use a better explanation, not
> necessarily here but in the omap4 code that reads the nvalues.  I expected that these
> would be single byte aligned to compact the address space and remove some unused
> space, but no, they seem to be arbitrarily shifted around.
>
> Kevin
>
>

Re: [PATCH v2 08/11] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Cousson, Benoit]

On 9/25/2010 2:51 PM, Gopinath, Thara wrote:
> This patch adds dev attributes for smartreflex modules
> in the OMAP4 hwmod database. This patch also updates the
> smartreflex rev in the smartreflex class data structure
> in the OMAP4 hwmod database.
>
> Signed-off-by: Thara Gopinath<thara@ti.com>
> ---
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
>   arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
>   2 files changed, 68 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index ba3c215..82657b5 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -22,6 +22,8 @@
>
>   #include<plat/omap_hwmod.h>
>   #include<plat/cpu.h>
> +#include<plat/smartreflex.h>
> +#include<plat/control.h>
>
>   #include "omap_hwmod_common_data.h"
>
> @@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
>   static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
>   	.name = "smartreflex",
>   	.sysc =&omap44xx_smartreflex_sysc,
> +	.rev  = 2,
>   };
>
>   /* smartreflex_core */
> @@ -505,6 +508,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
>   	&omap44xx_l4_cfg__smartreflex_core,
>   };
>
> +static u32 omap44xx_sr_core_efuse_offs[] = {
> +	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
> +};
> +
> +static u32 omap44xx_sr_core_test_nvalues[] = {
> +	0x0, 0x0
> +};

At first, I thought it was a good idea to put such data here, but now 
after the discussion about timer hwmod data, I realize I was wrong.

These informations belong to omap_volt_data. For each OPP you should 
provide the efuse offset an the SW nvalues.
BTW, you should not call them test Nvalues, these are perfectly valid 
and can be potentially used in production. There are just not as 
optimized as a efuse Nvalue.

Benoit


> +
> +static struct omap_sr_dev_data omap44xx_sr_core_dev_attr = {
> +	.efuse_nvalues_offs	= omap44xx_sr_core_efuse_offs,
> +	.test_sennenable	= 0x1,
> +	.test_senpenable	= 0x1,
> +	.test_nvalues		= omap44xx_sr_core_test_nvalues,
> +	.vdd_name		= "core"
> +};
> +
>   static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
>   	.name		= "smartreflex_core",
>   	.class		=&omap44xx_smartreflex_hwmod_class,
> @@ -518,6 +537,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
>   	},
>   	.slaves		= omap44xx_smartreflex_core_slaves,
>   	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
> +	.dev_attr	=&omap44xx_sr_core_dev_attr,
>   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
>   };
>
> @@ -550,6 +570,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
>   	&omap44xx_l4_cfg__smartreflex_iva,
>   };
>
> +static u32 omap44xx_sr_iva_efuse_offs[] = {
> +	OMAP44XX_CONTROL_FUSE_IVA_OPP50, OMAP44XX_CONTROL_FUSE_IVA_OPP100,
> +	OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO,
> +};
> +
> +static u32 omap44xx_sr_iva_test_nvalues[] = {
> +	0x0, 0x0, 0x0, 0x0
> +};
> +
> +static struct omap_sr_dev_data omap44xx_sr_iva_dev_attr = {
> +	.efuse_nvalues_offs	= omap44xx_sr_iva_efuse_offs,
> +	.test_sennenable	= 0x1,
> +	.test_senpenable	= 0x1,
> +	.test_nvalues		= omap44xx_sr_iva_test_nvalues,
> +	.vdd_name		= "iva"
> +};
> +
>   static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
>   	.name		= "smartreflex_iva",
>   	.class		=&omap44xx_smartreflex_hwmod_class,
> @@ -563,6 +600,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
>   	},
>   	.slaves		= omap44xx_smartreflex_iva_slaves,
>   	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
> +	.dev_attr	=&omap44xx_sr_iva_dev_attr,
>   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
>   };
>
> @@ -595,6 +633,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
>   	&omap44xx_l4_cfg__smartreflex_mpu,
>   };
>
> +static u32 omap44xx_sr_mpu_efuse_offs[] = {
> +	OMAP44XX_CONTROL_FUSE_MPU_OPP50, OMAP44XX_CONTROL_FUSE_MPU_OPP100,
> +	OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO,
> +};
> +
> +static u32 omap44xx_sr_mpu_test_nvalues[] = {
> +	0x0, 0x0, 0x0, 0x0
> +};
> +
> +static struct omap_sr_dev_data omap44xx_sr_mpu_dev_attr = {
> +	.efuse_nvalues_offs	= omap44xx_sr_mpu_efuse_offs,
> +	.test_sennenable	= 0x1,
> +	.test_senpenable	= 0x1,
> +	.test_nvalues		= omap44xx_sr_mpu_test_nvalues,
> +	.vdd_name		= "mpu"
> +};
> +
>   static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
>   	.name		= "smartreflex_mpu",
>   	.class		=&omap44xx_smartreflex_hwmod_class,
> @@ -608,6 +663,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
>   	},
>   	.slaves		= omap44xx_smartreflex_mpu_slaves,
>   	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
> +	.dev_attr	=&omap44xx_sr_mpu_dev_attr,
>   	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
>   };
>
> diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
> index 042eb6e..1e8f6ec 100644
> --- a/arch/arm/plat-omap/include/plat/control.h
> +++ b/arch/arm/plat-omap/include/plat/control.h
> @@ -181,6 +181,18 @@
>   #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
>   #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
>
> +/* 44xx control efuse offsets */
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
> +#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
> +#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
> +#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
> +
>   /* AM35XX only CONTROL_GENERAL register offsets */
>   #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
>   #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)

Re: [PATCH v2 08/11] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Kevin Hilman]

"Cousson, Benoit" <b-cousson@ti.com> writes:

> On 9/25/2010 2:51 PM, Gopinath, Thara wrote:
>> This patch adds dev attributes for smartreflex modules
>> in the OMAP4 hwmod database. This patch also updates the
>> smartreflex rev in the smartreflex class data structure
>> in the OMAP4 hwmod database.
>>
>> Signed-off-by: Thara Gopinath<thara@ti.com>
>> ---
>>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
>>   arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
>>   2 files changed, 68 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> index ba3c215..82657b5 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> @@ -22,6 +22,8 @@
>>
>>   #include<plat/omap_hwmod.h>
>>   #include<plat/cpu.h>
>> +#include<plat/smartreflex.h>
>> +#include<plat/control.h>
>>
>>   #include "omap_hwmod_common_data.h"
>>
>> @@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
>>   static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
>>   	.name = "smartreflex",
>>   	.sysc =&omap44xx_smartreflex_sysc,
>> +	.rev  = 2,
>>   };
>>
>>   /* smartreflex_core */
>> @@ -505,6 +508,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
>>   	&omap44xx_l4_cfg__smartreflex_core,
>>   };
>>
>> +static u32 omap44xx_sr_core_efuse_offs[] = {
>> +	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
>> +};
>> +
>> +static u32 omap44xx_sr_core_test_nvalues[] = {
>> +	0x0, 0x0
>> +};
>
> At first, I thought it was a good idea to put such data here, but now
> after the discussion about timer hwmod data, I realize I was wrong.
>
> These informations belong to omap_volt_data. For each OPP you should
> provide the efuse offset an the SW nvalues.
> BTW, you should not call them test Nvalues, these are perfectly valid
> and can be potentially used in production. There are just not as
> optimized as a efuse Nvalue.

Just to clarify... 

Benoit, what's your opinion of my comment that these values don't belong
in the volt_data.

As they are only used in the SR layer, they should remain there, IMO.
The only thing needed in volt_data is an efuse id/offset.

Kevin

Re: [PATCH v2 08/11] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Cousson, Benoit]

Hi Kevin,

On 11/2/2010 10:10 AM, Kevin Hilman wrote:
> "Cousson, Benoit"<b-cousson@ti.com>  writes:
>
>> On 9/25/2010 2:51 PM, Gopinath, Thara wrote:
>>> This patch adds dev attributes for smartreflex modules
>>> in the OMAP4 hwmod database. This patch also updates the
>>> smartreflex rev in the smartreflex class data structure
>>> in the OMAP4 hwmod database.
>>>
>>> Signed-off-by: Thara Gopinath<thara@ti.com>
>>> ---
>>>    arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
>>>    arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
>>>    2 files changed, 68 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>> index ba3c215..82657b5 100644
>>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>> @@ -22,6 +22,8 @@
>>>
>>>    #include<plat/omap_hwmod.h>
>>>    #include<plat/cpu.h>
>>> +#include<plat/smartreflex.h>
>>> +#include<plat/control.h>
>>>
>>>    #include "omap_hwmod_common_data.h"
>>>
>>> @@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
>>>    static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
>>>    	.name = "smartreflex",
>>>    	.sysc =&omap44xx_smartreflex_sysc,
>>> +	.rev  = 2,
>>>    };
>>>
>>>    /* smartreflex_core */
>>> @@ -505,6 +508,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
>>>    	&omap44xx_l4_cfg__smartreflex_core,
>>>    };
>>>
>>> +static u32 omap44xx_sr_core_efuse_offs[] = {
>>> +	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
>>> +};
>>> +
>>> +static u32 omap44xx_sr_core_test_nvalues[] = {
>>> +	0x0, 0x0
>>> +};
>>
>> At first, I thought it was a good idea to put such data here, but now
>> after the discussion about timer hwmod data, I realize I was wrong.
>>
>> These informations belong to omap_volt_data. For each OPP you should
>> provide the efuse offset an the SW nvalues.
>> BTW, you should not call them test Nvalues, these are perfectly valid
>> and can be potentially used in production. There are just not as
>> optimized as a efuse Nvalue.
>
> Just to clarify...
>
> Benoit, what's your opinion of my comment that these values don't belong
> in the volt_data.

Or maybe it is just volt_data that should be renamed, because all the 
data in it are SR / VP related:

{.volt_nominal = 975000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},

So the efuse info belongs to it as well.

At the end the volt_data at voltage management level is just a list of 
supported voltages. Does it make sense to add an id instead of keeping 
the voltage as an index?

volt_data should be:
{.volt_nominal = 975000},

and then volt_sr_vp_data will be:
{.volt_nominal = 975000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C, 
efuse_stuff...},

or with an id:
{.id = 0, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C, efuse_stuff...},

I do agree that we have to split that in two structures, but I'm not 
sure the id is really needed here?

Regards,
Benoit