* [PATCH v4 1/7] OMAP: DSS2: Add dss_features for omap4 and overlay manager related features
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
2010-11-08 12:24 ` [PATCH v4 2/7] OMAP: DSS2: Represent DISPC register defines with channel as parameter Archit Taneja
` (5 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Add support for LCD2 manager through introducing a new has_feature,
Initialize a dss_features struct for omap4.
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dss_features.c | 43 ++++++++++++++++++++++++++++++-
drivers/video/omap2/dss/dss_features.h | 7 ++++-
2 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 854deba..8ab54ab 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -82,6 +82,18 @@ static const enum omap_display_type omap3_dss_supported_displays[] = {
OMAP_DISPLAY_TYPE_VENC,
};
+static const enum omap_display_type omap4_dss_supported_displays[] = {
+ /* OMAP_DSS_CHANNEL_LCD */
+ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
+
+ /* OMAP_DSS_CHANNEL_DIGIT */
+ OMAP_DISPLAY_TYPE_VENC,
+
+ /* OMAP_DSS_CHANNEL_LCD2 */
+ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
+ OMAP_DISPLAY_TYPE_DSI,
+};
+
static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
@@ -127,6 +139,10 @@ static struct omap_dss_features omap2_dss_features = {
.reg_fields = omap2_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
+ .has_feature =
+ FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
+ FEAT_PCKFREEENABLE | FEAT_FUNCGATED,
+
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap2_dss_supported_displays,
@@ -138,7 +154,10 @@ static struct omap_dss_features omap3430_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
- .has_feature = FEAT_GLOBAL_ALPHA,
+ .has_feature =
+ FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
+ FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
+ FEAT_FUNCGATED,
.num_mgrs = 2,
.num_ovls = 3,
@@ -150,7 +169,10 @@ static struct omap_dss_features omap3630_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
- .has_feature = FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA,
+ .has_feature =
+ FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
+ FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
+ FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED,
.num_mgrs = 2,
.num_ovls = 3,
@@ -158,6 +180,21 @@ static struct omap_dss_features omap3630_dss_features = {
.supported_color_modes = omap3_dss_supported_color_modes,
};
+/* OMAP4 DSS Features */
+static struct omap_dss_features omap4_dss_features = {
+ .reg_fields = omap3_dss_reg_fields,
+ .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
+
+ .has_feature =
+ FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
+ FEAT_MGR_LCD2,
+
+ .num_mgrs = 3,
+ .num_ovls = 3,
+ .supported_displays = omap4_dss_supported_displays,
+ .supported_color_modes = omap3_dss_supported_color_modes,
+};
+
/* Functions returning values related to a DSS feature */
int dss_feat_get_num_mgrs(void)
{
@@ -202,4 +239,6 @@ void dss_features_init(void)
omap_current_dss_features = &omap3630_dss_features;
else if (cpu_is_omap34xx())
omap_current_dss_features = &omap3430_dss_features;
+ else
+ omap_current_dss_features = &omap4_dss_features;
}
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index aeb2eea..161d378 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -20,7 +20,7 @@
#ifndef __OMAP2_DSS_FEATURES_H
#define __OMAP2_DSS_FEATURES_H
-#define MAX_DSS_MANAGERS 2
+#define MAX_DSS_MANAGERS 3
#define MAX_DSS_OVERLAYS 3
/* DSS has feature id */
@@ -28,6 +28,11 @@ enum dss_feat_id {
FEAT_GLOBAL_ALPHA = 1 << 0,
FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
FEAT_PRE_MULT_ALPHA = 1 << 2,
+ FEAT_LCDENABLEPOL = 1 << 3,
+ FEAT_LCDENABLESIGNAL = 1 << 4,
+ FEAT_PCKFREEENABLE = 1 << 5,
+ FEAT_FUNCGATED = 1 << 6,
+ FEAT_MGR_LCD2 = 1 << 7,
};
/* DSS register field id */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v4 2/7] OMAP: DSS2: Represent DISPC register defines with channel as parameter
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
2010-11-08 12:24 ` [PATCH v4 1/7] OMAP: DSS2: Add dss_features for omap4 and overlay manager related features Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
2010-11-15 15:17 ` Tomi Valkeinen
2010-11-08 12:24 ` [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter Archit Taneja
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Samreen
From: Sumit Semwal <sumit.semwal@ti.com>
Introduce new enum members for LCD2 Channel and corresponding Overlay Manager.
Represent some of the DISPC register defines with channel as a parameter
to differentiate between LCD, DIGIT and LCD2 channels. Replace the existing
reads/writes to these registers in this new way.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
arch/arm/plat-omap/include/plat/display.h | 2 +
drivers/video/omap2/dss/dispc.c | 255 ++++++++++++++---------------
2 files changed, 128 insertions(+), 129 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index d433baf..586944d 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -64,6 +64,7 @@ enum omap_plane {
enum omap_channel {
OMAP_DSS_CHANNEL_LCD = 0,
OMAP_DSS_CHANNEL_DIGIT = 1,
+ OMAP_DSS_CHANNEL_LCD2 = 2,
};
enum omap_color_mode {
@@ -142,6 +143,7 @@ enum omap_dss_display_state {
enum omap_dss_overlay_managers {
OMAP_DSS_OVL_MGR_LCD,
OMAP_DSS_OVL_MGR_TV,
+ OMAP_DSS_OVL_MGR_LCD2,
};
enum omap_dss_rotation_type {
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 54ba8d3..493e0f9 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -44,34 +44,38 @@
/* DISPC */
#define DISPC_BASE 0x48050400
-#define DISPC_SZ_REGS SZ_1K
+#define DISPC_SZ_REGS SZ_4K
struct dispc_reg { u16 idx; };
#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
-/* DISPC common */
+/*
+ * DISPC common registers and
+ * DISPC channel registers , ch = 0 for LCD, ch = 1 for
+ * DIGIT, and ch = 2 for LCD2
+ */
#define DISPC_REVISION DISPC_REG(0x0000)
#define DISPC_SYSCONFIG DISPC_REG(0x0010)
#define DISPC_SYSSTATUS DISPC_REG(0x0014)
#define DISPC_IRQSTATUS DISPC_REG(0x0018)
#define DISPC_IRQENABLE DISPC_REG(0x001C)
-#define DISPC_CONTROL DISPC_REG(0x0040)
-#define DISPC_CONFIG DISPC_REG(0x0044)
+#define DISPC_CONTROL(ch) DISPC_REG(ch != 2 ? 0x0040 : 0x0238)
+#define DISPC_CONFIG(ch) DISPC_REG(ch != 2 ? 0x0044 : 0x0620)
#define DISPC_CAPABLE DISPC_REG(0x0048)
-#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
-#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
-#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
-#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
+#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
+ (ch == 1 ? 0x0050 : 0x03AC))
+#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
+ (ch == 1 ? 0x0058 : 0x03B0))
#define DISPC_LINE_STATUS DISPC_REG(0x005C)
#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
-#define DISPC_TIMING_H DISPC_REG(0x0064)
-#define DISPC_TIMING_V DISPC_REG(0x0068)
-#define DISPC_POL_FREQ DISPC_REG(0x006C)
-#define DISPC_DIVISOR DISPC_REG(0x0070)
+#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
+#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
+#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
+#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
#define DISPC_SIZE_DIG DISPC_REG(0x0078)
-#define DISPC_SIZE_LCD DISPC_REG(0x007C)
+#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
/* DISPC GFX plane */
#define DISPC_GFX_BA0 DISPC_REG(0x0080)
@@ -86,13 +90,12 @@ struct dispc_reg { u16 idx; };
#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
-#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
-#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
-#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
-
-#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
-#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
-#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
+#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
+#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
+#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
+#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
+#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
+#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
@@ -215,20 +218,20 @@ void dispc_save_context(void)
SR(SYSCONFIG);
SR(IRQENABLE);
- SR(CONTROL);
- SR(CONFIG);
- SR(DEFAULT_COLOR0);
- SR(DEFAULT_COLOR1);
- SR(TRANS_COLOR0);
- SR(TRANS_COLOR1);
+ SR(CONTROL(0));
+ SR(CONFIG(0));
+ SR(DEFAULT_COLOR(0));
+ SR(DEFAULT_COLOR(1));
+ SR(TRANS_COLOR(0));
+ SR(TRANS_COLOR(1));
SR(LINE_NUMBER);
- SR(TIMING_H);
- SR(TIMING_V);
- SR(POL_FREQ);
- SR(DIVISOR);
+ SR(TIMING_H(0));
+ SR(TIMING_V(0));
+ SR(POL_FREQ(0));
+ SR(DIVISOR(0));
SR(GLOBAL_ALPHA);
SR(SIZE_DIG);
- SR(SIZE_LCD);
+ SR(SIZE_LCD(0));
SR(GFX_BA0);
SR(GFX_BA1);
@@ -241,13 +244,13 @@ void dispc_save_context(void)
SR(GFX_WINDOW_SKIP);
SR(GFX_TABLE_BA);
- SR(DATA_CYCLE1);
- SR(DATA_CYCLE2);
- SR(DATA_CYCLE3);
+ SR(DATA_CYCLE1(0));
+ SR(DATA_CYCLE2(0));
+ SR(DATA_CYCLE3(0));
- SR(CPR_COEF_R);
- SR(CPR_COEF_G);
- SR(CPR_COEF_B);
+ SR(CPR_COEF_R(0));
+ SR(CPR_COEF_G(0));
+ SR(CPR_COEF_B(0));
SR(GFX_PRELOAD);
@@ -355,19 +358,19 @@ void dispc_restore_context(void)
RR(SYSCONFIG);
/*RR(IRQENABLE);*/
/*RR(CONTROL);*/
- RR(CONFIG);
- RR(DEFAULT_COLOR0);
- RR(DEFAULT_COLOR1);
- RR(TRANS_COLOR0);
- RR(TRANS_COLOR1);
+ RR(CONFIG(0));
+ RR(DEFAULT_COLOR(0));
+ RR(DEFAULT_COLOR(1));
+ RR(TRANS_COLOR(0));
+ RR(TRANS_COLOR(1));
RR(LINE_NUMBER);
- RR(TIMING_H);
- RR(TIMING_V);
- RR(POL_FREQ);
- RR(DIVISOR);
+ RR(TIMING_H(0));
+ RR(TIMING_V(0));
+ RR(POL_FREQ(0));
+ RR(DIVISOR(0));
RR(GLOBAL_ALPHA);
RR(SIZE_DIG);
- RR(SIZE_LCD);
+ RR(SIZE_LCD(0));
RR(GFX_BA0);
RR(GFX_BA1);
@@ -380,13 +383,13 @@ void dispc_restore_context(void)
RR(GFX_WINDOW_SKIP);
RR(GFX_TABLE_BA);
- RR(DATA_CYCLE1);
- RR(DATA_CYCLE2);
- RR(DATA_CYCLE3);
+ RR(DATA_CYCLE1(0));
+ RR(DATA_CYCLE2(0));
+ RR(DATA_CYCLE3(0));
- RR(CPR_COEF_R);
- RR(CPR_COEF_G);
- RR(CPR_COEF_B);
+ RR(CPR_COEF_R(0));
+ RR(CPR_COEF_G(0));
+ RR(CPR_COEF_B(0));
RR(GFX_PRELOAD);
@@ -489,7 +492,7 @@ void dispc_restore_context(void)
RR(VID_PRELOAD(1));
/* enable last, because LCD & DIGIT enable are here */
- RR(CONTROL);
+ RR(CONTROL(0));
/* clear spurious SYNC_LOST_DIGIT interrupts */
dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
@@ -521,7 +524,7 @@ bool dispc_go_busy(enum omap_channel channel)
else
bit = 6; /* GODIGIT */
- return REG_GET(DISPC_CONTROL, bit, bit) == 1;
+ return REG_GET(DISPC_CONTROL(channel), bit, bit) == 1;
}
void dispc_go(enum omap_channel channel)
@@ -536,7 +539,7 @@ void dispc_go(enum omap_channel channel)
bit = 1; /* DIGITALENABLE */
/* if the channel is not enabled, we don't need GO */
- if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
+ if (REG_GET(DISPC_CONTROL(channel), bit, bit) == 0)
goto end;
if (channel == OMAP_DSS_CHANNEL_LCD)
@@ -544,14 +547,14 @@ void dispc_go(enum omap_channel channel)
else
bit = 6; /* GODIGIT */
- if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
+ if (REG_GET(DISPC_CONTROL(channel), bit, bit) == 1) {
DSSERR("GO bit not down for channel %d\n", channel);
goto end;
}
DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
- REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
+ REG_FLD_MOD(DISPC_CONTROL(channel), 1, bit, bit);
end:
enable_clocks(0);
}
@@ -942,7 +945,7 @@ void dispc_set_lcd_size(u16 width, u16 height)
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
enable_clocks(1);
- dispc_write_reg(DISPC_SIZE_LCD, val);
+ dispc_write_reg(DISPC_SIZE_LCD(OMAP_DSS_CHANNEL_LCD), val);
enable_clocks(0);
}
@@ -1012,7 +1015,7 @@ void dispc_enable_fifomerge(bool enable)
enable_clocks(1);
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
- REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
+ REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD), enable ? 1 : 0, 14, 14);
enable_clocks(0);
}
@@ -1726,7 +1729,7 @@ static void dispc_disable_isr(void *data, u32 mask)
static void _enable_lcd_out(bool enable)
{
- REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), enable ? 1 : 0, 0, 0);
}
static void dispc_enable_lcd_out(bool enable)
@@ -1740,7 +1743,7 @@ static void dispc_enable_lcd_out(bool enable)
/* When we disable LCD output, we need to wait until frame is done.
* Otherwise the DSS is still working, and turning off the clocks
* prevents DSS from going to OFF mode */
- is_on = REG_GET(DISPC_CONTROL, 0, 0);
+ is_on = REG_GET(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), 0, 0);
if (!enable && is_on) {
init_completion(&frame_done_completion);
@@ -1773,7 +1776,8 @@ static void dispc_enable_lcd_out(bool enable)
static void _enable_digit_out(bool enable)
{
- REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_DIGIT),
+ enable ? 1 : 0, 1, 1);
}
static void dispc_enable_digit_out(bool enable)
@@ -1783,7 +1787,7 @@ static void dispc_enable_digit_out(bool enable)
enable_clocks(1);
- if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
+ if (REG_GET(DISPC_CONTROL(OMAP_DSS_CHANNEL_DIGIT), 1, 1) == enable) {
enable_clocks(0);
return;
}
@@ -1843,9 +1847,9 @@ static void dispc_enable_digit_out(bool enable)
bool dispc_is_channel_enabled(enum omap_channel channel)
{
if (channel == OMAP_DSS_CHANNEL_LCD)
- return !!REG_GET(DISPC_CONTROL, 0, 0);
+ return !!REG_GET(DISPC_CONTROL(channel), 0, 0);
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
- return !!REG_GET(DISPC_CONTROL, 1, 1);
+ return !!REG_GET(DISPC_CONTROL(channel), 1, 1);
else
BUG();
}
@@ -1863,28 +1867,32 @@ void dispc_enable_channel(enum omap_channel channel, bool enable)
void dispc_lcd_enable_signal_polarity(bool act_high)
{
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD),
+ act_high ? 1 : 0, 29, 29);
enable_clocks(0);
}
void dispc_lcd_enable_signal(bool enable)
{
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD),
+ enable ? 1 : 0, 28, 28);
enable_clocks(0);
}
void dispc_pck_free_enable(bool enable)
{
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD),
+ enable ? 1 : 0, 27, 27);
enable_clocks(0);
}
void dispc_enable_fifohandcheck(bool enable)
{
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
+ REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD),
+ enable ? 1 : 0, 16, 16);
enable_clocks(0);
}
@@ -1908,39 +1916,34 @@ void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
}
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), mode, 3, 3);
enable_clocks(0);
}
void dispc_set_loadmode(enum omap_dss_load_mode mode)
{
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
+ REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD), mode, 2, 1);
enable_clocks(0);
}
void dispc_set_default_color(enum omap_channel channel, u32 color)
{
- const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
- DISPC_DEFAULT_COLOR1 };
-
enable_clocks(1);
- dispc_write_reg(def_reg[channel], color);
+ dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
enable_clocks(0);
}
u32 dispc_get_default_color(enum omap_channel channel)
{
- const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
- DISPC_DEFAULT_COLOR1 };
u32 l;
BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
channel != OMAP_DSS_CHANNEL_LCD);
enable_clocks(1);
- l = dispc_read_reg(def_reg[channel]);
+ l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
enable_clocks(0);
return l;
@@ -1950,16 +1953,13 @@ void dispc_set_trans_key(enum omap_channel ch,
enum omap_dss_trans_key_type type,
u32 trans_key)
{
- const struct dispc_reg tr_reg[] = {
- DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
-
enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
- REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
+ REG_FLD_MOD(DISPC_CONFIG(ch), type, 11, 11);
else /* OMAP_DSS_CHANNEL_DIGIT */
- REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
+ REG_FLD_MOD(DISPC_CONFIG(ch), type, 13, 13);
- dispc_write_reg(tr_reg[ch], trans_key);
+ dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
enable_clocks(0);
}
@@ -1967,21 +1967,18 @@ void dispc_get_trans_key(enum omap_channel ch,
enum omap_dss_trans_key_type *type,
u32 *trans_key)
{
- const struct dispc_reg tr_reg[] = {
- DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
-
enable_clocks(1);
if (type) {
if (ch == OMAP_DSS_CHANNEL_LCD)
- *type = REG_GET(DISPC_CONFIG, 11, 11);
+ *type = REG_GET(DISPC_CONFIG(ch), 11, 11);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
- *type = REG_GET(DISPC_CONFIG, 13, 13);
+ *type = REG_GET(DISPC_CONFIG(ch), 13, 13);
else
BUG();
}
if (trans_key)
- *trans_key = dispc_read_reg(tr_reg[ch]);
+ *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
enable_clocks(0);
}
@@ -1989,9 +1986,9 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable)
{
enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
- REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
+ REG_FLD_MOD(DISPC_CONFIG(ch), enable, 10, 10);
else /* OMAP_DSS_CHANNEL_DIGIT */
- REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
+ REG_FLD_MOD(DISPC_CONFIG(ch), enable, 12, 12);
enable_clocks(0);
}
void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
@@ -2001,9 +1998,9 @@ void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
- REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
+ REG_FLD_MOD(DISPC_CONFIG(ch), enable, 18, 18);
else /* OMAP_DSS_CHANNEL_DIGIT */
- REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
+ REG_FLD_MOD(DISPC_CONFIG(ch), enable, 19, 19);
enable_clocks(0);
}
bool dispc_alpha_blending_enabled(enum omap_channel ch)
@@ -2015,9 +2012,9 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
- enabled = REG_GET(DISPC_CONFIG, 18, 18);
+ enabled = REG_GET(DISPC_CONFIG(ch), 18, 18);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
- enabled = REG_GET(DISPC_CONFIG, 19, 19);
+ enabled = REG_GET(DISPC_CONFIG(ch), 19, 19);
else
BUG();
enable_clocks(0);
@@ -2032,9 +2029,9 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
- enabled = REG_GET(DISPC_CONFIG, 10, 10);
+ enabled = REG_GET(DISPC_CONFIG(ch), 10, 10);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
- enabled = REG_GET(DISPC_CONFIG, 12, 12);
+ enabled = REG_GET(DISPC_CONFIG(ch), 12, 12);
else
BUG();
enable_clocks(0);
@@ -2066,7 +2063,7 @@ void dispc_set_tft_data_lines(u8 data_lines)
}
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
+ REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), code, 9, 8);
enable_clocks(0);
}
@@ -2100,13 +2097,13 @@ void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
enable_clocks(1);
- l = dispc_read_reg(DISPC_CONTROL);
+ l = dispc_read_reg(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD));
l = FLD_MOD(l, stallmode, 11, 11);
l = FLD_MOD(l, gpout0, 15, 15);
l = FLD_MOD(l, gpout1, 16, 16);
- dispc_write_reg(DISPC_CONTROL, l);
+ dispc_write_reg(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), l);
enable_clocks(0);
}
@@ -2162,8 +2159,8 @@ static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
}
enable_clocks(1);
- dispc_write_reg(DISPC_TIMING_H, timing_h);
- dispc_write_reg(DISPC_TIMING_V, timing_v);
+ dispc_write_reg(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), timing_h);
+ dispc_write_reg(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD), timing_v);
enable_clocks(0);
}
@@ -2204,7 +2201,7 @@ static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
BUG_ON(pck_div < 2);
enable_clocks(1);
- dispc_write_reg(DISPC_DIVISOR,
+ dispc_write_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
enable_clocks(0);
}
@@ -2212,7 +2209,7 @@ static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
{
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR);
+ l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
}
@@ -2238,7 +2235,7 @@ unsigned long dispc_lclk_rate(void)
unsigned long r;
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR);
+ l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
lcd = FLD_GET(l, 23, 16);
@@ -2253,7 +2250,7 @@ unsigned long dispc_pclk_rate(void)
unsigned long r;
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR);
+ l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
lcd = FLD_GET(l, 23, 16);
pcd = FLD_GET(l, 7, 0);
@@ -2337,22 +2334,22 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_SYSSTATUS);
DUMPREG(DISPC_IRQSTATUS);
DUMPREG(DISPC_IRQENABLE);
- DUMPREG(DISPC_CONTROL);
- DUMPREG(DISPC_CONFIG);
+ DUMPREG(DISPC_CONTROL(0));
+ DUMPREG(DISPC_CONFIG(0));
DUMPREG(DISPC_CAPABLE);
- DUMPREG(DISPC_DEFAULT_COLOR0);
- DUMPREG(DISPC_DEFAULT_COLOR1);
- DUMPREG(DISPC_TRANS_COLOR0);
- DUMPREG(DISPC_TRANS_COLOR1);
+ DUMPREG(DISPC_DEFAULT_COLOR(0));
+ DUMPREG(DISPC_DEFAULT_COLOR(1));
+ DUMPREG(DISPC_TRANS_COLOR(0));
+ DUMPREG(DISPC_TRANS_COLOR(1));
DUMPREG(DISPC_LINE_STATUS);
DUMPREG(DISPC_LINE_NUMBER);
- DUMPREG(DISPC_TIMING_H);
- DUMPREG(DISPC_TIMING_V);
- DUMPREG(DISPC_POL_FREQ);
- DUMPREG(DISPC_DIVISOR);
+ DUMPREG(DISPC_TIMING_H(0));
+ DUMPREG(DISPC_TIMING_V(0));
+ DUMPREG(DISPC_POL_FREQ(0));
+ DUMPREG(DISPC_DIVISOR(0));
DUMPREG(DISPC_GLOBAL_ALPHA);
DUMPREG(DISPC_SIZE_DIG);
- DUMPREG(DISPC_SIZE_LCD);
+ DUMPREG(DISPC_SIZE_LCD(0));
DUMPREG(DISPC_GFX_BA0);
DUMPREG(DISPC_GFX_BA1);
@@ -2366,13 +2363,13 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_GFX_WINDOW_SKIP);
DUMPREG(DISPC_GFX_TABLE_BA);
- DUMPREG(DISPC_DATA_CYCLE1);
- DUMPREG(DISPC_DATA_CYCLE2);
- DUMPREG(DISPC_DATA_CYCLE3);
+ DUMPREG(DISPC_DATA_CYCLE1(0));
+ DUMPREG(DISPC_DATA_CYCLE2(0));
+ DUMPREG(DISPC_DATA_CYCLE3(0));
- DUMPREG(DISPC_CPR_COEF_R);
- DUMPREG(DISPC_CPR_COEF_G);
- DUMPREG(DISPC_CPR_COEF_B);
+ DUMPREG(DISPC_CPR_COEF_R(0));
+ DUMPREG(DISPC_CPR_COEF_G(0));
+ DUMPREG(DISPC_CPR_COEF_B(0));
DUMPREG(DISPC_GFX_PRELOAD);
@@ -2489,7 +2486,7 @@ static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
l |= FLD_VAL(acb, 7, 0);
enable_clocks(1);
- dispc_write_reg(DISPC_POL_FREQ, l);
+ dispc_write_reg(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD), l);
enable_clocks(0);
}
@@ -2580,8 +2577,8 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo)
fck = dispc_fclk_rate();
- cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
- cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
+ cinfo->lck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 23, 16);
+ cinfo->pck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 7, 0);
cinfo->lck = fck / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
@@ -3078,7 +3075,7 @@ static void _omap_dispc_initial_config(void)
dispc_write_reg(DISPC_SYSCONFIG, l);
/* FUNCGATED */
- REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
+ REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD), 1, 9, 9);
/* L3 firewall setting: enable access to OCM RAM */
/* XXX this should be somewhere in plat-omap */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/7] OMAP: DSS2: Represent DISPC register defines with channel as parameter
2010-11-08 12:24 ` [PATCH v4 2/7] OMAP: DSS2: Represent DISPC register defines with channel as parameter Archit Taneja
@ 2010-11-15 15:17 ` Tomi Valkeinen
2010-11-16 4:25 ` Taneja, Archit
0 siblings, 1 reply; 15+ messages in thread
From: Tomi Valkeinen @ 2010-11-15 15:17 UTC (permalink / raw)
To: ext Archit Taneja
Cc: linux-omap@vger.kernel.org, Sumit Semwal, Mukund Mittal, Samreen
Hi,
On Mon, 2010-11-08 at 13:24 +0100, ext Archit Taneja wrote:
> From: Sumit Semwal <sumit.semwal@ti.com>
>
> Introduce new enum members for LCD2 Channel and corresponding Overlay Manager.
>
> Represent some of the DISPC register defines with channel as a parameter
> to differentiate between LCD, DIGIT and LCD2 channels. Replace the existing
> reads/writes to these registers in this new way.
>
> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
> Signed-off-by: Mukund Mittal <mmittal@ti.com>
> Signed-off-by: Samreen <samreen@ti.com>
<snip>
> @@ -1843,9 +1847,9 @@ static void dispc_enable_digit_out(bool enable)
> bool dispc_is_channel_enabled(enum omap_channel channel)
> {
> if (channel == OMAP_DSS_CHANNEL_LCD)
> - return !!REG_GET(DISPC_CONTROL, 0, 0);
> + return !!REG_GET(DISPC_CONTROL(channel), 0, 0);
> else if (channel == OMAP_DSS_CHANNEL_DIGIT)
> - return !!REG_GET(DISPC_CONTROL, 1, 1);
> + return !!REG_GET(DISPC_CONTROL(channel), 1, 1);
> else
> BUG();
> }
I don't think this is good.
Looking at the code here, it looks like we're accessing different
DISPC_CONTROL registers for LCD and DIGIT out. But we're not.
For some registers it's good to have DISPC_XXX(ch) style, when the
registers are accessed identically for different channels. Then you can
just modify the same bits in DISPC_REG(ch) register, and you don't have
to mind what the channel actually is.
But this is not the case in the function above.
The DISPC_CONTROL(ch) is defined as:
DISPC_REG(ch != 2 ? 0x0040 : 0x0238)
I don't think this is actually right. DISPC_CONTROL is not a register
defined per channel. The register at 0x40 contains bits for both
channels 0 and 1. Perhaps leave DISPC_CONTROL as it was, and add
DISPC_CONTROL2, because the registers are not used similarly for all
channels. Or you can come up with some other solution, but using channel
as argument for the macro doesn't look right.
The same comments apply to other functions using DISPC_CONTROL(channel).
(And possibly to some other registers which are similar).
Tomi
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v4 2/7] OMAP: DSS2: Represent DISPC register defines with channel as parameter
2010-11-15 15:17 ` Tomi Valkeinen
@ 2010-11-16 4:25 ` Taneja, Archit
0 siblings, 0 replies; 15+ messages in thread
From: Taneja, Archit @ 2010-11-16 4:25 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund,
Nilofer, Samreen
Hi,
Tomi Valkeinen wrote:
> Hi,
>
> On Mon, 2010-11-08 at 13:24 +0100, ext Archit Taneja wrote:
>> From: Sumit Semwal <sumit.semwal@ti.com>
>>
>> Introduce new enum members for LCD2 Channel and corresponding Overlay
>> Manager.
>>
>> Represent some of the DISPC register defines with channel as a
>> parameter to differentiate between LCD, DIGIT and LCD2 channels.
>> Replace the existing reads/writes to these registers in this new way.
>>
>> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
>> Signed-off-by: Mukund Mittal <mmittal@ti.com>
>> Signed-off-by: Samreen <samreen@ti.com>
>
> <snip>
>
>> @@ -1843,9 +1847,9 @@ static void
> dispc_enable_digit_out(bool enable)
>> bool dispc_is_channel_enabled(enum omap_channel channel) {
>> if (channel == OMAP_DSS_CHANNEL_LCD)
>> - return !!REG_GET(DISPC_CONTROL, 0, 0);
>> + return !!REG_GET(DISPC_CONTROL(channel), 0, 0);
>> else if (channel == OMAP_DSS_CHANNEL_DIGIT)
>> - return !!REG_GET(DISPC_CONTROL, 1, 1);
>> + return !!REG_GET(DISPC_CONTROL(channel), 1, 1); else
>> BUG();
>> }
>
> I don't think this is good.
>
> Looking at the code here, it looks like we're accessing
> different DISPC_CONTROL registers for LCD and DIGIT out. But we're not.
>
> For some registers it's good to have DISPC_XXX(ch) style,
> when the registers are accessed identically for different
> channels. Then you can just modify the same bits in
> DISPC_REG(ch) register, and you don't have to mind what the channel actually
> is.
>
> But this is not the case in the function above.
>
> The DISPC_CONTROL(ch) is defined as:
> DISPC_REG(ch != 2 ? 0x0040 : 0x0238)
>
> I don't think this is actually right. DISPC_CONTROL is not a
> register defined per channel. The register at 0x40 contains
> bits for both channels 0 and 1. Perhaps leave DISPC_CONTROL
> as it was, and add DISPC_CONTROL2, because the registers are
> not used similarly for all channels. Or you can come up with
> some other solution, but using channel as argument for the macro doesn't look
> right.
Yes, this holds for DISPC_CONTROL and DISPC_CONFIG registers, I didn't
think it would be wrong if 2 channels point to the same register field.
But apart from that, there are some bits in these registers which are
not specific to any channel and doing something like this would be misleading,
For setting fifiomerge:
REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD), enable ? 1 : 0, 14, 14);
Since the above bit is not specific to LCD channel.
I'll keep these 2 registers the way they are.
Thanks,
Archit
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
2010-11-08 12:24 ` [PATCH v4 1/7] OMAP: DSS2: Add dss_features for omap4 and overlay manager related features Archit Taneja
2010-11-08 12:24 ` [PATCH v4 2/7] OMAP: DSS2: Represent DISPC register defines with channel as parameter Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
2010-11-16 10:55 ` Tomi Valkeinen
2010-11-08 12:24 ` [PATCH v4 4/7] OMAP: DSS2: Change remaining Dispc functions for new 'channel' argument Archit Taneja
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Samreen
From: Sumit Semwal <sumit.semwal@ti.com>
A new member 'channel' is introduced in omap_dss_device structure to determine
which channel the panel uses. The dispc functions used by interface drivers
(dsi, sdi etc) will use this member to differentiate between the 2 channels.
The following dispc functions are changed to incorporate channel as an argument:
-dispc_enable_fifohandcheck()
-dispc_set_lcd_size()
-dispc_set_parallel_interface_mode()
-dispc_set_tft_data_lines()
-dispc_set_lcd_display_type()
-dispc_set_lcd_timings()
The calls to these functions from the interface drivers have been changed to
incorporate the new channel argument.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
arch/arm/plat-omap/include/plat/display.h | 1 +
drivers/video/omap2/dss/dispc.c | 49 ++++++++++++++++-------------
drivers/video/omap2/dss/dpi.c | 11 +++---
drivers/video/omap2/dss/dsi.c | 13 ++++---
drivers/video/omap2/dss/dss.h | 19 ++++++-----
drivers/video/omap2/dss/rfbi.c | 19 ++++++-----
drivers/video/omap2/dss/sdi.c | 14 +++++---
7 files changed, 70 insertions(+), 56 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 586944d..3e6eec1 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -434,6 +434,7 @@ struct omap_dss_device {
struct omap_overlay_manager *manager;
enum omap_dss_display_state state;
+ enum omap_channel channel;
/* platform specific */
int (*platform_enable)(struct omap_dss_device *dssdev);
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 493e0f9..2ea1a7a 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -939,13 +939,13 @@ void dispc_enable_replication(enum omap_plane plane, bool enable)
enable_clocks(0);
}
-void dispc_set_lcd_size(u16 width, u16 height)
+void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
{
u32 val;
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
enable_clocks(1);
- dispc_write_reg(DISPC_SIZE_LCD(OMAP_DSS_CHANNEL_LCD), val);
+ dispc_write_reg(DISPC_SIZE_LCD(channel), val);
enable_clocks(0);
}
@@ -1888,16 +1888,16 @@ void dispc_pck_free_enable(bool enable)
enable_clocks(0);
}
-void dispc_enable_fifohandcheck(bool enable)
+void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
{
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD),
- enable ? 1 : 0, 16, 16);
+ REG_FLD_MOD(DISPC_CONFIG(channel), enable ? 1 : 0, 16, 16);
enable_clocks(0);
}
-void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
+void dispc_set_lcd_display_type(enum omap_channel channel,
+ enum omap_lcd_display_type type)
{
int mode;
@@ -1916,7 +1916,7 @@ void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
}
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), mode, 3, 3);
+ REG_FLD_MOD(DISPC_CONTROL(channel), mode, 3, 3);
enable_clocks(0);
}
@@ -2040,7 +2040,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
}
-void dispc_set_tft_data_lines(u8 data_lines)
+void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
{
int code;
@@ -2063,11 +2063,12 @@ void dispc_set_tft_data_lines(u8 data_lines)
}
enable_clocks(1);
- REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), code, 9, 8);
+ REG_FLD_MOD(DISPC_CONTROL(channel), code, 9, 8);
enable_clocks(0);
}
-void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
+void dispc_set_parallel_interface_mode(enum omap_channel channel,
+ enum omap_parallel_interface_mode mode)
{
u32 l;
int stallmode;
@@ -2097,13 +2098,15 @@ void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
enable_clocks(1);
- l = dispc_read_reg(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD));
+ l = dispc_read_reg(DISPC_CONTROL(channel));
l = FLD_MOD(l, stallmode, 11, 11);
- l = FLD_MOD(l, gpout0, 15, 15);
- l = FLD_MOD(l, gpout1, 16, 16);
- dispc_write_reg(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), l);
+ if (channel == OMAP_DSS_CHANNEL_LCD) {
+ l = FLD_MOD(l, gpout0, 15, 15);
+ l = FLD_MOD(l, gpout1, 16, 16);
+ }
+ dispc_write_reg(DISPC_CONTROL(channel), l);
enable_clocks(0);
}
@@ -2139,8 +2142,8 @@ bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
timings->vfp, timings->vbp);
}
-static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
- int vsw, int vfp, int vbp)
+static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
+ int hfp, int hbp, int vsw, int vfp, int vbp)
{
u32 timing_h, timing_v;
@@ -2159,13 +2162,14 @@ static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
}
enable_clocks(1);
- dispc_write_reg(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), timing_h);
- dispc_write_reg(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD), timing_v);
+ dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
+ dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
enable_clocks(0);
}
/* change name to mode? */
-void dispc_set_lcd_timings(struct omap_video_timings *timings)
+void dispc_set_lcd_timings(enum omap_channel channel,
+ struct omap_video_timings *timings)
{
unsigned xtot, ytot;
unsigned long ht, vt;
@@ -2175,10 +2179,11 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
timings->vfp, timings->vbp))
BUG();
- _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
- timings->vsw, timings->vfp, timings->vbp);
+ _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
+ timings->hbp, timings->vsw, timings->vfp,
+ timings->vbp);
- dispc_set_lcd_size(timings->x_res, timings->y_res);
+ dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 960e977..51040dc 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -132,7 +132,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
t->pixel_clock = pck;
}
- dispc_set_lcd_timings(t);
+ dispc_set_lcd_timings(dssdev->channel, t);
err0:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
@@ -145,10 +145,11 @@ static int dpi_basic_init(struct omap_dss_device *dssdev)
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
- dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
- dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
- OMAP_DSS_LCD_DISPLAY_STN);
- dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines);
+ dispc_set_parallel_interface_mode(dssdev->channel,
+ OMAP_DSS_PARALLELMODE_BYPASS);
+ dispc_set_lcd_display_type(dssdev->channel, is_tft ?
+ OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
+ dispc_set_tft_data_lines(dssdev->channel, dssdev->phy.dpi.data_lines);
return 0;
}
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index aa4f7a5..a4c031e 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -2888,7 +2888,7 @@ int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
dss_setup_partial_planes(dssdev, x, y, w, h,
enlarge_update_area);
- dispc_set_lcd_size(*w, *h);
+ dispc_set_lcd_size(dssdev->channel, *w, *h);
}
return 0;
@@ -2947,12 +2947,13 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
return r;
}
- dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
+ dispc_set_lcd_display_type(dssdev->channel, OMAP_DSS_LCD_DISPLAY_TFT);
- dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
- dispc_enable_fifohandcheck(1);
+ dispc_set_parallel_interface_mode(dssdev->channel,
+ OMAP_DSS_PARALLELMODE_DSI);
+ dispc_enable_fifohandcheck(dssdev->channel, 1);
- dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
+ dispc_set_tft_data_lines(dssdev->channel, dssdev->ctrl.pixel_size);
{
struct omap_video_timings timings = {
@@ -2964,7 +2965,7 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
.vbp = 0,
};
- dispc_set_lcd_timings(&timings);
+ dispc_set_lcd_timings(dssdev->channel, &timings);
}
return 0;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 2bb515c..68f7c42 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -333,9 +333,9 @@ void dispc_disable_sidle(void);
void dispc_lcd_enable_signal_polarity(bool act_high);
void dispc_lcd_enable_signal(bool enable);
void dispc_pck_free_enable(bool enable);
-void dispc_enable_fifohandcheck(bool enable);
+void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
-void dispc_set_lcd_size(u16 width, u16 height);
+void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
void dispc_set_digit_size(u16 width, u16 height);
u32 dispc_get_plane_fifo_size(enum omap_plane plane);
void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
@@ -369,9 +369,11 @@ bool dispc_is_channel_enabled(enum omap_channel channel);
int dispc_enable_plane(enum omap_plane plane, bool enable);
void dispc_enable_replication(enum omap_plane plane, bool enable);
-void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
-void dispc_set_tft_data_lines(u8 data_lines);
-void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
+void dispc_set_parallel_interface_mode(enum omap_channel channel,
+ enum omap_parallel_interface_mode mode);
+void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
+void dispc_set_lcd_display_type(enum omap_channel channel,
+ enum omap_lcd_display_type type);
void dispc_set_loadmode(enum omap_dss_load_mode mode);
void dispc_set_default_color(enum omap_channel channel, u32 color);
@@ -388,7 +390,8 @@ bool dispc_trans_key_enabled(enum omap_channel ch);
bool dispc_alpha_blending_enabled(enum omap_channel ch);
bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
-void dispc_set_lcd_timings(struct omap_video_timings *timings);
+void dispc_set_lcd_timings(enum omap_channel channel,
+ struct omap_video_timings *timings);
unsigned long dispc_fclk_rate(void);
unsigned long dispc_lclk_rate(void);
unsigned long dispc_pclk_rate(void);
@@ -425,8 +428,8 @@ void rfbi_dump_regs(struct seq_file *s);
int rfbi_configure(int rfbi_module, int bpp, int lines);
void rfbi_enable_rfbi(bool enable);
-void rfbi_transfer_area(u16 width, u16 height,
- void (callback)(void *data), void *data);
+void rfbi_transfer_area(enum omap_channel channel, u16 width,
+ u16 height, void (callback)(void *data), void *data);
void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
unsigned long rfbi_get_max_tx_rate(void);
int rfbi_init_display(struct omap_dss_device *display);
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index bbe6246..08cf3c6 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -301,8 +301,8 @@ void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
}
EXPORT_SYMBOL(omap_rfbi_write_pixels);
-void rfbi_transfer_area(u16 width, u16 height,
- void (callback)(void *data), void *data)
+void rfbi_transfer_area(enum omap_channel channel, u16 width,
+ u16 height, void (*callback)(void *data), void *data)
{
u32 l;
@@ -311,9 +311,9 @@ void rfbi_transfer_area(u16 width, u16 height,
DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
- dispc_set_lcd_size(width, height);
+ dispc_set_lcd_size(channel, width, height);
- dispc_enable_channel(OMAP_DSS_CHANNEL_LCD, true);
+ dispc_enable_channel(channel, true);
rfbi.framedone_callback = callback;
rfbi.framedone_callback_data = data;
@@ -887,7 +887,7 @@ int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
dss_setup_partial_planes(dssdev, x, y, w, h, true);
- dispc_set_lcd_size(*w, *h);
+ dispc_set_lcd_size(dssdev->channel, *w, *h);
}
return 0;
@@ -899,7 +899,7 @@ int omap_rfbi_update(struct omap_dss_device *dssdev,
void (*callback)(void *), void *data)
{
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
- rfbi_transfer_area(w, h, callback, data);
+ rfbi_transfer_area(dssdev->channel, w, h, callback, data);
} else {
struct omap_overlay *ovl;
void __iomem *addr;
@@ -1018,11 +1018,12 @@ int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
goto err1;
}
- dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
+ dispc_set_lcd_display_type(dssdev->channel, OMAP_DSS_LCD_DISPLAY_TFT);
- dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
+ dispc_set_parallel_interface_mode(dssdev->channel,
+ OMAP_DSS_PARALLELMODE_RFBI);
- dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
+ dispc_set_tft_data_lines(dssdev->channel, dssdev->ctrl.pixel_size);
rfbi_configure(dssdev->phy.rfbi.channel,
dssdev->ctrl.pixel_size,
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index ee07a3c..a011be6 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -35,12 +35,14 @@ static struct {
struct regulator *vdds_sdi_reg;
} sdi;
-static void sdi_basic_init(void)
+static void sdi_basic_init(enum omap_channel channel)
+
{
- dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
+ dispc_set_parallel_interface_mode(channel,
+ OMAP_DSS_PARALLELMODE_BYPASS);
- dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
- dispc_set_tft_data_lines(24);
+ dispc_set_lcd_display_type(channel, OMAP_DSS_LCD_DISPLAY_TFT);
+ dispc_set_tft_data_lines(channel, 24);
dispc_lcd_enable_signal_polarity(1);
}
@@ -68,7 +70,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
if (!sdi.skip_init)
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
- sdi_basic_init();
+ sdi_basic_init(dssdev->channel);
/* 15.5.9.1.2 */
dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
@@ -102,7 +104,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
}
- dispc_set_lcd_timings(t);
+ dispc_set_lcd_timings(dssdev->channel, t);
r = dss_set_clock_div(&dss_cinfo);
if (r)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter
2010-11-08 12:24 ` [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter Archit Taneja
@ 2010-11-16 10:55 ` Tomi Valkeinen
2010-11-16 11:22 ` Taneja, Archit
0 siblings, 1 reply; 15+ messages in thread
From: Tomi Valkeinen @ 2010-11-16 10:55 UTC (permalink / raw)
To: ext Archit Taneja
Cc: linux-omap@vger.kernel.org, Sumit Semwal, Mukund Mittal, Samreen
Hi,
On Mon, 2010-11-08 at 13:24 +0100, ext Archit Taneja wrote:
> From: Sumit Semwal <sumit.semwal@ti.com>
>
> A new member 'channel' is introduced in omap_dss_device structure to determine
> which channel the panel uses. The dispc functions used by interface drivers
> (dsi, sdi etc) will use this member to differentiate between the 2 channels.
>
> The following dispc functions are changed to incorporate channel as an argument:
> -dispc_enable_fifohandcheck()
> -dispc_set_lcd_size()
> -dispc_set_parallel_interface_mode()
> -dispc_set_tft_data_lines()
> -dispc_set_lcd_display_type()
> -dispc_set_lcd_timings()
>
> The calls to these functions from the interface drivers have been changed to
> incorporate the new channel argument.
>
> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
> Signed-off-by: Mukund Mittal <mmittal@ti.com>
> Signed-off-by: Samreen <samreen@ti.com>
> ---
> arch/arm/plat-omap/include/plat/display.h | 1 +
> drivers/video/omap2/dss/dispc.c | 49 ++++++++++++++++-------------
> drivers/video/omap2/dss/dpi.c | 11 +++---
> drivers/video/omap2/dss/dsi.c | 13 ++++---
> drivers/video/omap2/dss/dss.h | 19 ++++++-----
> drivers/video/omap2/dss/rfbi.c | 19 ++++++-----
> drivers/video/omap2/dss/sdi.c | 14 +++++---
> 7 files changed, 70 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
> index 586944d..3e6eec1 100644
> --- a/arch/arm/plat-omap/include/plat/display.h
> +++ b/arch/arm/plat-omap/include/plat/display.h
> @@ -434,6 +434,7 @@ struct omap_dss_device {
> struct omap_overlay_manager *manager;
>
> enum omap_dss_display_state state;
> + enum omap_channel channel;
Isn't this the same as dssdev->manager->id?
Yes, this channel stuff is a bit confusing, even the enum "omap_channel"
is badly named (should at least have "dss" in it). But
omap_overlay_manager should represent the output pipe, so I don't think
there's need for channel field in dss_device.
I think in many places we could even pass omap_overlay_manager pointer
around, instead of omap_channel. However, for low level dispc functions
it's perhaps cleaner to pass the channel ID though.
Tomi
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter
2010-11-16 10:55 ` Tomi Valkeinen
@ 2010-11-16 11:22 ` Taneja, Archit
2010-11-16 13:32 ` Tomi Valkeinen
0 siblings, 1 reply; 15+ messages in thread
From: Taneja, Archit @ 2010-11-16 11:22 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund,
Nilofer, Samreen
Hi,
Tomi Valkeinen wrote:
> Hi,
>
[snip]
>> diff --git a/arch/arm/plat-omap/include/plat/display.h
>> b/arch/arm/plat-omap/include/plat/display.h
>> index 586944d..3e6eec1 100644
>> --- a/arch/arm/plat-omap/include/plat/display.h
>> +++ b/arch/arm/plat-omap/include/plat/display.h
>> @@ -434,6 +434,7 @@ struct omap_dss_device {
>> struct omap_overlay_manager *manager;
>>
>> enum omap_dss_display_state state;
>> + enum omap_channel channel;
>
> Isn't this the same as dssdev->manager->id?
>
> Yes, this channel stuff is a bit confusing, even the enum "omap_channel"
> is badly named (should at least have "dss" in it). But
> omap_overlay_manager should represent the output pipe, so I
> don't think there's need for channel field in dss_device.
The panel somehow needs to tell which manager it is connected to. We went with
with the way of declaring a new member 'channel' and setting that parameter up in the
board file.
The current way to relate the manager and device is done by checking the dssdev->type
in dss_recheck_connections() and then calling set_device()
This is not sufficient any more since two of the managers can support similar types of
displays.
So in the channel approach the following happens:
-mgr->id's are initialized at bootup.
-devices and managers are connected using 'channel'.
-mgr->id automatically becomes equal to channel.
Can we set something like dssdev->manager->id in the board file itself?
Archit
>
> I think in many places we could even pass
> omap_overlay_manager pointer around, instead of omap_channel.
> However, for low level dispc functions it's perhaps cleaner
> to pass the channel ID though.
>
> Tomi
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter
2010-11-16 11:22 ` Taneja, Archit
@ 2010-11-16 13:32 ` Tomi Valkeinen
2010-11-17 8:31 ` Taneja, Archit
0 siblings, 1 reply; 15+ messages in thread
From: Tomi Valkeinen @ 2010-11-16 13:32 UTC (permalink / raw)
To: ext Taneja, Archit
Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund,
Nilofer, Samreen
On Tue, 2010-11-16 at 12:22 +0100, ext Taneja, Archit wrote:
> Hi,
>
> Tomi Valkeinen wrote:
> > Hi,
> >
>
> [snip]
>
> >> diff --git a/arch/arm/plat-omap/include/plat/display.h
> >> b/arch/arm/plat-omap/include/plat/display.h
> >> index 586944d..3e6eec1 100644
> >> --- a/arch/arm/plat-omap/include/plat/display.h
> >> +++ b/arch/arm/plat-omap/include/plat/display.h
> >> @@ -434,6 +434,7 @@ struct omap_dss_device {
> >> struct omap_overlay_manager *manager;
> >>
> >> enum omap_dss_display_state state;
> >> + enum omap_channel channel;
> >
> > Isn't this the same as dssdev->manager->id?
> >
> > Yes, this channel stuff is a bit confusing, even the enum "omap_channel"
> > is badly named (should at least have "dss" in it). But
> > omap_overlay_manager should represent the output pipe, so I
> > don't think there's need for channel field in dss_device.
>
> The panel somehow needs to tell which manager it is connected to. We went with
> with the way of declaring a new member 'channel' and setting that parameter up in the
> board file.
>
> The current way to relate the manager and device is done by checking the dssdev->type
> in dss_recheck_connections() and then calling set_device()
>
> This is not sufficient any more since two of the managers can support similar types of
> displays.
>
> So in the channel approach the following happens:
>
> -mgr->id's are initialized at bootup.
> -devices and managers are connected using 'channel'.
> -mgr->id automatically becomes equal to channel.
>
> Can we set something like dssdev->manager->id in the board file itself?
Right, now I see.
The dss_recheck_connections() felt like a hack when I wrote it =).
Clearly we need some way to define in the board file which panel
connects to which manager.
Perhaps move the channel-field up, just below "enum omap_display_type
type". The lines in the beginning of omap_dss_device are things which
define the interface etc, and later there are miscallaneous dynamic
things. And this belongs to the former.
Now, if we have the channel defined in this way in the omap_dss_device,
I'm wondering if:
1) the manager pointer is needed at all, as the channel tells which
manager it is?
2) if we keep the manager pointer (as a helper shortcut), should the
code use generally use dssdev->channel or dssdev->manager->id?
3) having this channel field requires a change to every board file,
because the channel has to be defined?
And answering to myself, I guess the manager pointer is needed, because
DSS2 supports (at least in theory) multiple panels in the same interface
(not at the same time, of course). This means that we could have to
panels, with the same interface and channel, but only one would be in
use. So the one in use should have manager pointing to the correct
manager, and the other would have manager NULL.
And thus perhaps using dssdev->channel only for connecting the right
manager to right panel, and using dssdev->manager->id for other uses
would be the best? The values would of course be the same, but at least
we'd get a crash if somehow an unconnected display is being used for
configuration.
Does this make sense?
Tomi
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter
2010-11-16 13:32 ` Tomi Valkeinen
@ 2010-11-17 8:31 ` Taneja, Archit
2010-11-17 12:56 ` Taneja, Archit
0 siblings, 1 reply; 15+ messages in thread
From: Taneja, Archit @ 2010-11-17 8:31 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund,
Nilofer, Samreen
Hi,
Tomi Valkeinen wrote:
> On Tue, 2010-11-16 at 12:22 +0100, ext Taneja, Archit wrote:
>> Hi,
>>
>> Tomi Valkeinen wrote:
>>> Hi,
>>>
>>
>> [snip]
>>
>>>> diff --git a/arch/arm/plat-omap/include/plat/display.h
>>>> b/arch/arm/plat-omap/include/plat/display.h
>>>> index 586944d..3e6eec1 100644
>>>> --- a/arch/arm/plat-omap/include/plat/display.h
>>>> +++ b/arch/arm/plat-omap/include/plat/display.h
>>>> @@ -434,6 +434,7 @@ struct omap_dss_device {
>>>> struct omap_overlay_manager *manager;
>>>>
>>>> enum omap_dss_display_state state;
>>>> + enum omap_channel channel;
>>>
>>> Isn't this the same as dssdev->manager->id?
>>>
>>> Yes, this channel stuff is a bit confusing, even the enum "omap_channel"
>>> is badly named (should at least have "dss" in it). But
>>> omap_overlay_manager should represent the output pipe, so I don't
>>> think there's need for channel field in dss_device.
>>
>> The panel somehow needs to tell which manager it is connected to. We
>> went with with the way of declaring a new member 'channel' and setting
>> that parameter up in the board file.
>>
>> The current way to relate the manager and device is done by checking
>> the dssdev->type in dss_recheck_connections() and then calling set_device()
>>
>> This is not sufficient any more since two of the managers can support
>> similar types of displays.
>>
>> So in the channel approach the following happens:
>>
>> -mgr->id's are initialized at bootup.
>> -devices and managers are connected using 'channel'.
>> -mgr->id automatically becomes equal to channel.
>>
>> Can we set something like dssdev->manager->id in the board file itself?
>
> Right, now I see.
>
> The dss_recheck_connections() felt like a hack when I wrote it =).
> Clearly we need some way to define in the board file which
> panel connects to which manager.
>
It wasn't needed probably for OMAP3 since all non-venc panels connect
to LCD and venc to VENC type.
Now that I think of it, what channel would we mention if the panel is
used in dsi l4 update mode or dma mode? It should have no manager at all.
> Perhaps move the channel-field up, just below "enum
> omap_display_type type". The lines in the beginning of
> omap_dss_device are things which define the interface etc,
> and later there are miscallaneous dynamic things. And this belongs to the
> former.
>
> Now, if we have the channel defined in this way in the
> omap_dss_device, I'm wondering if:
> 1) the manager pointer is needed at all, as the channel tells which manager
> it is? 2) if we keep the manager pointer (as a helper shortcut),
> should the code use generally use dssdev->channel or dssdev->manager->id?
I think manager->id makes more sense considering your logic below.
> 3) having this channel field requires a change to every board
> file, because the channel has to be defined?
>
Yes, that is something that has to be done for all 'DIGIT'
panels across all boards.
> And answering to myself, I guess the manager pointer is
> needed, because
> DSS2 supports (at least in theory) multiple panels in the
> same interface (not at the same time, of course). This means
> that we could have to panels, with the same interface and
> channel, but only one would be in use. So the one in use
> should have manager pointing to the correct manager, and the
> other would have manager NULL.
>
Yes, passing dssdev->channel would make things worse if 2 panels
are connected to same interface.
> And thus perhaps using dssdev->channel only for connecting
> the right manager to right panel, and using
> dssdev->manager->id for other uses would be the best? The
> values would of course be the same, but at least we'd get a
> crash if somehow an unconnected display is being used for configuration.
>
Even in the current kernel on 3430sdp, the board file adds sharp_ls, venc and generic panels
If I boot up with venc as default display, mgr0 has dvi as its display and mgr1 has tv.
So if I try to enable sharp_ls panel I get a crash when we first try to access dssdev->manager
in dpi_display_enable(). We should have a way to prevent enabling a panel if it isn't connected
to a manager. We should also have a way to allow a panel to have no channel at all (something like
OMAP_DSS_CHANNEL_NONE) if we are using something like dsi l4 update.
I won't add this extra channel now though, we need to think of a better way later.
> Does this make sense?
Yes, it does, I'll make these changes, and more if you can think of any.
Archit
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter
2010-11-17 8:31 ` Taneja, Archit
@ 2010-11-17 12:56 ` Taneja, Archit
0 siblings, 0 replies; 15+ messages in thread
From: Taneja, Archit @ 2010-11-17 12:56 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: linux-omap@vger.kernel.org, Semwal, Sumit, Mittal, Mukund,
Nilofer, Samreen
Hi,
Tomi Valkeinen wrote:
> Hi,
>
> Tomi Valkeinen wrote:
>> On Tue, 2010-11-16 at 12:22 +0100, ext Taneja, Archit wrote:
>>> Hi,
>>>
>>> Tomi Valkeinen wrote:
>>>> Hi,
>>>>
>>>
>>> [snip]
>>>
>>>>> diff --git a/arch/arm/plat-omap/include/plat/display.h
>>>>> b/arch/arm/plat-omap/include/plat/display.h
>>>>> index 586944d..3e6eec1 100644
>>>>> --- a/arch/arm/plat-omap/include/plat/display.h
>>>>> +++ b/arch/arm/plat-omap/include/plat/display.h
>>>>> @@ -434,6 +434,7 @@ struct omap_dss_device {
>>>>> struct omap_overlay_manager *manager;
>>>>>
>>>>> enum omap_dss_display_state state;
>>>>> + enum omap_channel channel;
>>>>
>>>> Isn't this the same as dssdev->manager->id?
>>>>
>>>> Yes, this channel stuff is a bit confusing, even the enum "omap_channel"
>>>> is badly named (should at least have "dss" in it). But
>>>> omap_overlay_manager should represent the output pipe, so I don't
>>>> think there's need for channel field in dss_device.
>>>
>>> The panel somehow needs to tell which manager it is connected to. We
>>> went with with the way of declaring a new member 'channel' and
>>> setting that parameter up in the board file.
>>>
>>> The current way to relate the manager and device is done by checking
>>> the dssdev->type in dss_recheck_connections() and then calling set_device()
>>>
>>> This is not sufficient any more since two of the managers can support
>>> similar types of displays.
>>>
>>> So in the channel approach the following happens:
>>>
>>> -mgr->id's are initialized at bootup.
>>> -devices and managers are connected using 'channel'.
>>> -mgr->id automatically becomes equal to channel.
>>>
>>> Can we set something like dssdev->manager->id in the board file itself?
>>
>> Right, now I see.
>>
>> The dss_recheck_connections() felt like a hack when I wrote it =).
>> Clearly we need some way to define in the board file which panel connects to
>> which manager.
>>
>
> It wasn't needed probably for OMAP3 since all non-venc panels
> connect to LCD and venc to VENC type.
>
> Now that I think of it, what channel would we mention if the
> panel is used in dsi l4 update mode or dma mode? It should
> have no manager at all.
>
>> Perhaps move the channel-field up, just below "enum omap_display_type
>> type". The lines in the beginning of omap_dss_device are things which
>> define the interface etc, and later there are miscallaneous dynamic
>> things. And this belongs to the former.
>>
>> Now, if we have the channel defined in this way in the
>> omap_dss_device, I'm wondering if:
>> 1) the manager pointer is needed at all, as the channel tells which
>> manager it is? 2) if we keep the manager pointer (as a helper
>> shortcut), should the code use generally use
> dssdev->channel or dssdev->manager->id?
>
> I think manager->id makes more sense considering your logic below.
>
>> 3) having this channel field requires a change to every board file,
>> because the channel has to be defined?
>>
>
> Yes, that is something that has to be done for all 'DIGIT'
> panels across all boards.
>
>> And answering to myself, I guess the manager pointer is needed, because
>> DSS2 supports (at least in theory) multiple panels in the same
>> interface (not at the same time, of course). This means that we could
>> have to panels, with the same interface and channel, but only one
>> would be in use. So the one in use should have manager pointing to the
>> correct manager, and the other would have manager NULL.
>>
>
> Yes, passing dssdev->channel would make things worse if 2
> panels are connected to same interface.
>
>> And thus perhaps using dssdev->channel only for connecting the right
>> manager to right panel, and using
>> dssdev->manager->id for other uses would be the best? The
>> values would of course be the same, but at least we'd get a crash if
>> somehow an unconnected display is being used for configuration.
>>
>
> Even in the current kernel on 3430sdp, the board file adds
> sharp_ls, venc and generic panels If I boot up with venc as
> default display, mgr0 has dvi as its display and mgr1 has tv.
> So if I try to enable sharp_ls panel I get a crash when we
> first try to access dssdev->manager in dpi_display_enable().
> We should have a way to prevent enabling a panel if it isn't
> connected to a manager. We should also have a way to allow a
> panel to have no channel at all (something like
> OMAP_DSS_CHANNEL_NONE) if we are using something like dsi l4 update.
>
> I won't add this extra channel now though, we need to think
> of a better way later.
>
Also, do you think when a display unsets a manager and sets a new manager
the channel should be changed? Or should it purely be a one time thing
for choosing the correct manager and not use it anywhere else?
Thanks,
Archit
>> Does this make sense?
>
> Yes, it does, I'll make these changes, and more if you can
> think of any.
>
> Archit--
> To unsubscribe from this list: send the line "unsubscribe
> linux-omap" in the body of a message to
> majordomo@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v4 4/7] OMAP: DSS2: Change remaining Dispc functions for new 'channel' argument
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
` (2 preceding siblings ...)
2010-11-08 12:24 ` [PATCH v4 3/7] OMAP: DSS2: Introduce omap_channel as a omap_dss_device parameter Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
2010-11-08 12:24 ` [PATCH v4 5/7] OMAP: DSS2: LCD2 Channel Changes for DISPC Archit Taneja
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Samreen
From: Sumit Semwal <sumit.semwal@ti.com>
The following dispc functions are changed to incorporate channel as an argument:
-dispc_lclk_rate()
-dispc_pclk_rate()
-dispc_set_pol_freq()
-dispc_set_clock_div()
-dispc_get_clock_div()
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
drivers/video/omap2/dss/dispc.c | 62 ++++++++++++++++++++++-----------------
drivers/video/omap2/dss/dpi.c | 22 +++++++------
drivers/video/omap2/dss/dsi.c | 8 ++--
drivers/video/omap2/dss/dss.h | 13 +++++---
drivers/video/omap2/dss/sdi.c | 8 ++--
5 files changed, 63 insertions(+), 50 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 2ea1a7a..b9be4fd 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1442,12 +1442,13 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
}
}
-static unsigned long calc_fclk_five_taps(u16 width, u16 height,
- u16 out_width, u16 out_height, enum omap_color_mode color_mode)
+static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
+ u16 height, u16 out_width, u16 out_height,
+ enum omap_color_mode color_mode)
{
u32 fclk = 0;
/* FIXME venc pclk? */
- u64 tmp, pclk = dispc_pclk_rate();
+ u64 tmp, pclk = dispc_pclk_rate(channel);
if (height > out_height) {
/* FIXME get real display PPL */
@@ -1479,8 +1480,8 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
return fclk;
}
-static unsigned long calc_fclk(u16 width, u16 height,
- u16 out_width, u16 out_height)
+static unsigned long calc_fclk(enum omap_channel channel, u16 width,
+ u16 height, u16 out_width, u16 out_height)
{
unsigned int hf, vf;
@@ -1504,7 +1505,7 @@ static unsigned long calc_fclk(u16 width, u16 height,
vf = 1;
/* FIXME venc pclk? */
- return dispc_pclk_rate() * vf * hf;
+ return dispc_pclk_rate(channel) * vf * hf;
}
void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
@@ -1623,7 +1624,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
five_taps = height > out_height * 2;
if (!five_taps) {
- fclk = calc_fclk(width, height,
+ fclk = calc_fclk(OMAP_DSS_CHANNEL_LCD, width, height,
out_width, out_height);
/* Try 5-tap filter if 3-tap fclk is too high */
@@ -1638,8 +1639,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
}
if (five_taps)
- fclk = calc_fclk_five_taps(width, height,
- out_width, out_height, color_mode);
+ fclk = calc_fclk_five_taps(OMAP_DSS_CHANNEL_LCD, width,
+ height, out_width, out_height,
+ color_mode);
DSSDBG("required fclk rate = %lu Hz\n", fclk);
DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
@@ -2200,13 +2202,14 @@ void dispc_set_lcd_timings(enum omap_channel channel,
DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
}
-static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
+static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
+ u16 pck_div)
{
BUG_ON(lck_div < 1);
BUG_ON(pck_div < 2);
enable_clocks(1);
- dispc_write_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD),
+ dispc_write_reg(DISPC_DIVISOR(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
enable_clocks(0);
}
@@ -2234,13 +2237,13 @@ unsigned long dispc_fclk_rate(void)
return r;
}
-unsigned long dispc_lclk_rate(void)
+unsigned long dispc_lclk_rate(enum omap_channel channel)
{
int lcd;
unsigned long r;
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
+ l = dispc_read_reg(DISPC_DIVISOR(channel));
lcd = FLD_GET(l, 23, 16);
@@ -2249,13 +2252,13 @@ unsigned long dispc_lclk_rate(void)
return r / lcd;
}
-unsigned long dispc_pclk_rate(void)
+unsigned long dispc_pclk_rate(enum omap_channel channel)
{
int lcd, pcd;
unsigned long r;
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
+ l = dispc_read_reg(DISPC_DIVISOR(channel));
lcd = FLD_GET(l, 23, 16);
pcd = FLD_GET(l, 7, 0);
@@ -2280,8 +2283,10 @@ void dispc_dump_clocks(struct seq_file *s)
"dss1_alwon_fclk" : "dsi1_pll_fclk");
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
- seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
- seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
+ seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+ dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
+ seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+ dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
enable_clocks(0);
}
@@ -2473,8 +2478,8 @@ void dispc_dump_regs(struct seq_file *s)
#undef DUMPREG
}
-static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
- bool ihs, bool ivs, u8 acbi, u8 acb)
+static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
+ bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
{
u32 l = 0;
@@ -2491,13 +2496,14 @@ static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
l |= FLD_VAL(acb, 7, 0);
enable_clocks(1);
- dispc_write_reg(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD), l);
+ dispc_write_reg(DISPC_POL_FREQ(channel), l);
enable_clocks(0);
}
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
+void dispc_set_pol_freq(enum omap_channel channel,
+ enum omap_panel_config config, u8 acbi, u8 acb)
{
- _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
+ _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
(config & OMAP_DSS_LCD_RF) != 0,
(config & OMAP_DSS_LCD_IEO) != 0,
(config & OMAP_DSS_LCD_IPC) != 0,
@@ -2566,24 +2572,26 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
return 0;
}
-int dispc_set_clock_div(struct dispc_clock_info *cinfo)
+int dispc_set_clock_div(enum omap_channel channel,
+ struct dispc_clock_info *cinfo)
{
DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
- dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
+ dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
return 0;
}
-int dispc_get_clock_div(struct dispc_clock_info *cinfo)
+int dispc_get_clock_div(enum omap_channel channel,
+ struct dispc_clock_info *cinfo)
{
unsigned long fck;
fck = dispc_fclk_rate();
- cinfo->lck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 23, 16);
- cinfo->pck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 7, 0);
+ cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
+ cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
cinfo->lck = fck / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 51040dc..8f4f500 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -40,8 +40,9 @@ static struct {
} dpi;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
- unsigned long *fck, int *lck_div, int *pck_div)
+static int dpi_set_dsi_clk(enum omap_channel channel, bool is_tft,
+ unsigned long pck_req, unsigned long *fck, int *lck_div,
+ int *pck_div)
{
struct dsi_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
@@ -58,7 +59,7 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
- r = dispc_set_clock_div(&dispc_cinfo);
+ r = dispc_set_clock_div(channel, &dispc_cinfo);
if (r)
return r;
@@ -69,8 +70,9 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
return 0;
}
#else
-static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
- unsigned long *fck, int *lck_div, int *pck_div)
+static int dpi_set_dispc_clk(enum omap_channel channel, bool is_tft,
+ unsigned long pck_req, unsigned long *fck, int *lck_div,
+ int *pck_div)
{
struct dss_clock_info dss_cinfo;
struct dispc_clock_info dispc_cinfo;
@@ -84,7 +86,7 @@ static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
if (r)
return r;
- r = dispc_set_clock_div(&dispc_cinfo);
+ r = dispc_set_clock_div(channel, &dispc_cinfo);
if (r)
return r;
@@ -107,16 +109,16 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
- dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
- dssdev->panel.acb);
+ dispc_set_pol_freq(dssdev->channel, dssdev->panel.config,
+ dssdev->panel.acbi, dssdev->panel.acb);
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
+ r = dpi_set_dsi_clk(dssdev->channel, is_tft, t->pixel_clock * 1000,
&fck, &lck_div, &pck_div);
#else
- r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
+ r = dpi_set_dispc_clk(dssdev->channel, is_tft, t->pixel_clock * 1000,
&fck, &lck_div, &pck_div);
#endif
if (r)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index a4c031e..932321d 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -812,7 +812,7 @@ static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
* with DSS2_FCK source also */
cinfo->highfreq = 0;
} else {
- cinfo->clkin = dispc_pclk_rate();
+ cinfo->clkin = dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD);
if (cinfo->clkin < 32000000)
cinfo->highfreq = 0;
@@ -1206,8 +1206,8 @@ void dsi_dump_clocks(struct seq_file *s)
seq_printf(s, "VP_CLK\t\t%lu\n"
"VP_PCLK\t\t%lu\n",
- dispc_lclk_rate(),
- dispc_pclk_rate());
+ dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
+ dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
enable_clocks(0);
}
@@ -3020,7 +3020,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
return r;
}
- r = dispc_set_clock_div(&dispc_cinfo);
+ r = dispc_set_clock_div(dssdev->channel, &dispc_cinfo);
if (r) {
DSSERR("Failed to set dispc clocks\n");
return r;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 68f7c42..599df58 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -393,15 +393,18 @@ bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
void dispc_set_lcd_timings(enum omap_channel channel,
struct omap_video_timings *timings);
unsigned long dispc_fclk_rate(void);
-unsigned long dispc_lclk_rate(void);
-unsigned long dispc_pclk_rate(void);
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb);
+unsigned long dispc_lclk_rate(enum omap_channel channel);
+unsigned long dispc_pclk_rate(enum omap_channel channel);
+void dispc_set_pol_freq(enum omap_channel channel,
+ enum omap_panel_config config, u8 acbi, u8 acb);
void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
struct dispc_clock_info *cinfo);
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
struct dispc_clock_info *cinfo);
-int dispc_set_clock_div(struct dispc_clock_info *cinfo);
-int dispc_get_clock_div(struct dispc_clock_info *cinfo);
+int dispc_set_clock_div(enum omap_channel channel,
+ struct dispc_clock_info *cinfo);
+int dispc_get_clock_div(enum omap_channel channel,
+ struct dispc_clock_info *cinfo);
/* VENC */
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index a011be6..82d763a 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -75,15 +75,15 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
/* 15.5.9.1.2 */
dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
- dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
- dssdev->panel.acb);
+ dispc_set_pol_freq(dssdev->channel, dssdev->panel.config,
+ dssdev->panel.acbi, dssdev->panel.acb);
if (!sdi.skip_init) {
r = dss_calc_clock_div(1, t->pixel_clock * 1000,
&dss_cinfo, &dispc_cinfo);
} else {
r = dss_get_clock_div(&dss_cinfo);
- r = dispc_get_clock_div(&dispc_cinfo);
+ r = dispc_get_clock_div(dssdev->channel, &dispc_cinfo);
}
if (r)
@@ -110,7 +110,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
if (r)
goto err2;
- r = dispc_set_clock_div(&dispc_cinfo);
+ r = dispc_set_clock_div(dssdev->channel, &dispc_cinfo);
if (r)
goto err2;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v4 5/7] OMAP: DSS2: LCD2 Channel Changes for DISPC
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
` (3 preceding siblings ...)
2010-11-08 12:24 ` [PATCH v4 4/7] OMAP: DSS2: Change remaining Dispc functions for new 'channel' argument Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
2010-11-08 12:24 ` [PATCH v4 6/7] OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 Archit Taneja
2010-11-08 12:24 ` [PATCH v4 7/7] OMAP: DSS2: Add new Overlay Manager Archit Taneja
6 siblings, 0 replies; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Samreen
From: Sumit Semwal <sumit.semwal@ti.com>
Modify DISPC functions to work with LCD2 as the DISPC Channel.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
arch/arm/plat-omap/include/plat/display.h | 4 +
drivers/video/omap2/dss/dispc.c | 216 +++++++++++++++++++++++++----
2 files changed, 191 insertions(+), 29 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 3e6eec1..03d7893 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -42,6 +42,10 @@
#define DISPC_IRQ_SYNC_LOST (1 << 14)
#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
#define DISPC_IRQ_WAKEUP (1 << 16)
+#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
+#define DISPC_IRQ_VSYNC2 (1 << 18)
+#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
+#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
struct omap_dss_device;
struct omap_overlay_manager;
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index b9be4fd..967fa87 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -232,6 +232,17 @@ void dispc_save_context(void)
SR(GLOBAL_ALPHA);
SR(SIZE_DIG);
SR(SIZE_LCD(0));
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ SR(CONTROL(2));
+ SR(DEFAULT_COLOR(2));
+ SR(TRANS_COLOR(2));
+ SR(SIZE_LCD(2));
+ SR(TIMING_H(2));
+ SR(TIMING_V(2));
+ SR(POL_FREQ(2));
+ SR(DIVISOR(2));
+ SR(CONFIG(2));
+ }
SR(GFX_BA0);
SR(GFX_BA1);
@@ -251,6 +262,15 @@ void dispc_save_context(void)
SR(CPR_COEF_R(0));
SR(CPR_COEF_G(0));
SR(CPR_COEF_B(0));
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ SR(CPR_COEF_B(2));
+ SR(CPR_COEF_G(2));
+ SR(CPR_COEF_R(2));
+
+ SR(DATA_CYCLE1(2));
+ SR(DATA_CYCLE2(2));
+ SR(DATA_CYCLE3(2));
+ }
SR(GFX_PRELOAD);
@@ -371,6 +391,16 @@ void dispc_restore_context(void)
RR(GLOBAL_ALPHA);
RR(SIZE_DIG);
RR(SIZE_LCD(0));
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ RR(DEFAULT_COLOR(2));
+ RR(TRANS_COLOR(2));
+ RR(SIZE_LCD(2));
+ RR(TIMING_H(2));
+ RR(TIMING_V(2));
+ RR(POL_FREQ(2));
+ RR(DIVISOR(2));
+ RR(CONFIG(2));
+ }
RR(GFX_BA0);
RR(GFX_BA1);
@@ -390,6 +420,15 @@ void dispc_restore_context(void)
RR(CPR_COEF_R(0));
RR(CPR_COEF_G(0));
RR(CPR_COEF_B(0));
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ RR(DATA_CYCLE1(2));
+ RR(DATA_CYCLE2(2));
+ RR(DATA_CYCLE3(2));
+
+ RR(CPR_COEF_B(2));
+ RR(CPR_COEF_G(2));
+ RR(CPR_COEF_R(2));
+ }
RR(GFX_PRELOAD);
@@ -493,6 +532,8 @@ void dispc_restore_context(void)
/* enable last, because LCD & DIGIT enable are here */
RR(CONTROL(0));
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ RR(CONTROL(2));
/* clear spurious SYNC_LOST_DIGIT interrupts */
dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
@@ -519,7 +560,8 @@ bool dispc_go_busy(enum omap_channel channel)
{
int bit;
- if (channel == OMAP_DSS_CHANNEL_LCD)
+ if (channel == OMAP_DSS_CHANNEL_LCD ||
+ channel == OMAP_DSS_CHANNEL_LCD2)
bit = 5; /* GOLCD */
else
bit = 6; /* GODIGIT */
@@ -533,7 +575,8 @@ void dispc_go(enum omap_channel channel)
enable_clocks(1);
- if (channel == OMAP_DSS_CHANNEL_LCD)
+ if (channel == OMAP_DSS_CHANNEL_LCD ||
+ channel == OMAP_DSS_CHANNEL_LCD2)
bit = 0; /* LCDENABLE */
else
bit = 1; /* DIGITALENABLE */
@@ -542,7 +585,8 @@ void dispc_go(enum omap_channel channel)
if (REG_GET(DISPC_CONTROL(channel), bit, bit) == 0)
goto end;
- if (channel == OMAP_DSS_CHANNEL_LCD)
+ if (channel == OMAP_DSS_CHANNEL_LCD ||
+ channel == OMAP_DSS_CHANNEL_LCD2)
bit = 5; /* GOLCD */
else
bit = 6; /* GODIGIT */
@@ -552,7 +596,8 @@ void dispc_go(enum omap_channel channel)
goto end;
}
- DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
+ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
+ (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
REG_FLD_MOD(DISPC_CONTROL(channel), 1, bit, bit);
end:
@@ -867,6 +912,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
{
int shift;
u32 val;
+ int chan = 0, chan2 = 0;
switch (plane) {
case OMAP_DSS_GFX:
@@ -882,7 +928,29 @@ static void _dispc_set_channel_out(enum omap_plane plane,
}
val = dispc_read_reg(dispc_reg_att[plane]);
- val = FLD_MOD(val, channel, shift, shift);
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ chan = 0;
+ chan2 = 0;
+ break;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ chan = 1;
+ chan2 = 0;
+ break;
+ case OMAP_DSS_CHANNEL_LCD2:
+ chan = 0;
+ chan2 = 1;
+ break;
+ default:
+ BUG();
+ }
+
+ val = FLD_MOD(val, chan, shift, shift);
+ val = FLD_MOD(val, chan2, 31, 30);
+ } else {
+ val = FLD_MOD(val, channel, shift, shift);
+ }
dispc_write_reg(dispc_reg_att[plane], val);
}
@@ -1729,36 +1797,39 @@ static void dispc_disable_isr(void *data, u32 mask)
complete(compl);
}
-static void _enable_lcd_out(bool enable)
+static void _enable_lcd_out(enum omap_channel channel, bool enable)
{
- REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), enable ? 1 : 0, 0, 0);
+ REG_FLD_MOD(DISPC_CONTROL(channel), enable ? 1 : 0, 0, 0);
}
-static void dispc_enable_lcd_out(bool enable)
+static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
{
struct completion frame_done_completion;
bool is_on;
int r;
+ u32 irq;
enable_clocks(1);
/* When we disable LCD output, we need to wait until frame is done.
* Otherwise the DSS is still working, and turning off the clocks
* prevents DSS from going to OFF mode */
- is_on = REG_GET(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD), 0, 0);
+ is_on = REG_GET(DISPC_CONTROL(channel), 0, 0);
+
+ irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
+ DISPC_IRQ_FRAMEDONE;
if (!enable && is_on) {
init_completion(&frame_done_completion);
r = omap_dispc_register_isr(dispc_disable_isr,
- &frame_done_completion,
- DISPC_IRQ_FRAMEDONE);
+ &frame_done_completion, irq);
if (r)
DSSERR("failed to register FRAMEDONE isr\n");
}
- _enable_lcd_out(enable);
+ _enable_lcd_out(channel, enable);
if (!enable && is_on) {
if (!wait_for_completion_timeout(&frame_done_completion,
@@ -1766,8 +1837,7 @@ static void dispc_enable_lcd_out(bool enable)
DSSERR("timeout waiting for FRAME DONE\n");
r = omap_dispc_unregister_isr(dispc_disable_isr,
- &frame_done_completion,
- DISPC_IRQ_FRAMEDONE);
+ &frame_done_completion, irq);
if (r)
DSSERR("failed to unregister FRAMEDONE isr\n");
@@ -1838,6 +1908,8 @@ static void dispc_enable_digit_out(bool enable)
unsigned long flags;
spin_lock_irqsave(&dispc.irq_lock, flags);
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
_omap_dispc_set_irqs();
spin_unlock_irqrestore(&dispc.irq_lock, flags);
@@ -1848,7 +1920,8 @@ static void dispc_enable_digit_out(bool enable)
bool dispc_is_channel_enabled(enum omap_channel channel)
{
- if (channel == OMAP_DSS_CHANNEL_LCD)
+ if (channel == OMAP_DSS_CHANNEL_LCD ||
+ channel == OMAP_DSS_CHANNEL_LCD2)
return !!REG_GET(DISPC_CONTROL(channel), 0, 0);
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
return !!REG_GET(DISPC_CONTROL(channel), 1, 1);
@@ -1858,8 +1931,9 @@ bool dispc_is_channel_enabled(enum omap_channel channel)
void dispc_enable_channel(enum omap_channel channel, bool enable)
{
- if (channel == OMAP_DSS_CHANNEL_LCD)
- dispc_enable_lcd_out(enable);
+ if (channel == OMAP_DSS_CHANNEL_LCD ||
+ channel == OMAP_DSS_CHANNEL_LCD2)
+ dispc_enable_lcd_out(channel, enable);
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
dispc_enable_digit_out(enable);
else
@@ -1942,7 +2016,8 @@ u32 dispc_get_default_color(enum omap_channel channel)
u32 l;
BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
- channel != OMAP_DSS_CHANNEL_LCD);
+ channel != OMAP_DSS_CHANNEL_LCD &&
+ channel != OMAP_DSS_CHANNEL_LCD2);
enable_clocks(1);
l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
@@ -1956,7 +2031,7 @@ void dispc_set_trans_key(enum omap_channel ch,
u32 trans_key)
{
enable_clocks(1);
- if (ch == OMAP_DSS_CHANNEL_LCD)
+ if (ch == OMAP_DSS_CHANNEL_LCD || ch == OMAP_DSS_CHANNEL_LCD2)
REG_FLD_MOD(DISPC_CONFIG(ch), type, 11, 11);
else /* OMAP_DSS_CHANNEL_DIGIT */
REG_FLD_MOD(DISPC_CONFIG(ch), type, 13, 13);
@@ -1971,7 +2046,7 @@ void dispc_get_trans_key(enum omap_channel ch,
{
enable_clocks(1);
if (type) {
- if (ch == OMAP_DSS_CHANNEL_LCD)
+ if (ch == OMAP_DSS_CHANNEL_LCD || ch == OMAP_DSS_CHANNEL_LCD2)
*type = REG_GET(DISPC_CONFIG(ch), 11, 11);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
*type = REG_GET(DISPC_CONFIG(ch), 13, 13);
@@ -1987,7 +2062,7 @@ void dispc_get_trans_key(enum omap_channel ch,
void dispc_enable_trans_key(enum omap_channel ch, bool enable)
{
enable_clocks(1);
- if (ch == OMAP_DSS_CHANNEL_LCD)
+ if (ch == OMAP_DSS_CHANNEL_LCD || ch == OMAP_DSS_CHANNEL_LCD2)
REG_FLD_MOD(DISPC_CONFIG(ch), enable, 10, 10);
else /* OMAP_DSS_CHANNEL_DIGIT */
REG_FLD_MOD(DISPC_CONFIG(ch), enable, 12, 12);
@@ -1999,7 +2074,7 @@ void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
return;
enable_clocks(1);
- if (ch == OMAP_DSS_CHANNEL_LCD)
+ if (ch == OMAP_DSS_CHANNEL_LCD || ch == OMAP_DSS_CHANNEL_LCD2)
REG_FLD_MOD(DISPC_CONFIG(ch), enable, 18, 18);
else /* OMAP_DSS_CHANNEL_DIGIT */
REG_FLD_MOD(DISPC_CONFIG(ch), enable, 19, 19);
@@ -2013,7 +2088,7 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
return false;
enable_clocks(1);
- if (ch == OMAP_DSS_CHANNEL_LCD)
+ if (ch == OMAP_DSS_CHANNEL_LCD || ch == OMAP_DSS_CHANNEL_LCD2)
enabled = REG_GET(DISPC_CONFIG(ch), 18, 18);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
enabled = REG_GET(DISPC_CONFIG(ch), 19, 19);
@@ -2030,7 +2105,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
bool enabled;
enable_clocks(1);
- if (ch == OMAP_DSS_CHANNEL_LCD)
+ if (ch == OMAP_DSS_CHANNEL_LCD || ch == OMAP_DSS_CHANNEL_LCD2)
enabled = REG_GET(DISPC_CONFIG(ch), 10, 10);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
enabled = REG_GET(DISPC_CONFIG(ch), 12, 12);
@@ -2193,7 +2268,8 @@ void dispc_set_lcd_timings(enum omap_channel channel,
ht = (timings->pixel_clock * 1000) / xtot;
vt = (timings->pixel_clock * 1000) / xtot / ytot;
- DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
+ DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
+ timings->y_res);
DSSDBG("pck %u\n", timings->pixel_clock);
DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
timings->hsw, timings->hfp, timings->hbp,
@@ -2214,10 +2290,11 @@ static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
enable_clocks(0);
}
-static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
+static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
+ int *pck_div)
{
u32 l;
- l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
+ l = dispc_read_reg(DISPC_DIVISOR(channel));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
}
@@ -2274,8 +2351,6 @@ void dispc_dump_clocks(struct seq_file *s)
enable_clocks(1);
- dispc_get_lcd_divisor(&lcd, &pcd);
-
seq_printf(s, "- DISPC -\n");
seq_printf(s, "dispc fclk source = %s\n",
@@ -2283,11 +2358,25 @@ void dispc_dump_clocks(struct seq_file *s)
"dss1_alwon_fclk" : "dsi1_pll_fclk");
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
+
+ seq_printf(s, "- LCD1 -\n");
+
+ dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
+
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ seq_printf(s, "- LCD2 -\n");
+ dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
+
+ seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+ dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
+ seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+ dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
+ }
enable_clocks(0);
}
@@ -2329,6 +2418,12 @@ void dispc_dump_irqs(struct seq_file *s)
PIS(SYNC_LOST);
PIS(SYNC_LOST_DIGIT);
PIS(WAKEUP);
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ PIS(FRAMEDONE2);
+ PIS(VSYNC2);
+ PIS(ACBIAS_COUNT_STAT2);
+ PIS(SYNC_LOST2);
+ }
#undef PIS
}
#endif
@@ -2360,6 +2455,17 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_GLOBAL_ALPHA);
DUMPREG(DISPC_SIZE_DIG);
DUMPREG(DISPC_SIZE_LCD(0));
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ DUMPREG(DISPC_CONTROL(2));
+ DUMPREG(DISPC_CONFIG(2));
+ DUMPREG(DISPC_DEFAULT_COLOR(2));
+ DUMPREG(DISPC_TRANS_COLOR(2));
+ DUMPREG(DISPC_TIMING_H(2));
+ DUMPREG(DISPC_TIMING_V(2));
+ DUMPREG(DISPC_POL_FREQ(2));
+ DUMPREG(DISPC_DIVISOR(2));
+ DUMPREG(DISPC_SIZE_LCD(2));
+ }
DUMPREG(DISPC_GFX_BA0);
DUMPREG(DISPC_GFX_BA1);
@@ -2380,6 +2486,15 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_CPR_COEF_R(0));
DUMPREG(DISPC_CPR_COEF_G(0));
DUMPREG(DISPC_CPR_COEF_B(0));
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ DUMPREG(DISPC_DATA_CYCLE1(2));
+ DUMPREG(DISPC_DATA_CYCLE2(2));
+ DUMPREG(DISPC_DATA_CYCLE3(2));
+
+ DUMPREG(DISPC_CPR_COEF_R(2));
+ DUMPREG(DISPC_CPR_COEF_G(2));
+ DUMPREG(DISPC_CPR_COEF_B(2));
+ }
DUMPREG(DISPC_GFX_PRELOAD);
@@ -2731,6 +2846,8 @@ static void print_irq_status(u32 status)
PIS(VID2_FIFO_UNDERFLOW);
PIS(SYNC_LOST);
PIS(SYNC_LOST_DIGIT);
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ PIS(SYNC_LOST2);
#undef PIS
printk("\n");
@@ -2949,6 +3066,45 @@ static void dispc_error_worker(struct work_struct *work)
}
}
+ if (errors & DISPC_IRQ_SYNC_LOST2) {
+ struct omap_overlay_manager *manager = NULL;
+ bool enable = false;
+
+ DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
+
+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
+ struct omap_overlay_manager *mgr;
+ mgr = omap_dss_get_overlay_manager(i);
+
+ if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
+ manager = mgr;
+ enable = mgr->device->state ==
+ OMAP_DSS_DISPLAY_ACTIVE;
+ mgr->device->driver->disable(mgr->device);
+ break;
+ }
+ }
+
+ if (manager) {
+ struct omap_dss_device *dssdev = manager->device;
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+ struct omap_overlay *ovl;
+ ovl = omap_dss_get_overlay(i);
+
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+ continue;
+
+ if (ovl->id != 0 && ovl->manager == manager)
+ dispc_enable_plane(ovl->id, 0);
+ }
+
+ dispc_go(manager->id);
+ mdelay(50);
+ if (enable)
+ dssdev->driver->enable(dssdev);
+ }
+ }
+
if (errors & DISPC_IRQ_OCP_ERR) {
DSSERR("OCP_ERR\n");
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
@@ -3056,6 +3212,8 @@ static void _omap_dispc_initialize_irq(void)
memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
/* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
* so clear it */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v4 6/7] OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
` (4 preceding siblings ...)
2010-11-08 12:24 ` [PATCH v4 5/7] OMAP: DSS2: LCD2 Channel Changes for DISPC Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
2010-11-08 12:24 ` [PATCH v4 7/7] OMAP: DSS2: Add new Overlay Manager Archit Taneja
6 siblings, 0 replies; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED
have been removed from OMAP4, use dss_features to handle them correctly.
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 12 +++++++++++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 967fa87..e34c129 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1942,6 +1942,9 @@ void dispc_enable_channel(enum omap_channel channel, bool enable)
void dispc_lcd_enable_signal_polarity(bool act_high)
{
+ if (!dss_has_feature(FEAT_LCDENABLEPOL))
+ return;
+
enable_clocks(1);
REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD),
act_high ? 1 : 0, 29, 29);
@@ -1950,6 +1953,9 @@ void dispc_lcd_enable_signal_polarity(bool act_high)
void dispc_lcd_enable_signal(bool enable)
{
+ if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
+ return;
+
enable_clocks(1);
REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD),
enable ? 1 : 0, 28, 28);
@@ -1958,6 +1964,9 @@ void dispc_lcd_enable_signal(bool enable)
void dispc_pck_free_enable(bool enable)
{
+ if (!dss_has_feature(FEAT_PCKFREEENABLE))
+ return;
+
enable_clocks(1);
REG_FLD_MOD(DISPC_CONTROL(OMAP_DSS_CHANNEL_LCD),
enable ? 1 : 0, 27, 27);
@@ -3246,7 +3255,8 @@ static void _omap_dispc_initial_config(void)
dispc_write_reg(DISPC_SYSCONFIG, l);
/* FUNCGATED */
- REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD), 1, 9, 9);
+ if (dss_has_feature(FEAT_FUNCGATED))
+ REG_FLD_MOD(DISPC_CONFIG(OMAP_DSS_CHANNEL_LCD), 1, 9, 9);
/* L3 firewall setting: enable access to OCM RAM */
/* XXX this should be somewhere in plat-omap */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v4 7/7] OMAP: DSS2: Add new Overlay Manager
2010-11-08 12:24 [PATCH v4 0/7] OMAP: DSS2: Overlay Manager LCD2 support in DISPC Archit Taneja
` (5 preceding siblings ...)
2010-11-08 12:24 ` [PATCH v4 6/7] OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 Archit Taneja
@ 2010-11-08 12:24 ` Archit Taneja
6 siblings, 0 replies; 15+ messages in thread
From: Archit Taneja @ 2010-11-08 12:24 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Sumit Semwal, Mukund Mittal, Samreen
From: Sumit Semwal <sumit.semwal@ti.com>
Add new Overlay Manager in manager.c, make changes needed
for LCD2 channel.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
---
drivers/video/omap2/dss/dispc.c | 21 +++++------
drivers/video/omap2/dss/dss.h | 4 +-
drivers/video/omap2/dss/manager.c | 73 +++++++++++++++++++++++--------------
drivers/video/omap2/dss/overlay.c | 14 ++++++-
4 files changed, 70 insertions(+), 42 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e34c129..ab4ca0b 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1592,8 +1592,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
bool ilace,
enum omap_dss_rotation_type rotation_type,
u8 rotation, int mirror,
- u8 global_alpha,
- u8 pre_mult_alpha)
+ u8 global_alpha, u8 pre_mult_alpha,
+ enum omap_channel channel)
{
const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
bool five_taps = 0;
@@ -1692,8 +1692,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
five_taps = height > out_height * 2;
if (!five_taps) {
- fclk = calc_fclk(OMAP_DSS_CHANNEL_LCD, width, height,
- out_width, out_height);
+ fclk = calc_fclk(channel, width, height, out_width,
+ out_height);
/* Try 5-tap filter if 3-tap fclk is too high */
if (cpu_is_omap34xx() && height > out_height &&
@@ -1707,9 +1707,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
}
if (five_taps)
- fclk = calc_fclk_five_taps(OMAP_DSS_CHANNEL_LCD, width,
- height, out_width, out_height,
- color_mode);
+ fclk = calc_fclk_five_taps(channel, width, height,
+ out_width, out_height, color_mode);
DSSDBG("required fclk rate = %lu Hz\n", fclk);
DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
@@ -3331,17 +3330,17 @@ int dispc_setup_plane(enum omap_plane plane,
bool ilace,
enum omap_dss_rotation_type rotation_type,
u8 rotation, bool mirror, u8 global_alpha,
- u8 pre_mult_alpha)
+ u8 pre_mult_alpha, enum omap_channel channel)
{
int r = 0;
DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
- "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
+ "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
plane, paddr, screen_width, pos_x, pos_y,
width, height,
out_width, out_height,
ilace, color_mode,
- rotation, mirror);
+ rotation, mirror, channel);
enable_clocks(1);
@@ -3354,7 +3353,7 @@ int dispc_setup_plane(enum omap_plane plane,
rotation_type,
rotation, mirror,
global_alpha,
- pre_mult_alpha);
+ pre_mult_alpha, channel);
enable_clocks(0);
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 599df58..3072a76 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -359,8 +359,8 @@ int dispc_setup_plane(enum omap_plane plane,
bool ilace,
enum omap_dss_rotation_type rotation_type,
u8 rotation, bool mirror,
- u8 global_alpha,
- u8 pre_mult_alpha);
+ u8 global_alpha, u8 pre_mult_alpha,
+ enum omap_channel channel);
bool dispc_go_busy(enum omap_channel channel);
void dispc_go(enum omap_channel channel);
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 873b334..c345378 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -513,11 +513,14 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
unsigned long timeout = msecs_to_jiffies(500);
u32 irq;
- if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC)
+ if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) {
irq = DISPC_IRQ_EVSYNC_ODD;
- else
- irq = DISPC_IRQ_VSYNC;
-
+ } else {
+ if (mgr->device->channel == OMAP_DSS_CHANNEL_LCD)
+ irq = DISPC_IRQ_VSYNC;
+ else
+ irq = DISPC_IRQ_VSYNC2;
+ }
return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
}
@@ -525,7 +528,6 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
{
unsigned long timeout = msecs_to_jiffies(500);
struct manager_cache_data *mc;
- enum omap_channel channel;
u32 irq;
int r;
int i;
@@ -536,7 +538,6 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
- channel = OMAP_DSS_CHANNEL_DIGIT;
} else {
if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
enum omap_dss_update_mode mode;
@@ -544,11 +545,14 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
if (mode != OMAP_DSS_UPDATE_AUTO)
return 0;
- irq = DISPC_IRQ_FRAMEDONE;
+ irq = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+ DISPC_IRQ_FRAMEDONE
+ : DISPC_IRQ_FRAMEDONE2;
} else {
- irq = DISPC_IRQ_VSYNC;
+ irq = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+ DISPC_IRQ_VSYNC
+ : DISPC_IRQ_VSYNC2;
}
- channel = OMAP_DSS_CHANNEL_LCD;
}
mc = &dss_cache.manager_cache[mgr->id];
@@ -595,7 +599,6 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
{
unsigned long timeout = msecs_to_jiffies(500);
- enum omap_channel channel;
struct overlay_cache_data *oc;
struct omap_dss_device *dssdev;
u32 irq;
@@ -612,7 +615,6 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
- channel = OMAP_DSS_CHANNEL_DIGIT;
} else {
if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
enum omap_dss_update_mode mode;
@@ -620,11 +622,14 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
if (mode != OMAP_DSS_UPDATE_AUTO)
return 0;
- irq = DISPC_IRQ_FRAMEDONE;
+ irq = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+ DISPC_IRQ_FRAMEDONE
+ : DISPC_IRQ_FRAMEDONE2;
} else {
- irq = DISPC_IRQ_VSYNC;
+ irq = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+ DISPC_IRQ_VSYNC
+ : DISPC_IRQ_VSYNC2;
}
- channel = OMAP_DSS_CHANNEL_LCD;
}
oc = &dss_cache.overlay_cache[ovl->id];
@@ -844,7 +849,8 @@ static int configure_overlay(enum omap_plane plane)
c->rotation,
c->mirror,
c->global_alpha,
- c->pre_mult_alpha);
+ c->pre_mult_alpha,
+ c->channel);
if (r) {
/* this shouldn't happen */
@@ -896,10 +902,10 @@ static int configure_dispc(void)
r = 0;
busy = false;
- mgr_busy[0] = dispc_go_busy(0);
- mgr_busy[1] = dispc_go_busy(1);
- mgr_go[0] = false;
- mgr_go[1] = false;
+ for (i = 0; i < num_mgrs; i++) {
+ mgr_busy[i] = dispc_go_busy(i);
+ mgr_go[i] = false;
+ }
/* Commit overlay settings */
for (i = 0; i < num_ovls; ++i) {
@@ -1158,9 +1164,10 @@ static void dss_apply_irq_handler(void *data, u32 mask)
const int num_mgrs = dss_feat_get_num_mgrs();
int i, r;
bool mgr_busy[MAX_DSS_MANAGERS];
+ u32 irq_mask;
- mgr_busy[0] = dispc_go_busy(0);
- mgr_busy[1] = dispc_go_busy(1);
+ for (i = 0; i < num_mgrs; i++)
+ mgr_busy[i] = dispc_go_busy(i);
spin_lock(&dss_cache.lock);
@@ -1191,9 +1198,12 @@ static void dss_apply_irq_handler(void *data, u32 mask)
goto end;
}
- omap_dispc_unregister_isr(dss_apply_irq_handler, NULL,
- DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
- DISPC_IRQ_EVSYNC_EVEN);
+ irq_mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
+ DISPC_IRQ_EVSYNC_EVEN;
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ irq_mask |= DISPC_IRQ_VSYNC2;
+
+ omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, irq_mask);
dss_cache.irq_enabled = false;
end:
@@ -1386,9 +1396,14 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
r = 0;
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
if (!dss_cache.irq_enabled) {
- r = omap_dispc_register_isr(dss_apply_irq_handler, NULL,
- DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
- DISPC_IRQ_EVSYNC_EVEN);
+ u32 mask;
+
+ mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
+ DISPC_IRQ_EVSYNC_EVEN;
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ mask |= DISPC_IRQ_VSYNC2;
+
+ r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
dss_cache.irq_enabled = true;
}
configure_dispc();
@@ -1480,6 +1495,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
mgr->name = "tv";
mgr->id = OMAP_DSS_CHANNEL_DIGIT;
break;
+ case 2:
+ mgr->name = "lcd2";
+ mgr->id = OMAP_DSS_CHANNEL_LCD2;
+ break;
}
mgr->set_device = &omap_dss_set_device;
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index 41a2902..456efef 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -664,12 +664,22 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
int i;
struct omap_overlay_manager *lcd_mgr;
struct omap_overlay_manager *tv_mgr;
+ struct omap_overlay_manager *lcd2_mgr = NULL;
struct omap_overlay_manager *mgr = NULL;
lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
-
- if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
+ if (dss_has_feature(FEAT_MGR_LCD2))
+ lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD2);
+
+ if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
+ if (!lcd2_mgr->device || force) {
+ if (lcd2_mgr->device)
+ lcd2_mgr->unset_device(lcd2_mgr);
+ lcd2_mgr->set_device(lcd2_mgr, dssdev);
+ mgr = lcd2_mgr;
+ }
+ } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
if (!lcd_mgr->device || force) {
if (lcd_mgr->device)
lcd_mgr->unset_device(lcd_mgr);
--
1.7.0.4
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