From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hari Kanigeri Subject: [PATCH v3 2/5] OMAP: mailbox: fix rx interrupt disable in omap4 Date: Thu, 18 Nov 2010 13:15:39 -0600 Message-ID: <1290107742-16760-3-git-send-email-h-kanigeri2@ti.com> References: <1290107742-16760-1-git-send-email-h-kanigeri2@ti.com> Return-path: Received: from arroyo.ext.ti.com ([192.94.94.40]:54486 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753157Ab0KRTNu (ORCPT ); Thu, 18 Nov 2010 14:13:50 -0500 In-Reply-To: <1290107742-16760-1-git-send-email-h-kanigeri2@ti.com> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Hiroshi Doyu , linux omap Cc: Tony Lindgren , Linux ARM , Hari Kanigeri disabling rx interrupt on omap4 is different than its pre-decessors. The bit in OMAP4_MAILBOX_IRQENABLE_CLR should be set to disable the interrupts instead of clearing the bit. Signed-off-by: Hari Kanigeri --- arch/arm/mach-omap2/mailbox.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 42dbfa4..82b5ced 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -195,7 +195,10 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox, struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqdisable); - l &= ~bit; + if (cpu_is_omap44xx()) + l |= bit; + else + l &= ~bit; mbox_write_reg(l, p->irqdisable); } -- 1.7.0