* [PATCH 1/3] OMAP2PLUS: DSS2: Make members of dss_clk_source generic
2011-02-28 6:50 [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names Archit Taneja
@ 2011-02-28 6:50 ` Archit Taneja
2011-02-28 6:50 ` [PATCH 2/3] OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP Archit Taneja
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Archit Taneja @ 2011-02-28 6:50 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
The enum members of 'dss_clk_source' have clock source names specific to
OMAP2/3. Change the names to more generic terms such that they now describe
where the clocks come from and what they are used for.
Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC"
for more clarity.
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 4 ++--
drivers/video/omap2/dss/dpi.c | 4 ++--
drivers/video/omap2/dss/dsi.c | 20 ++++++++++----------
drivers/video/omap2/dss/dss.c | 20 ++++++++++----------
drivers/video/omap2/dss/dss.h | 6 +++---
5 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 3616302..7563f12 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2341,7 +2341,7 @@ unsigned long dispc_fclk_rate(void)
{
unsigned long r = 0;
- if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
+ if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK)
r = dss_clk_get_rate(DSS_CLK_FCK);
else
#ifdef CONFIG_OMAP2_DSS_DSI
@@ -2393,7 +2393,7 @@ void dispc_dump_clocks(struct seq_file *s)
seq_printf(s, "- DISPC -\n");
seq_printf(s, "dispc fclk source = %s\n",
- dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
+ dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
"dss1_alwon_fclk" : "dsi1_pll_fclk");
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 026702b..1b2867d 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -57,7 +57,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
if (r)
return r;
- dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
+ dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
if (r)
@@ -217,7 +217,7 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
dssdev->manager->disable(dssdev->manager);
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
dsi_pll_uninit();
dss_clk_disable(DSS_CLK_SYSCK);
#endif
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 2e92888..964dbd5 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -731,7 +731,7 @@ static unsigned long dsi_fclk_rate(void)
{
unsigned long r;
- if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
+ if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
r = dss_clk_get_rate(DSS_CLK_FCK);
} else {
@@ -1188,19 +1188,19 @@ void dsi_dump_clocks(struct seq_file *s)
seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
cinfo->dsi1_pll_fclk,
cinfo->regm3,
- dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
+ dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
"off" : "on");
seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
cinfo->dsi2_pll_fclk,
cinfo->regm4,
- dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
+ dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
"off" : "on");
seq_printf(s, "- DSI -\n");
seq_printf(s, "dsi fclk source = %s\n",
- dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
+ dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
"dss1_alwon_fclk" : "dsi2_pll_fclk");
seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
@@ -3052,8 +3052,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
if (r)
goto err1;
- dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
- dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
+ dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
+ dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
DSSDBG("PLL OK\n");
@@ -3089,8 +3089,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
err3:
dsi_complexio_uninit();
err2:
- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
- dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
+ dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
err1:
dsi_pll_uninit();
err0:
@@ -3106,8 +3106,8 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
dsi_vc_enable(2, 0);
dsi_vc_enable(3, 0);
- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
- dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
+ dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
dsi_complexio_uninit();
dsi_pll_uninit();
}
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index a73dbab..1225979 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -272,12 +272,12 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
{
int b;
- BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
- clk_src != DSS_SRC_DSS1_ALWON_FCLK);
+ BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
+ clk_src != DSS_CLK_SRC_FCK);
- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
+ b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
- if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
+ if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
dsi_wait_dsi1_pll_active();
REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
@@ -289,12 +289,12 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
{
int b;
- BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
- clk_src != DSS_SRC_DSS1_ALWON_FCLK);
+ BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
+ clk_src != DSS_CLK_SRC_FCK);
- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
+ b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
- if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
+ if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
dsi_wait_dsi2_pll_active();
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
@@ -595,8 +595,8 @@ static int dss_init(bool skip_init)
}
}
- dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
- dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
+ dss.dsi_clk_source = DSS_CLK_SRC_FCK;
+ dss.dispc_clk_source = DSS_CLK_SRC_FCK;
dss_save_context();
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 7fe32d1..a166ff3 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -118,9 +118,9 @@ enum dss_clock {
};
enum dss_clk_source {
- DSS_SRC_DSI1_PLL_FCLK,
- DSS_SRC_DSI2_PLL_FCLK,
- DSS_SRC_DSS1_ALWON_FCLK,
+ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* DSI1_PLL_FCLK */
+ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* DSI2_PLL_FCLK */
+ DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */
};
struct dss_clock_info {
--
1.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP
2011-02-28 6:50 [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names Archit Taneja
2011-02-28 6:50 ` [PATCH 1/3] OMAP2PLUS: DSS2: Make members of dss_clk_source generic Archit Taneja
@ 2011-02-28 6:50 ` Archit Taneja
2011-02-28 6:50 ` [PATCH 3/3] OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming Archit Taneja
2011-02-28 12:29 ` [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names Tomi Valkeinen
3 siblings, 0 replies; 5+ messages in thread
From: Archit Taneja @ 2011-02-28 6:50 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
Clock source names vary across OMAP2/3 and OMAP4, the clock source enum
names have been made generic in the driver, but for purposes of debugging
and dumping clock sources, it is better to preserve the actual TRM name of
the clock.
Introduce a dss feature function 'dss_feat_get_clk_source_name()' which
returns a string with the TRM clock name for the current OMAP in use. The OMAP
specific name is printed along the generic name within brackets.
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/dispc.c | 7 +++--
drivers/video/omap2/dss/dsi.c | 42 ++++++++++++++++++++++----------
drivers/video/omap2/dss/dss.c | 19 +++++++++++++-
drivers/video/omap2/dss/dss.h | 7 +++++
drivers/video/omap2/dss/dss_features.c | 23 +++++++++++++++++
drivers/video/omap2/dss/dss_features.h | 1 +
6 files changed, 81 insertions(+), 18 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 7563f12..c6392c4 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2387,14 +2387,15 @@ void dispc_dump_clocks(struct seq_file *s)
{
int lcd, pcd;
u32 l;
+ enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
enable_clocks(1);
seq_printf(s, "- DISPC -\n");
- seq_printf(s, "dispc fclk source = %s\n",
- dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
- "dss1_alwon_fclk" : "dsi1_pll_fclk");
+ seq_printf(s, "dispc fclk source = %s (%s)\n",
+ dss_get_generic_clk_source_name(dispc_clk_src),
+ dss_feat_get_clk_source_name(dispc_clk_src));
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 964dbd5..4009991 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1022,10 +1022,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
- DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
- cinfo->regm3, cinfo->dsi1_pll_fclk);
- DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
- cinfo->regm4, cinfo->dsi2_pll_fclk);
+ DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3,
+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+ cinfo->dsi1_pll_fclk);
+ DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4,
+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+ cinfo->dsi2_pll_fclk);
REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
@@ -1169,6 +1173,10 @@ void dsi_dump_clocks(struct seq_file *s)
{
int clksel;
struct dsi_clock_info *cinfo = &dsi.current_cinfo;
+ enum dss_clk_source dispc_clk_src, dsi_clk_src;
+
+ dispc_clk_src = dss_get_dispc_clk_source();
+ dsi_clk_src = dss_get_dsi_clk_source();
enable_clocks(1);
@@ -1185,23 +1193,27 @@ void dsi_dump_clocks(struct seq_file *s)
seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
cinfo->clkin4ddr, cinfo->regm);
- seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
+ seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n",
+ dss_get_generic_clk_source_name(dispc_clk_src),
+ dss_feat_get_clk_source_name(dispc_clk_src),
cinfo->dsi1_pll_fclk,
cinfo->regm3,
- dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
+ dispc_clk_src == DSS_CLK_SRC_FCK ?
"off" : "on");
- seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
+ seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n",
+ dss_get_generic_clk_source_name(dsi_clk_src),
+ dss_feat_get_clk_source_name(dsi_clk_src),
cinfo->dsi2_pll_fclk,
cinfo->regm4,
- dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
+ dsi_clk_src == DSS_CLK_SRC_FCK ?
"off" : "on");
seq_printf(s, "- DSI -\n");
- seq_printf(s, "dsi fclk source = %s\n",
- dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
- "dss1_alwon_fclk" : "dsi2_pll_fclk");
+ seq_printf(s, "dsi fclk source = %s (%s)\n",
+ dss_get_generic_clk_source_name(dsi_clk_src),
+ dss_feat_get_clk_source_name(dsi_clk_src));
seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
@@ -3249,13 +3261,17 @@ int dsi_init_display(struct omap_dss_device *dssdev)
void dsi_wait_dsi1_pll_active(void)
{
if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
- DSSERR("DSI1 PLL clock not active\n");
+ DSSERR("%s (%s) not active\n",
+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
}
void dsi_wait_dsi2_pll_active(void)
{
if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
- DSSERR("DSI2 PLL clock not active\n");
+ DSSERR("%s (%s) not active\n",
+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
}
static int dsi_init(struct platform_device *pdev)
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 1225979..44707a3 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -81,6 +81,12 @@ static struct {
u32 ctx[DSS_SZ_REGS / sizeof(u32)];
} dss;
+static const struct dss_clk_source_name dss_generic_clk_source_names[] = {
+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" },
+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" },
+ { DSS_CLK_SRC_FCK, "DSS_FCK" },
+};
+
static void dss_clk_enable_all_no_ctx(void);
static void dss_clk_disable_all_no_ctx(void);
static void dss_clk_enable_no_ctx(enum dss_clock clks);
@@ -221,6 +227,11 @@ void dss_sdi_disable(void)
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
}
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
+{
+ return dss_generic_clk_source_names[clk_src].clksrc_name;
+}
+
void dss_dump_clocks(struct seq_file *s)
{
unsigned long dpll4_ck_rate;
@@ -236,12 +247,16 @@ void dss_dump_clocks(struct seq_file *s)
seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
if (cpu_is_omap3630())
- seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
+ seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
+ dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
+ dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
dpll4_ck_rate,
dpll4_ck_rate / dpll4_m4_ck_rate,
dss_clk_get_rate(DSS_CLK_FCK));
else
- seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
+ seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
+ dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
+ dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
dpll4_ck_rate,
dpll4_ck_rate / dpll4_m4_ck_rate,
dss_clk_get_rate(DSS_CLK_FCK));
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index a166ff3..42ca70f 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -123,6 +123,12 @@ enum dss_clk_source {
DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */
};
+/* Correlates clock source name and dss_clk_source member */
+struct dss_clk_source_name {
+ enum dss_clk_source clksrc;
+ const char *clksrc_name;
+};
+
struct dss_clock_info {
/* rates that we get with dividers below */
unsigned long fck;
@@ -215,6 +221,7 @@ void dss_clk_enable(enum dss_clock clks);
void dss_clk_disable(enum dss_clock clks);
unsigned long dss_clk_get_rate(enum dss_clock clk);
int dss_need_ctx_restore(void);
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);
void dss_dump_clocks(struct seq_file *s);
void dss_dump_regs(struct seq_file *s);
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 5ba591e..6c8d709 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -25,6 +25,7 @@
#include <plat/display.h>
#include <plat/cpu.h>
+#include "dss.h"
#include "dss_features.h"
/* Defines a generic omap register field */
@@ -44,6 +45,7 @@ struct omap_dss_features {
const unsigned long max_dss_fck;
const enum omap_display_type *supported_displays;
const enum omap_color_mode *supported_color_modes;
+ const struct dss_clk_source_name *clksrc_names;
};
/* This struct is assigned to one of the below during initialization */
@@ -149,6 +151,18 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
};
+static const struct dss_clk_source_name omap2_dss_clk_source_names[] = {
+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" },
+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" },
+ { DSS_CLK_SRC_FCK, "DSS_FCLK1" },
+};
+
+static const struct dss_clk_source_name omap3_dss_clk_source_names[] = {
+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" },
+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" },
+ { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" },
+};
+
/* OMAP2 DSS Features */
static struct omap_dss_features omap2_dss_features = {
.reg_fields = omap2_dss_reg_fields,
@@ -164,6 +178,7 @@ static struct omap_dss_features omap2_dss_features = {
.max_dss_fck = 173000000,
.supported_displays = omap2_dss_supported_displays,
.supported_color_modes = omap2_dss_supported_color_modes,
+ .clksrc_names = omap2_dss_clk_source_names,
};
/* OMAP3 DSS Features */
@@ -182,6 +197,7 @@ static struct omap_dss_features omap3430_dss_features = {
.max_dss_fck = 173000000,
.supported_displays = omap3_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
+ .clksrc_names = omap3_dss_clk_source_names,
};
static struct omap_dss_features omap3630_dss_features = {
@@ -200,6 +216,7 @@ static struct omap_dss_features omap3630_dss_features = {
.max_dss_fck = 173000000,
.supported_displays = omap3_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
+ .clksrc_names = omap3_dss_clk_source_names,
};
/* OMAP4 DSS Features */
@@ -217,6 +234,7 @@ static struct omap_dss_features omap4_dss_features = {
.max_dss_fck = 186000000,
.supported_displays = omap4_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
+ .clksrc_names = omap3_dss_clk_source_names,
};
/* Functions returning values related to a DSS feature */
@@ -253,6 +271,11 @@ bool dss_feat_color_mode_supported(enum omap_plane plane,
color_mode;
}
+const char *dss_feat_get_clk_source_name(enum dss_clk_source id)
+{
+ return omap_current_dss_features->clksrc_names[id].clksrc_name;
+}
+
/* DSS has_feature check */
bool dss_has_feature(enum dss_feat_id id)
{
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index b983c21..4f11e5e 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -59,6 +59,7 @@ enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
bool dss_feat_color_mode_supported(enum omap_plane plane,
enum omap_color_mode color_mode);
+const char *dss_feat_get_clk_source_name(enum dss_clk_source id);
bool dss_has_feature(enum dss_feat_id id);
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
--
1.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming
2011-02-28 6:50 [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names Archit Taneja
2011-02-28 6:50 ` [PATCH 1/3] OMAP2PLUS: DSS2: Make members of dss_clk_source generic Archit Taneja
2011-02-28 6:50 ` [PATCH 2/3] OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP Archit Taneja
@ 2011-02-28 6:50 ` Archit Taneja
2011-02-28 12:29 ` [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names Tomi Valkeinen
3 siblings, 0 replies; 5+ messages in thread
From: Archit Taneja @ 2011-02-28 6:50 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, Archit Taneja
DSI PLL output clock names have been made more generic. The clock name
describes what the source of the clock and what clock is used for. Some of
DSI PLL parameters like dividers and DSI PLL source have also been made more
generic.
dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk
and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named
regm_dispc and regm_dsi instead of regm3 and regm4.
Functions and macros named on the basis of these clock names have also been
made generic.
Signed-off-by: Archit Taneja <archit@ti.com>
---
arch/arm/plat-omap/include/plat/display.h | 4 +-
drivers/video/omap2/dss/dispc.c | 2 +-
drivers/video/omap2/dss/dpi.c | 4 +-
drivers/video/omap2/dss/dsi.c | 134 +++++++++++++++--------------
drivers/video/omap2/dss/dss.c | 4 +-
drivers/video/omap2/dss/dss.h | 20 ++--
6 files changed, 87 insertions(+), 81 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 2fb057e..d45f107 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -401,8 +401,8 @@ struct omap_dss_device {
struct {
u16 regn;
u16 regm;
- u16 regm3;
- u16 regm4;
+ u16 regm_dispc;
+ u16 regm_dsi;
u16 lp_clk_div;
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index c6392c4..ce11204 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2345,7 +2345,7 @@ unsigned long dispc_fclk_rate(void)
r = dss_clk_get_rate(DSS_CLK_FCK);
else
#ifdef CONFIG_OMAP2_DSS_DSI
- r = dsi_get_dsi1_pll_rate();
+ r = dsi_get_pll_hsdiv_dispc_rate();
#else
BUG();
#endif
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 1b2867d..08fed30 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -63,7 +63,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
if (r)
return r;
- *fck = dsi_cinfo.dsi1_pll_fclk;
+ *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
*lck_div = dispc_cinfo.lck_div;
*pck_div = dispc_cinfo.pck_div;
@@ -271,7 +271,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
if (r)
return r;
- fck = dsi_cinfo.dsi1_pll_fclk;
+ fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
lck_div = dispc_cinfo.lck_div;
pck_div = dispc_cinfo.pck_div;
}
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 4009991..cda83b0 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -189,8 +189,8 @@ struct dsi_reg { u16 idx; };
#define FINT_MIN 750000
#define REGN_MAX (1 << 7)
#define REGM_MAX ((1 << 11) - 1)
-#define REGM3_MAX (1 << 4)
-#define REGM4_MAX (1 << 4)
+#define REGM_DISPC_MAX (1 << 4)
+#define REGM_DSI_MAX (1 << 4)
#define LP_DIV_MAX ((1 << 13) - 1)
enum fifo_size {
@@ -642,7 +642,7 @@ static void dsi_vc_disable_bta_irq(int channel)
dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
}
-/* DSI func clock. this could also be DSI2_PLL_FCLK */
+/* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */
static inline void enable_clocks(bool enable)
{
if (enable)
@@ -712,14 +712,14 @@ static inline int dsi_if_enable(bool enable)
return 0;
}
-unsigned long dsi_get_dsi1_pll_rate(void)
+unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
{
- return dsi.current_cinfo.dsi1_pll_fclk;
+ return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk;
}
-static unsigned long dsi_get_dsi2_pll_rate(void)
+static unsigned long dsi_get_pll_hsdiv_dsi_rate(void)
{
- return dsi.current_cinfo.dsi2_pll_fclk;
+ return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk;
}
static unsigned long dsi_get_txbyteclkhs(void)
@@ -732,11 +732,11 @@ static unsigned long dsi_fclk_rate(void)
unsigned long r;
if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
- /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
+ /* DSI FCLK source is DSS_CLK_FCK */
r = dss_clk_get_rate(DSS_CLK_FCK);
} else {
- /* DSI FCLK source is DSI2_PLL_FCLK */
- r = dsi_get_dsi2_pll_rate();
+ /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
+ r = dsi_get_pll_hsdiv_dsi_rate();
}
return r;
@@ -806,16 +806,16 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
return -EINVAL;
- if (cinfo->regm3 > REGM3_MAX)
+ if (cinfo->regm_dispc > REGM_DISPC_MAX)
return -EINVAL;
- if (cinfo->regm4 > REGM4_MAX)
+ if (cinfo->regm_dsi > REGM_DSI_MAX)
return -EINVAL;
- if (cinfo->use_dss2_fck) {
+ if (cinfo->use_sys_clk) {
cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
/* XXX it is unclear if highfreq should be used
- * with DSS2_FCK source also */
+ * with DSS_SYS_CLK source also */
cinfo->highfreq = 0;
} else {
cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
@@ -836,15 +836,17 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
return -EINVAL;
- if (cinfo->regm3 > 0)
- cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
+ if (cinfo->regm_dispc > 0)
+ cinfo->dsi_pll_hsdiv_dispc_clk =
+ cinfo->clkin4ddr / cinfo->regm_dispc;
else
- cinfo->dsi1_pll_fclk = 0;
+ cinfo->dsi_pll_hsdiv_dispc_clk = 0;
- if (cinfo->regm4 > 0)
- cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
+ if (cinfo->regm_dsi > 0)
+ cinfo->dsi_pll_hsdiv_dsi_clk =
+ cinfo->clkin4ddr / cinfo->regm_dsi;
else
- cinfo->dsi2_pll_fclk = 0;
+ cinfo->dsi_pll_hsdiv_dsi_clk = 0;
return 0;
}
@@ -857,18 +859,18 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
struct dispc_clock_info best_dispc;
int min_fck_per_pck;
int match = 0;
- unsigned long dss_clk_fck2, max_dss_fck;
+ unsigned long dss_sys_clk, max_dss_fck;
- dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
+ dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK);
max_dss_fck = dss_feat_get_max_dss_fck();
if (req_pck == dsi.cache_req_pck &&
- dsi.cache_cinfo.clkin == dss_clk_fck2) {
+ dsi.cache_cinfo.clkin == dss_sys_clk) {
DSSDBG("DSI clock info found from cache\n");
*dsi_cinfo = dsi.cache_cinfo;
- dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
- dispc_cinfo);
+ dispc_find_clk_divs(is_tft, req_pck,
+ dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
return 0;
}
@@ -889,8 +891,8 @@ retry:
memset(&best_dispc, 0, sizeof(best_dispc));
memset(&cur, 0, sizeof(cur));
- cur.clkin = dss_clk_fck2;
- cur.use_dss2_fck = 1;
+ cur.clkin = dss_sys_clk;
+ cur.use_sys_clk = 1;
cur.highfreq = 0;
/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
@@ -916,30 +918,32 @@ retry:
if (cur.clkin4ddr > 1800 * 1000 * 1000)
break;
- /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
- for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
- ++cur.regm3) {
+ /* dsi_pll_hsdiv_dispc_clk(MHz) =
+ * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
+ for (cur.regm_dispc = 1; cur.regm_dispc < REGM_DISPC_MAX;
+ ++cur.regm_dispc) {
struct dispc_clock_info cur_dispc;
- cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
+ cur.dsi_pll_hsdiv_dispc_clk =
+ cur.clkin4ddr / cur.regm_dispc;
/* this will narrow down the search a bit,
* but still give pixclocks below what was
* requested */
- if (cur.dsi1_pll_fclk < req_pck)
+ if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
break;
- if (cur.dsi1_pll_fclk > max_dss_fck)
+ if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
continue;
if (min_fck_per_pck &&
- cur.dsi1_pll_fclk <
+ cur.dsi_pll_hsdiv_dispc_clk <
req_pck * min_fck_per_pck)
continue;
match = 1;
dispc_find_clk_divs(is_tft, req_pck,
- cur.dsi1_pll_fclk,
+ cur.dsi_pll_hsdiv_dispc_clk,
&cur_dispc);
if (abs(cur_dispc.pck - req_pck) <
@@ -968,9 +972,9 @@ found:
return -EINVAL;
}
- /* DSI2_PLL_FCLK (regm4) is not used */
- best.regm4 = 0;
- best.dsi2_pll_fclk = 0;
+ /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
+ best.regm_dsi = 0;
+ best.dsi_pll_hsdiv_dsi_clk = 0;
if (dsi_cinfo)
*dsi_cinfo = best;
@@ -994,18 +998,20 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
dsi.current_cinfo.fint = cinfo->fint;
dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
- dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
- dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
+ dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk =
+ cinfo->dsi_pll_hsdiv_dispc_clk;
+ dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk =
+ cinfo->dsi_pll_hsdiv_dsi_clk;
dsi.current_cinfo.regn = cinfo->regn;
dsi.current_cinfo.regm = cinfo->regm;
- dsi.current_cinfo.regm3 = cinfo->regm3;
- dsi.current_cinfo.regm4 = cinfo->regm4;
+ dsi.current_cinfo.regm_dispc = cinfo->regm_dispc;
+ dsi.current_cinfo.regm_dsi = cinfo->regm_dsi;
DSSDBG("DSI Fint %ld\n", cinfo->fint);
DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
- cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
+ cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
cinfo->clkin,
cinfo->highfreq);
@@ -1022,14 +1028,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
- DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3,
+ DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
- cinfo->dsi1_pll_fclk);
- DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4,
+ cinfo->dsi_pll_hsdiv_dispc_clk);
+ DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
- cinfo->dsi2_pll_fclk);
+ cinfo->dsi_pll_hsdiv_dsi_clk);
REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
@@ -1037,9 +1043,9 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
- l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
+ l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
22, 19); /* DSI_CLOCK_DIV */
- l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
+ l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
26, 23); /* DSIPROTO_CLOCK_DIV */
dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
@@ -1057,7 +1063,7 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
- l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
+ l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
11, 11); /* DSI_PLL_CLKSEL */
l = FLD_MOD(l, cinfo->highfreq,
12, 12); /* DSI_PLL_HIGHFREQ */
@@ -1186,26 +1192,26 @@ void dsi_dump_clocks(struct seq_file *s)
seq_printf(s, "dsi pll source = %s\n",
clksel == 0 ?
- "dss2_alwon_fclk" : "pclkfree");
+ "dss_sys_clk" : "pclkfree");
seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
cinfo->clkin4ddr, cinfo->regm);
- seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n",
+ seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
dss_get_generic_clk_source_name(dispc_clk_src),
dss_feat_get_clk_source_name(dispc_clk_src),
- cinfo->dsi1_pll_fclk,
- cinfo->regm3,
+ cinfo->dsi_pll_hsdiv_dispc_clk,
+ cinfo->regm_dispc,
dispc_clk_src == DSS_CLK_SRC_FCK ?
"off" : "on");
- seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n",
+ seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
dss_get_generic_clk_source_name(dsi_clk_src),
dss_feat_get_clk_source_name(dsi_clk_src),
- cinfo->dsi2_pll_fclk,
- cinfo->regm4,
+ cinfo->dsi_pll_hsdiv_dsi_clk,
+ cinfo->regm_dsi,
dsi_clk_src == DSS_CLK_SRC_FCK ?
"off" : "on");
@@ -3003,12 +3009,12 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
struct dsi_clock_info cinfo;
int r;
- /* we always use DSS2_FCK as input clock */
- cinfo.use_dss2_fck = true;
+ /* we always use DSS_CLK_SYSCK as input clock */
+ cinfo.use_sys_clk = true;
cinfo.regn = dssdev->phy.dsi.div.regn;
cinfo.regm = dssdev->phy.dsi.div.regm;
- cinfo.regm3 = dssdev->phy.dsi.div.regm3;
- cinfo.regm4 = dssdev->phy.dsi.div.regm4;
+ cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc;
+ cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi;
r = dsi_calc_clock_rates(dssdev, &cinfo);
if (r) {
DSSERR("Failed to calc dsi clocks\n");
@@ -3030,7 +3036,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
int r;
unsigned long long fck;
- fck = dsi_get_dsi1_pll_rate();
+ fck = dsi_get_pll_hsdiv_dispc_rate();
dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
@@ -3258,7 +3264,7 @@ int dsi_init_display(struct omap_dss_device *dssdev)
return 0;
}
-void dsi_wait_dsi1_pll_active(void)
+void dsi_wait_pll_hsdiv_dispc_active(void)
{
if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
DSSERR("%s (%s) not active\n",
@@ -3266,7 +3272,7 @@ void dsi_wait_dsi1_pll_active(void)
dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
}
-void dsi_wait_dsi2_pll_active(void)
+void dsi_wait_pll_hsdiv_dsi_active(void)
{
if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
DSSERR("%s (%s) not active\n",
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 44707a3..53c13bc 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -293,7 +293,7 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
- dsi_wait_dsi1_pll_active();
+ dsi_wait_pll_hsdiv_dispc_active();
REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
@@ -310,7 +310,7 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
- dsi_wait_dsi2_pll_active();
+ dsi_wait_pll_hsdiv_dsi_active();
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 42ca70f..20590fb 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -152,21 +152,21 @@ struct dsi_clock_info {
unsigned long fint;
unsigned long clkin4ddr;
unsigned long clkin;
- unsigned long dsi1_pll_fclk;
- unsigned long dsi2_pll_fclk;
+ unsigned long dsi_pll_hsdiv_dispc_clk; /* DSI1_PLL_CLK */
+ unsigned long dsi_pll_hsdiv_dsi_clk; /* DSI2_PLL_CLK */
unsigned long lp_clk;
/* dividers */
u16 regn;
u16 regm;
- u16 regm3;
- u16 regm4;
+ u16 regm_dispc; /* REGM3 */
+ u16 regm_dsi; /* REGM4 */
u16 lp_clk_div;
u8 highfreq;
- bool use_dss2_fck;
+ bool use_sys_clk;
};
struct seq_file;
@@ -278,7 +278,7 @@ void dsi_restore_context(void);
int dsi_init_display(struct omap_dss_device *display);
void dsi_irq_handler(void);
-unsigned long dsi_get_dsi1_pll_rate(void);
+unsigned long dsi_get_pll_hsdiv_dispc_rate(void);
int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
struct dsi_clock_info *cinfo,
@@ -289,8 +289,8 @@ void dsi_pll_uninit(void);
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, enum omap_burst_size *burst_size,
u32 *fifo_low, u32 *fifo_high);
-void dsi_wait_dsi1_pll_active(void);
-void dsi_wait_dsi2_pll_active(void);
+void dsi_wait_pll_hsdiv_dispc_active(void);
+void dsi_wait_pll_hsdiv_dsi_active(void);
#else
static inline int dsi_init_platform_driver(void)
{
@@ -299,10 +299,10 @@ static inline int dsi_init_platform_driver(void)
static inline void dsi_uninit_platform_driver(void)
{
}
-static inline void dsi_wait_dsi1_pll_active(void)
+static inline void dsi_wait_pll_hsdiv_dispc_active(void)
{
}
-static inline void dsi_wait_dsi2_pll_active(void)
+static inline void dsi_wait_pll_hsdiv_dsi_active(void)
{
}
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names
2011-02-28 6:50 [PATCH 0/3] OMAP: DSS2: Generalize DSS clock source names Archit Taneja
` (2 preceding siblings ...)
2011-02-28 6:50 ` [PATCH 3/3] OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming Archit Taneja
@ 2011-02-28 12:29 ` Tomi Valkeinen
3 siblings, 0 replies; 5+ messages in thread
From: Tomi Valkeinen @ 2011-02-28 12:29 UTC (permalink / raw)
To: Taneja, Archit; +Cc: linux-omap@vger.kernel.org
Hi,
On Mon, 2011-02-28 at 00:50 -0600, Taneja, Archit wrote:
> The OMAP Display Subsystem has multiple clock sources available for its
> modules. One of these sources has to be selected through a global control
> register called DSS_CTRL.
>
> For example, on OMAP4, the Display Controller Module's (DISPC) functional
> clock can be derived from:
> a) output of DPLL_PER's M5 divisor
> b) output of DSI1 PLL's M4 divisor
> c) output of DSI2 PLL's M4 divisor
> d) output of HDMI PLL
>
> There is, hence, an enum called 'dss_clk_source' which is used throughout
> DSS2, to select clock sources for various DSS sub modules. These clock
> source names are currently specific to OMAP2/3 TRM clock names.
>
> All enum members, variables, functions which are based on these clock
> source names have been made generic such that they can be used for future
> OMAPs as well.
>
> Archit Taneja (3):
> OMAP2PLUS: DSS2: Make members of dss_clk_source generic
> OMAP2PLUS: DSS2: Use dss features to get clock source names of
> current OMAP
> OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming
This patch set, and also the two individual patches for using
dss_features, look ok. However, they don't apply to DSS tree. Can you
rebase these on top of DSS master branch, please?
Tomi
^ permalink raw reply [flat|nested] 5+ messages in thread