* [PATCH 0/5] OMAPDSS: HDMI: Debug support and Register cleanup
@ 2011-09-20 12:49 mythripk
2011-09-20 12:49 ` [PATCH 1/5] OMAPDSS: HDMI: Move the comments in avi infoframe mythripk
0 siblings, 1 reply; 10+ messages in thread
From: mythripk @ 2011-09-20 12:49 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
Add support to dump HDMI core, wrapper, PHY and PLL registers and the clock
dividers for HDMI.
Some changes such as
1.Add some H/w indexable registers missed in definition.
2.Remove usage of struct hdmi_reg and use u16 instead.
3.Move the avi_infoframe parameters comments above the field.
are also added as a part of this patch series.
Mythri P K (5):
OMAPDSS: HDMI: Move the comments in avi infoframe structure
OMAPDSS: HDMI: Replace hdmi_reg struct with u16
OMAPDSS: HDMI: Add missing register definitions
OMAPDSS: HDMI: Add support to dump registers through debugfs
OMAPDSS: HDMI: Add support to dump clocks through debugfs
drivers/video/omap2/dss/core.c | 4 +
drivers/video/omap2/dss/dss.c | 3 +
drivers/video/omap2/dss/dss.h | 2 +
drivers/video/omap2/dss/dss_features.c | 5 +
drivers/video/omap2/dss/hdmi.c | 47 +++++
drivers/video/omap2/dss/ti_hdmi.h | 14 ++
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 178 +++++++++++++++++-
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 296 ++++++++++++++---------------
8 files changed, 394 insertions(+), 155 deletions(-)
--
1.7.5.4
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/5] OMAPDSS: HDMI: Move the comments in avi infoframe
2011-09-20 12:49 [PATCH 0/5] OMAPDSS: HDMI: Debug support and Register cleanup mythripk
@ 2011-09-20 12:49 ` mythripk
2011-09-20 12:49 ` [PATCH 2/5] OMAPDSS: HDMI: Replace hdmi_reg struct with u16 mythripk
0 siblings, 1 reply; 10+ messages in thread
From: mythripk @ 2011-09-20 12:49 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
Move the comments in AVI infoframe structure above each parameter
to align with other comments in the header file
Signed-off-by: Mythri P K <mythripk@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 34 ++++++++++++++--------------
1 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 929de88..de1e199 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -455,40 +455,40 @@ struct hdmi_core_video_config {
* details about infoframe databytes
*/
struct hdmi_core_infoframe_avi {
+ /* Y0, Y1 rgb,yCbCr */
u8 db1_format;
- /* Y0, Y1 rgb,yCbCr */
+ /* A0 Active information Present */
u8 db1_active_info;
- /* A0 Active information Present */
+ /* B0, B1 Bar info data valid */
u8 db1_bar_info_dv;
- /* B0, B1 Bar info data valid */
+ /* S0, S1 scan information */
u8 db1_scan_info;
- /* S0, S1 scan information */
+ /* C0, C1 colorimetry */
u8 db2_colorimetry;
- /* C0, C1 colorimetry */
+ /* M0, M1 Aspect ratio (4:3, 16:9) */
u8 db2_aspect_ratio;
- /* M0, M1 Aspect ratio (4:3, 16:9) */
+ /* R0...R3 Active format aspect ratio */
u8 db2_active_fmt_ar;
- /* R0...R3 Active format aspect ratio */
+ /* ITC IT content. */
u8 db3_itc;
- /* ITC IT content. */
+ /* EC0, EC1, EC2 Extended colorimetry */
u8 db3_ec;
- /* EC0, EC1, EC2 Extended colorimetry */
+ /* Q1, Q0 Quantization range */
u8 db3_q_range;
- /* Q1, Q0 Quantization range */
+ /* SC1, SC0 Non-uniform picture scaling */
u8 db3_nup_scaling;
- /* SC1, SC0 Non-uniform picture scaling */
+ /* VIC0..6 Video format identification */
u8 db4_videocode;
- /* VIC0..6 Video format identification */
+ /* PR0..PR3 Pixel repetition factor */
u8 db5_pixel_repeat;
- /* PR0..PR3 Pixel repetition factor */
+ /* Line number end of top bar */
u16 db6_7_line_eoftop;
- /* Line number end of top bar */
+ /* Line number start of bottom bar */
u16 db8_9_line_sofbottom;
- /* Line number start of bottom bar */
+ /* Pixel number end of left bar */
u16 db10_11_pixel_eofleft;
- /* Pixel number end of left bar */
+ /* Pixel number start of right bar */
u16 db12_13_pixel_sofright;
- /* Pixel number start of right bar */
};
/*
* Refer to section 8.2 in HDMI 1.3 specification for
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/5] OMAPDSS: HDMI: Replace hdmi_reg struct with u16
2011-09-20 12:49 ` [PATCH 1/5] OMAPDSS: HDMI: Move the comments in avi infoframe mythripk
@ 2011-09-20 12:49 ` mythripk
2011-09-20 12:49 ` [PATCH 3/5] OMAPDSS: HDMI: Add missing register definitions mythripk
0 siblings, 1 reply; 10+ messages in thread
From: mythripk @ 2011-09-20 12:49 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
Remove usage of hdmi_reg struct to use u16 instead in the HDMI IP header file.
Signed-off-by: Mythri P K <mythripk@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 10 +-
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 262 ++++++++++++++---------------
2 files changed, 134 insertions(+), 138 deletions(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index da7fe50..5f22d2e 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -32,15 +32,15 @@
#include "dss.h"
static inline void hdmi_write_reg(void __iomem *base_addr,
- const struct hdmi_reg idx, u32 val)
+ const u16 idx, u32 val)
{
- __raw_writel(val, base_addr + idx.idx);
+ __raw_writel(val, base_addr + idx);
}
static inline u32 hdmi_read_reg(void __iomem *base_addr,
- const struct hdmi_reg idx)
+ const u16 idx)
{
- return __raw_readl(base_addr + idx.idx);
+ return __raw_readl(base_addr + idx);
}
static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
@@ -69,7 +69,7 @@ static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
}
static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
- const struct hdmi_reg idx,
+ const u16 idx,
int b2, int b1, u32 val)
{
u32 t = 0;
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index de1e199..694888a 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -30,142 +30,138 @@
#include <sound/pcm_params.h>
#endif
-struct hdmi_reg { u16 idx; };
-
-#define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
-
/* HDMI Wrapper */
-#define HDMI_WP_REVISION HDMI_REG(0x0)
-#define HDMI_WP_SYSCONFIG HDMI_REG(0x10)
-#define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24)
-#define HDMI_WP_IRQSTATUS HDMI_REG(0x28)
-#define HDMI_WP_PWR_CTRL HDMI_REG(0x40)
-#define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C)
-#define HDMI_WP_VIDEO_CFG HDMI_REG(0x50)
-#define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60)
-#define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68)
-#define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C)
-#define HDMI_WP_WP_CLK HDMI_REG(0x70)
-#define HDMI_WP_AUDIO_CFG HDMI_REG(0x80)
-#define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84)
-#define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88)
-#define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C)
+#define HDMI_WP_REVISION 0x0
+#define HDMI_WP_SYSCONFIG 0x10
+#define HDMI_WP_IRQSTATUS_RAW 0x24
+#define HDMI_WP_IRQSTATUS 0x28
+#define HDMI_WP_PWR_CTRL 0x40
+#define HDMI_WP_IRQENABLE_SET 0x2C
+#define HDMI_WP_VIDEO_CFG 0x50
+#define HDMI_WP_VIDEO_SIZE 0x60
+#define HDMI_WP_VIDEO_TIMING_H 0x68
+#define HDMI_WP_VIDEO_TIMING_V 0x6C
+#define HDMI_WP_WP_CLK 0x70
+#define HDMI_WP_AUDIO_CFG 0x80
+#define HDMI_WP_AUDIO_CFG2 0x84
+#define HDMI_WP_AUDIO_CTRL 0x88
+#define HDMI_WP_AUDIO_DATA 0x8C
/* HDMI IP Core System */
-#define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0)
-#define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8)
-#define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC)
-#define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10)
-#define HDMI_CORE_SYS_SRST HDMI_REG(0x14)
-#define HDMI_CORE_CTRL1 HDMI_REG(0x20)
-#define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24)
-#define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124)
-#define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128)
-#define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0)
-#define HDMI_CORE_SYS_INTR1 HDMI_REG(0x1C4)
-#define HDMI_CORE_SYS_INTR2 HDMI_REG(0x1C8)
-#define HDMI_CORE_SYS_INTR3 HDMI_REG(0x1CC)
-#define HDMI_CORE_SYS_INTR4 HDMI_REG(0x1D0)
-#define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4)
-#define HDMI_CORE_SYS_TMDS_CTRL HDMI_REG(0x208)
-#define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8)
-#define HDMI_CORE_SYS_DE_CTRL HDMI_REG(0xCC)
-#define HDMI_CORE_SYS_DE_TOP HDMI_REG(0xD0)
-#define HDMI_CORE_SYS_DE_CNTL HDMI_REG(0xD8)
-#define HDMI_CORE_SYS_DE_CNTH HDMI_REG(0xDC)
-#define HDMI_CORE_SYS_DE_LINL HDMI_REG(0xE0)
-#define HDMI_CORE_SYS_DE_LINH_1 HDMI_REG(0xE4)
+#define HDMI_CORE_SYS_VND_IDL 0x0
+#define HDMI_CORE_SYS_DEV_IDL 0x8
+#define HDMI_CORE_SYS_DEV_IDH 0xC
+#define HDMI_CORE_SYS_DEV_REV 0x10
+#define HDMI_CORE_SYS_SRST 0x14
+#define HDMI_CORE_CTRL1 0x20
+#define HDMI_CORE_SYS_SYS_STAT 0x24
+#define HDMI_CORE_SYS_VID_ACEN 0x124
+#define HDMI_CORE_SYS_VID_MODE 0x128
+#define HDMI_CORE_SYS_INTR_STATE 0x1C0
+#define HDMI_CORE_SYS_INTR1 0x1C4
+#define HDMI_CORE_SYS_INTR2 0x1C8
+#define HDMI_CORE_SYS_INTR3 0x1CC
+#define HDMI_CORE_SYS_INTR4 0x1D0
+#define HDMI_CORE_SYS_UMASK1 0x1D4
+#define HDMI_CORE_SYS_TMDS_CTRL 0x208
+#define HDMI_CORE_SYS_DE_DLY 0xC8
+#define HDMI_CORE_SYS_DE_CTRL 0xCC
+#define HDMI_CORE_SYS_DE_TOP 0xD0
+#define HDMI_CORE_SYS_DE_CNTL 0xD8
+#define HDMI_CORE_SYS_DE_CNTH 0xDC
+#define HDMI_CORE_SYS_DE_LINL 0xE0
+#define HDMI_CORE_SYS_DE_LINH_1 0xE4
#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
/* HDMI DDC E-DID */
-#define HDMI_CORE_DDC_CMD HDMI_REG(0x3CC)
-#define HDMI_CORE_DDC_STATUS HDMI_REG(0x3C8)
-#define HDMI_CORE_DDC_ADDR HDMI_REG(0x3B4)
-#define HDMI_CORE_DDC_OFFSET HDMI_REG(0x3BC)
-#define HDMI_CORE_DDC_COUNT1 HDMI_REG(0x3C0)
-#define HDMI_CORE_DDC_COUNT2 HDMI_REG(0x3C4)
-#define HDMI_CORE_DDC_DATA HDMI_REG(0x3D0)
-#define HDMI_CORE_DDC_SEGM HDMI_REG(0x3B8)
+#define HDMI_CORE_DDC_CMD 0x3CC
+#define HDMI_CORE_DDC_STATUS 0x3C8
+#define HDMI_CORE_DDC_ADDR 0x3B4
+#define HDMI_CORE_DDC_OFFSET 0x3BC
+#define HDMI_CORE_DDC_COUNT1 0x3C0
+#define HDMI_CORE_DDC_COUNT2 0x3C4
+#define HDMI_CORE_DDC_DATA 0x3D0
+#define HDMI_CORE_DDC_SEGM 0x3B8
/* HDMI IP Core Audio Video */
-#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
-#define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
-#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
-#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
-#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
-#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
-#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
-#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
-#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_REG(n * 4 + 0x110)
-#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_REG(15)
-#define HDMI_CORE_AV_SPD_DBYTE HDMI_REG(0x190)
-#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_REG(27)
-#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_REG(n * 4 + 0x210)
-#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_REG(10)
-#define HDMI_CORE_AV_MPEG_DBYTE HDMI_REG(0x290)
-#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_REG(27)
-#define HDMI_CORE_AV_GEN_DBYTE HDMI_REG(0x300)
-#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_REG(31)
-#define HDMI_CORE_AV_GEN2_DBYTE HDMI_REG(0x380)
-#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_REG(31)
-#define HDMI_CORE_AV_ACR_CTRL HDMI_REG(0x4)
-#define HDMI_CORE_AV_FREQ_SVAL HDMI_REG(0x8)
-#define HDMI_CORE_AV_N_SVAL1 HDMI_REG(0xC)
-#define HDMI_CORE_AV_N_SVAL2 HDMI_REG(0x10)
-#define HDMI_CORE_AV_N_SVAL3 HDMI_REG(0x14)
-#define HDMI_CORE_AV_CTS_SVAL1 HDMI_REG(0x18)
-#define HDMI_CORE_AV_CTS_SVAL2 HDMI_REG(0x1C)
-#define HDMI_CORE_AV_CTS_SVAL3 HDMI_REG(0x20)
-#define HDMI_CORE_AV_CTS_HVAL1 HDMI_REG(0x24)
-#define HDMI_CORE_AV_CTS_HVAL2 HDMI_REG(0x28)
-#define HDMI_CORE_AV_CTS_HVAL3 HDMI_REG(0x2C)
-#define HDMI_CORE_AV_AUD_MODE HDMI_REG(0x50)
-#define HDMI_CORE_AV_SPDIF_CTRL HDMI_REG(0x54)
-#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_REG(0x60)
-#define HDMI_CORE_AV_SWAP_I2S HDMI_REG(0x64)
-#define HDMI_CORE_AV_SPDIF_ERTH HDMI_REG(0x6C)
-#define HDMI_CORE_AV_I2S_IN_MAP HDMI_REG(0x70)
-#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_REG(0x74)
-#define HDMI_CORE_AV_I2S_CHST0 HDMI_REG(0x78)
-#define HDMI_CORE_AV_I2S_CHST1 HDMI_REG(0x7C)
-#define HDMI_CORE_AV_I2S_CHST2 HDMI_REG(0x80)
-#define HDMI_CORE_AV_I2S_CHST4 HDMI_REG(0x84)
-#define HDMI_CORE_AV_I2S_CHST5 HDMI_REG(0x88)
-#define HDMI_CORE_AV_ASRC HDMI_REG(0x8C)
-#define HDMI_CORE_AV_I2S_IN_LEN HDMI_REG(0x90)
-#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
-#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_REG(0xC0)
-#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_REG(0xCC)
-#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_REG(0xD0)
-#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_REG(0xD4)
-#define HDMI_CORE_AV_TEST_TXCTRL HDMI_REG(0xF0)
-#define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
-#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
-#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
-#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
-#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
-#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
-#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
-#define HDMI_CORE_AV_SPD_TYPE HDMI_REG(0x180)
-#define HDMI_CORE_AV_SPD_VERS HDMI_REG(0x184)
-#define HDMI_CORE_AV_SPD_LEN HDMI_REG(0x188)
-#define HDMI_CORE_AV_SPD_CHSUM HDMI_REG(0x18C)
-#define HDMI_CORE_AV_AUDIO_TYPE HDMI_REG(0x200)
-#define HDMI_CORE_AV_AUDIO_VERS HDMI_REG(0x204)
-#define HDMI_CORE_AV_AUDIO_LEN HDMI_REG(0x208)
-#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_REG(0x20C)
-#define HDMI_CORE_AV_MPEG_TYPE HDMI_REG(0x280)
-#define HDMI_CORE_AV_MPEG_VERS HDMI_REG(0x284)
-#define HDMI_CORE_AV_MPEG_LEN HDMI_REG(0x288)
-#define HDMI_CORE_AV_MPEG_CHSUM HDMI_REG(0x28C)
-#define HDMI_CORE_AV_CP_BYTE1 HDMI_REG(0x37C)
-#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_REG(0x3FC)
+#define HDMI_CORE_AV_HDMI_CTRL 0xBC
+#define HDMI_CORE_AV_DPD 0xF4
+#define HDMI_CORE_AV_PB_CTRL1 0xF8
+#define HDMI_CORE_AV_PB_CTRL2 0xFC
+#define HDMI_CORE_AV_AVI_TYPE 0x100
+#define HDMI_CORE_AV_AVI_VERS 0x104
+#define HDMI_CORE_AV_AVI_LEN 0x108
+#define HDMI_CORE_AV_AVI_CHSUM 0x10C
+#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
+#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
+#define HDMI_CORE_AV_SPD_DBYTE 0x190
+#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
+#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
+#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
+#define HDMI_CORE_AV_MPEG_DBYTE 0x290
+#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
+#define HDMI_CORE_AV_GEN_DBYTE 0x300
+#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
+#define HDMI_CORE_AV_GEN2_DBYTE 0x380
+#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
+#define HDMI_CORE_AV_ACR_CTRL 0x4
+#define HDMI_CORE_AV_FREQ_SVAL 0x8
+#define HDMI_CORE_AV_N_SVAL1 0xC
+#define HDMI_CORE_AV_N_SVAL2 0x10
+#define HDMI_CORE_AV_N_SVAL3 0x14
+#define HDMI_CORE_AV_CTS_SVAL1 0x18
+#define HDMI_CORE_AV_CTS_SVAL2 0x1C
+#define HDMI_CORE_AV_CTS_SVAL3 0x20
+#define HDMI_CORE_AV_CTS_HVAL1 0x24
+#define HDMI_CORE_AV_CTS_HVAL2 0x28
+#define HDMI_CORE_AV_CTS_HVAL3 0x2C
+#define HDMI_CORE_AV_AUD_MODE 0x50
+#define HDMI_CORE_AV_SPDIF_CTRL 0x54
+#define HDMI_CORE_AV_HW_SPDIF_FS 0x60
+#define HDMI_CORE_AV_SWAP_I2S 0x64
+#define HDMI_CORE_AV_SPDIF_ERTH 0x6C
+#define HDMI_CORE_AV_I2S_IN_MAP 0x70
+#define HDMI_CORE_AV_I2S_IN_CTRL 0x74
+#define HDMI_CORE_AV_I2S_CHST0 0x78
+#define HDMI_CORE_AV_I2S_CHST1 0x7C
+#define HDMI_CORE_AV_I2S_CHST2 0x80
+#define HDMI_CORE_AV_I2S_CHST4 0x84
+#define HDMI_CORE_AV_I2S_CHST5 0x88
+#define HDMI_CORE_AV_ASRC 0x8C
+#define HDMI_CORE_AV_I2S_IN_LEN 0x90
+#define HDMI_CORE_AV_HDMI_CTRL 0xBC
+#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0
+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4
+#define HDMI_CORE_AV_TEST_TXCTRL 0xF0
+#define HDMI_CORE_AV_DPD 0xF4
+#define HDMI_CORE_AV_PB_CTRL1 0xF8
+#define HDMI_CORE_AV_PB_CTRL2 0xFC
+#define HDMI_CORE_AV_AVI_TYPE 0x100
+#define HDMI_CORE_AV_AVI_VERS 0x104
+#define HDMI_CORE_AV_AVI_LEN 0x108
+#define HDMI_CORE_AV_AVI_CHSUM 0x10C
+#define HDMI_CORE_AV_SPD_TYPE 0x180
+#define HDMI_CORE_AV_SPD_VERS 0x184
+#define HDMI_CORE_AV_SPD_LEN 0x188
+#define HDMI_CORE_AV_SPD_CHSUM 0x18C
+#define HDMI_CORE_AV_AUDIO_TYPE 0x200
+#define HDMI_CORE_AV_AUDIO_VERS 0x204
+#define HDMI_CORE_AV_AUDIO_LEN 0x208
+#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C
+#define HDMI_CORE_AV_MPEG_TYPE 0x280
+#define HDMI_CORE_AV_MPEG_VERS 0x284
+#define HDMI_CORE_AV_MPEG_LEN 0x288
+#define HDMI_CORE_AV_MPEG_CHSUM 0x28C
+#define HDMI_CORE_AV_CP_BYTE1 0x37C
+#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC
#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
@@ -173,20 +169,20 @@ struct hdmi_reg { u16 idx; };
/* PLL */
-#define PLLCTRL_PLL_CONTROL HDMI_REG(0x0)
-#define PLLCTRL_PLL_STATUS HDMI_REG(0x4)
-#define PLLCTRL_PLL_GO HDMI_REG(0x8)
-#define PLLCTRL_CFG1 HDMI_REG(0xC)
-#define PLLCTRL_CFG2 HDMI_REG(0x10)
-#define PLLCTRL_CFG3 HDMI_REG(0x14)
-#define PLLCTRL_CFG4 HDMI_REG(0x20)
+#define PLLCTRL_PLL_CONTROL 0x0
+#define PLLCTRL_PLL_STATUS 0x4
+#define PLLCTRL_PLL_GO 0x8
+#define PLLCTRL_CFG1 0xC
+#define PLLCTRL_CFG2 0x10
+#define PLLCTRL_CFG3 0x14
+#define PLLCTRL_CFG4 0x20
/* HDMI PHY */
-#define HDMI_TXPHY_TX_CTRL HDMI_REG(0x0)
-#define HDMI_TXPHY_DIGITAL_CTRL HDMI_REG(0x4)
-#define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8)
-#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC)
+#define HDMI_TXPHY_TX_CTRL 0x0
+#define HDMI_TXPHY_DIGITAL_CTRL 0x4
+#define HDMI_TXPHY_POWER_CTRL 0x8
+#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
#define REG_FLD_MOD(base, idx, val, start, end) \
hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/5] OMAPDSS: HDMI: Add missing register definitions
2011-09-20 12:49 ` [PATCH 2/5] OMAPDSS: HDMI: Replace hdmi_reg struct with u16 mythripk
@ 2011-09-20 12:49 ` mythripk
2011-09-20 12:49 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through mythripk
0 siblings, 1 reply; 10+ messages in thread
From: mythripk @ 2011-09-20 12:49 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
Add some of the missing register definitions, which are h/w indexable.
Signed-off-by: Mythri P K <mythripk@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 694888a..2040956 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -100,15 +100,15 @@
#define HDMI_CORE_AV_AVI_CHSUM 0x10C
#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
-#define HDMI_CORE_AV_SPD_DBYTE 0x190
+#define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190)
#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
-#define HDMI_CORE_AV_MPEG_DBYTE 0x290
+#define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290)
#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
-#define HDMI_CORE_AV_GEN_DBYTE 0x300
+#define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300)
#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
-#define HDMI_CORE_AV_GEN2_DBYTE 0x380
+#define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380)
#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
#define HDMI_CORE_AV_ACR_CTRL 0x4
#define HDMI_CORE_AV_FREQ_SVAL 0x8
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through
2011-09-20 12:49 ` [PATCH 3/5] OMAPDSS: HDMI: Add missing register definitions mythripk
@ 2011-09-20 12:49 ` mythripk
2011-09-20 12:49 ` [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through mythripk
2011-09-20 13:29 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through Tomi Valkeinen
0 siblings, 2 replies; 10+ messages in thread
From: mythripk @ 2011-09-20 12:49 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
Add support to dump the HDMI core, PLL and PHY registers through debugfs
Signed-off-by: Mythri P K <mythripk@ti.com>
---
drivers/video/omap2/dss/core.c | 4 +
drivers/video/omap2/dss/dss.h | 1 +
drivers/video/omap2/dss/dss_features.c | 5 +
drivers/video/omap2/dss/hdmi.c | 16 +++
drivers/video/omap2/dss/ti_hdmi.h | 14 +++
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 168 +++++++++++++++++++++++++++++
6 files changed, 208 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 76821fe..86ec12e 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -145,6 +145,10 @@ static int dss_initialize_debugfs(void)
debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
&venc_dump_regs, &dss_debug_fops);
#endif
+#ifdef CONFIG_OMAP4_DSS_HDMI
+ debugfs_create_file("hdmi", S_IRUGO, dss_debugfs_dir,
+ &hdmi_dump_regs, &dss_debug_fops);
+#endif
return 0;
}
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 47eebd8..8652007 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -472,6 +472,7 @@ int hdmi_init_platform_driver(void);
void hdmi_uninit_platform_driver(void);
int hdmi_init_display(struct omap_dss_device *dssdev);
unsigned long hdmi_get_pixel_clock(void);
+void hdmi_dump_regs(struct seq_file *s);
#else
static inline int hdmi_init_display(struct omap_dss_device *dssdev)
{
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 47e66d8..a2fc8e0 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -447,6 +447,11 @@ static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
.pll_enable = ti_hdmi_4xxx_pll_enable,
.pll_disable = ti_hdmi_4xxx_pll_disable,
.video_enable = ti_hdmi_4xxx_wp_video_start,
+ .dump_wrapper = ti_hdmi_4xxx_wp_dump,
+ .dump_core = ti_hdmi_4xxx_core_dump,
+ .dump_pll = ti_hdmi_4xxx_pll_dump,
+ .dump_phy = ti_hdmi_4xxx_phy_dump,
+
};
void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 2f554ae..3262f0f 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -438,6 +438,22 @@ void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
}
}
+void hdmi_dump_regs(struct seq_file *s)
+{
+ mutex_lock(&hdmi.lock);
+
+ if (hdmi_runtime_get())
+ return;
+
+ hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
+ hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
+ hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
+ hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
+
+ hdmi_runtime_put();
+ mutex_unlock(&hdmi.lock);
+}
+
int omapdss_hdmi_read_edid(u8 *buf, int len)
{
int r;
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h
index d48603c..2c3443d 100644
--- a/drivers/video/omap2/dss/ti_hdmi.h
+++ b/drivers/video/omap2/dss/ti_hdmi.h
@@ -101,6 +101,15 @@ struct ti_hdmi_ip_ops {
void (*pll_disable)(struct hdmi_ip_data *ip_data);
void (*video_enable)(struct hdmi_ip_data *ip_data, bool start);
+
+ void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);
+
+ void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
+
+ void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
+
+ void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
+
};
struct hdmi_ip_data {
@@ -121,4 +130,9 @@ void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
+void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
+void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
+void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
+void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
+
#endif
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 5f22d2e..8355c4f 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -27,6 +27,7 @@
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/string.h>
+#include <linux/seq_file.h>
#include "ti_hdmi_4xxx_ip.h"
#include "dss.h"
@@ -805,6 +806,173 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
hdmi_core_av_packet_config(ip_data, repeat_cfg);
}
+void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
+{
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
+ hdmi_read_reg(hdmi_wp_base(ip_data), r))
+ DUMPREG(HDMI_WP_REVISION);
+ DUMPREG(HDMI_WP_SYSCONFIG);
+ DUMPREG(HDMI_WP_IRQSTATUS_RAW);
+ DUMPREG(HDMI_WP_IRQSTATUS);
+ DUMPREG(HDMI_WP_PWR_CTRL);
+ DUMPREG(HDMI_WP_IRQENABLE_SET);
+ DUMPREG(HDMI_WP_VIDEO_CFG);
+ DUMPREG(HDMI_WP_VIDEO_SIZE);
+ DUMPREG(HDMI_WP_VIDEO_TIMING_H);
+ DUMPREG(HDMI_WP_VIDEO_TIMING_V);
+ DUMPREG(HDMI_WP_WP_CLK);
+ DUMPREG(HDMI_WP_AUDIO_CFG);
+ DUMPREG(HDMI_WP_AUDIO_CFG2);
+ DUMPREG(HDMI_WP_AUDIO_CTRL);
+ DUMPREG(HDMI_WP_AUDIO_DATA);
+}
+
+void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
+{
+#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
+ hdmi_read_reg(hdmi_pll_base(ip_data), r))
+ DUMPPLL(PLLCTRL_PLL_CONTROL);
+ DUMPPLL(PLLCTRL_PLL_STATUS);
+ DUMPPLL(PLLCTRL_PLL_GO);
+ DUMPPLL(PLLCTRL_CFG1);
+ DUMPPLL(PLLCTRL_CFG2);
+ DUMPPLL(PLLCTRL_CFG3);
+ DUMPPLL(PLLCTRL_CFG4);
+}
+
+void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
+{
+ int i;
+#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
+ hdmi_read_reg(hdmi_pll_base(ip_data), r))
+
+ DUMPCORE(HDMI_CORE_SYS_VND_IDL);
+ DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
+ DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
+ DUMPCORE(HDMI_CORE_SYS_DEV_REV);
+ DUMPCORE(HDMI_CORE_SYS_SRST);
+ DUMPCORE(HDMI_CORE_CTRL1);
+ DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
+ DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
+ DUMPCORE(HDMI_CORE_SYS_VID_MODE);
+ DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
+ DUMPCORE(HDMI_CORE_SYS_INTR1);
+ DUMPCORE(HDMI_CORE_SYS_INTR2);
+ DUMPCORE(HDMI_CORE_SYS_INTR3);
+ DUMPCORE(HDMI_CORE_SYS_INTR4);
+ DUMPCORE(HDMI_CORE_SYS_UMASK1);
+ DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
+ DUMPCORE(HDMI_CORE_SYS_DE_DLY);
+ DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
+ DUMPCORE(HDMI_CORE_SYS_DE_TOP);
+ DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
+ DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
+ DUMPCORE(HDMI_CORE_SYS_DE_LINL);
+ DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
+
+ DUMPCORE(HDMI_CORE_DDC_CMD);
+ DUMPCORE(HDMI_CORE_DDC_STATUS);
+ DUMPCORE(HDMI_CORE_DDC_ADDR);
+ DUMPCORE(HDMI_CORE_DDC_OFFSET);
+ DUMPCORE(HDMI_CORE_DDC_COUNT1);
+ DUMPCORE(HDMI_CORE_DDC_COUNT2);
+ DUMPCORE(HDMI_CORE_DDC_DATA);
+ DUMPCORE(HDMI_CORE_DDC_SEGM);
+
+ DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
+ DUMPCORE(HDMI_CORE_AV_DPD);
+ DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
+ DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
+ DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
+ DUMPCORE(HDMI_CORE_AV_AVI_VERS);
+ DUMPCORE(HDMI_CORE_AV_AVI_LEN);
+ DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
+
+ for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
+ DUMPCORE(HDMI_CORE_AV_AVI_DBYTE(i));
+
+ for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
+ DUMPCORE(HDMI_CORE_AV_SPD_DBYTE(i));
+
+ for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
+ DUMPCORE(HDMI_CORE_AV_AUD_DBYTE(i));
+
+ for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
+ DUMPCORE(HDMI_CORE_AV_MPEG_DBYTE(i));
+
+ for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
+ DUMPCORE(HDMI_CORE_AV_GEN_DBYTE(i));
+
+ for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
+ DUMPCORE(HDMI_CORE_AV_GEN2_DBYTE(i));
+
+ DUMPCORE(HDMI_CORE_AV_ACR_CTRL);
+ DUMPCORE(HDMI_CORE_AV_FREQ_SVAL);
+ DUMPCORE(HDMI_CORE_AV_N_SVAL1);
+ DUMPCORE(HDMI_CORE_AV_N_SVAL2);
+ DUMPCORE(HDMI_CORE_AV_N_SVAL3);
+ DUMPCORE(HDMI_CORE_AV_CTS_SVAL1);
+ DUMPCORE(HDMI_CORE_AV_CTS_SVAL2);
+ DUMPCORE(HDMI_CORE_AV_CTS_SVAL3);
+ DUMPCORE(HDMI_CORE_AV_CTS_HVAL1);
+ DUMPCORE(HDMI_CORE_AV_CTS_HVAL2);
+ DUMPCORE(HDMI_CORE_AV_CTS_HVAL3);
+ DUMPCORE(HDMI_CORE_AV_AUD_MODE);
+ DUMPCORE(HDMI_CORE_AV_SPDIF_CTRL);
+ DUMPCORE(HDMI_CORE_AV_HW_SPDIF_FS);
+ DUMPCORE(HDMI_CORE_AV_SWAP_I2S);
+ DUMPCORE(HDMI_CORE_AV_SPDIF_ERTH);
+ DUMPCORE(HDMI_CORE_AV_I2S_IN_MAP);
+ DUMPCORE(HDMI_CORE_AV_I2S_IN_CTRL);
+ DUMPCORE(HDMI_CORE_AV_I2S_CHST0);
+ DUMPCORE(HDMI_CORE_AV_I2S_CHST1);
+ DUMPCORE(HDMI_CORE_AV_I2S_CHST2);
+ DUMPCORE(HDMI_CORE_AV_I2S_CHST4);
+ DUMPCORE(HDMI_CORE_AV_I2S_CHST5);
+ DUMPCORE(HDMI_CORE_AV_ASRC);
+ DUMPCORE(HDMI_CORE_AV_I2S_IN_LEN);
+ DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
+ DUMPCORE(HDMI_CORE_AV_AUDO_TXSTAT);
+ DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
+ DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
+ DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
+ DUMPCORE(HDMI_CORE_AV_TEST_TXCTRL);
+ DUMPCORE(HDMI_CORE_AV_DPD);
+ DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
+ DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
+ DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
+ DUMPCORE(HDMI_CORE_AV_AVI_VERS);
+ DUMPCORE(HDMI_CORE_AV_AVI_LEN);
+ DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
+ DUMPCORE(HDMI_CORE_AV_SPD_TYPE);
+ DUMPCORE(HDMI_CORE_AV_SPD_VERS);
+ DUMPCORE(HDMI_CORE_AV_SPD_LEN);
+ DUMPCORE(HDMI_CORE_AV_SPD_CHSUM);
+ DUMPCORE(HDMI_CORE_AV_AUDIO_TYPE);
+ DUMPCORE(HDMI_CORE_AV_AUDIO_VERS);
+ DUMPCORE(HDMI_CORE_AV_AUDIO_LEN);
+ DUMPCORE(HDMI_CORE_AV_AUDIO_CHSUM);
+ DUMPCORE(HDMI_CORE_AV_MPEG_TYPE);
+ DUMPCORE(HDMI_CORE_AV_MPEG_VERS);
+ DUMPCORE(HDMI_CORE_AV_MPEG_LEN);
+ DUMPCORE(HDMI_CORE_AV_MPEG_CHSUM);
+ DUMPCORE(HDMI_CORE_AV_CP_BYTE1);
+ DUMPCORE(HDMI_CORE_AV_CEC_ADDR_ID);
+}
+
+void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
+{
+#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
+ hdmi_read_reg(hdmi_pll_base(ip_data), r))
+ DUMPPHY(PLLCTRL_PLL_CONTROL);
+ DUMPPHY(PLLCTRL_PLL_STATUS);
+ DUMPPHY(PLLCTRL_PLL_GO);
+ DUMPPHY(PLLCTRL_CFG1);
+ DUMPPHY(PLLCTRL_CFG2);
+ DUMPPHY(PLLCTRL_CFG3);
+ DUMPPHY(PLLCTRL_CFG4);
+}
+
#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through
2011-09-20 12:49 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through mythripk
@ 2011-09-20 12:49 ` mythripk
2011-09-20 13:31 ` Tomi Valkeinen
2011-09-20 13:29 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through Tomi Valkeinen
1 sibling, 1 reply; 10+ messages in thread
From: mythripk @ 2011-09-20 12:49 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
Add support to dump the HDMI regm, regn, and other clock parameters.
Signed-off-by: Mythri P K <mythripk@ti.com>
---
drivers/video/omap2/dss/dss.c | 3 +++
drivers/video/omap2/dss/dss.h | 1 +
drivers/video/omap2/dss/hdmi.c | 31 +++++++++++++++++++++++++++++++
3 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 3e09726..816daef 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -732,6 +732,9 @@ void dss_debug_dump_clocks(struct seq_file *s)
#ifdef CONFIG_OMAP2_DSS_DSI
dsi_dump_clocks(s);
#endif
+#ifdef CONFIG_OMAP2_DSS_HDMI
+ hdmi_dump_clocks(s);
+#endif
}
#endif
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 8652007..ef8770a 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -473,6 +473,7 @@ void hdmi_uninit_platform_driver(void);
int hdmi_init_display(struct omap_dss_device *dssdev);
unsigned long hdmi_get_pixel_clock(void);
void hdmi_dump_regs(struct seq_file *s);
+void hdmi_dump_clocks(struct seq_file *s);
#else
static inline int hdmi_init_display(struct omap_dss_device *dssdev)
{
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 3262f0f..6751b1a 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -33,6 +33,8 @@
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <video/omapdss.h>
+#include <linux/seq_file.h>
+
#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
#include <sound/soc.h>
@@ -454,6 +456,35 @@ void hdmi_dump_regs(struct seq_file *s)
mutex_unlock(&hdmi.lock);
}
+void hdmi_dump_clocks(struct seq_file *s)
+{
+ enum omap_dss_clk_source dispc_clk_src;
+
+ dispc_clk_src = dss_get_dispc_clk_source();
+
+ if (hdmi_runtime_get())
+ return;
+
+ seq_printf(s, "HDMI Clock Info\n");
+
+ seq_printf(s, "regm\t\t%dregmf %u\n",
+ hdmi.ip_data.pll_data.regm, hdmi.ip_data.pll_data.regm);
+
+ seq_printf(s, "dcofreq\t%dregsd %u\n",
+ hdmi.ip_data.pll_data.dcofreq,
+ hdmi.ip_data.pll_data.regsd);
+
+ seq_printf(s, "%s (%s)\t(%s)\n",
+ dss_get_generic_clk_source_name(dispc_clk_src),
+ dss_feat_get_clk_source_name(dispc_clk_src),
+ dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
+ "off" : "on");
+
+ seq_printf(s, "hdmi fclk source = %d\n", hdmi.ip_data.pll_data.refsel);
+
+ hdmi_runtime_put();
+}
+
int omapdss_hdmi_read_edid(u8 *buf, int len)
{
int r;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through
2011-09-20 12:49 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through mythripk
2011-09-20 12:49 ` [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through mythripk
@ 2011-09-20 13:29 ` Tomi Valkeinen
1 sibling, 0 replies; 10+ messages in thread
From: Tomi Valkeinen @ 2011-09-20 13:29 UTC (permalink / raw)
To: mythripk; +Cc: linux-omap
On Tue, 2011-09-20 at 18:19 +0530, mythripk@ti.com wrote:
> From: Mythri P K <mythripk@ti.com>
>
> Add support to dump the HDMI core, PLL and PHY registers through debugfs
The subject seems to be broken.
This prints PLL registers twice, second time is when it should be
printing PHY registers.
It also prints lines like:
HDMI_CORE_AV_SPD_DBYTE(i) 00000000
HDMI_CORE_AV_SPD_DBYTE(i) 00000000
HDMI_CORE_AV_SPD_DBYTE(i) 00000000
HDMI_CORE_AV_SPD_DBYTE(i) 00000000
Tomi
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through
2011-09-20 12:49 ` [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through mythripk
@ 2011-09-20 13:31 ` Tomi Valkeinen
2011-09-20 15:36 ` K, Mythri P
0 siblings, 1 reply; 10+ messages in thread
From: Tomi Valkeinen @ 2011-09-20 13:31 UTC (permalink / raw)
To: mythripk; +Cc: linux-omap
On Tue, 2011-09-20 at 18:19 +0530, mythripk@ti.com wrote:
> From: Mythri P K <mythripk@ti.com>
>
> Add support to dump the HDMI regm, regn, and other clock parameters.
This patch doesn't work at all. It's checking for CONFIG_OMAP2_DSS_HDMI,
whereas the actual define is CONFIG_OMAP4_DSS_HDMI. And even after
fixing that, the output is:
HDMI Clock Info
regm 104regmf 104
dcofreq 0regsd 1
DSS_FCK (DSS_FCLK) (off)
hdmi fclk source = 3
Did you test your patches at all?
Tomi
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through
2011-09-20 13:31 ` Tomi Valkeinen
@ 2011-09-20 15:36 ` K, Mythri P
2011-09-20 15:42 ` Tomi Valkeinen
0 siblings, 1 reply; 10+ messages in thread
From: K, Mythri P @ 2011-09-20 15:36 UTC (permalink / raw)
To: Tomi Valkeinen; +Cc: linux-omap
Hi,
On Tue, Sep 20, 2011 at 7:01 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote:
> On Tue, 2011-09-20 at 18:19 +0530, mythripk@ti.com wrote:
>> From: Mythri P K <mythripk@ti.com>
>>
>> Add support to dump the HDMI regm, regn, and other clock parameters.
>
> This patch doesn't work at all. It's checking for CONFIG_OMAP2_DSS_HDMI,
> whereas the actual define is CONFIG_OMAP4_DSS_HDMI. And even after
> fixing that, the output is:
>
> HDMI Clock Info
> regm 104regmf 104
> dcofreq 0regsd 1
> DSS_FCK (DSS_FCLK) (off)
> hdmi fclk source = 3
>
These are the reg m , mf , dcofreq , by default the HDMI clock input is sysclk ,
These values are based on the pixel clock.I suppose all the other
clock values are
printed via dss / dispc clock dump , is there any other dump that is missing?
Thanks and regards,
Mythri.
> Did you test your patches at all?
>
> Tomi
>
>
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through
2011-09-20 15:36 ` K, Mythri P
@ 2011-09-20 15:42 ` Tomi Valkeinen
0 siblings, 0 replies; 10+ messages in thread
From: Tomi Valkeinen @ 2011-09-20 15:42 UTC (permalink / raw)
To: K, Mythri P; +Cc: linux-omap
On Tue, 2011-09-20 at 21:06 +0530, K, Mythri P wrote:
> Hi,
>
> On Tue, Sep 20, 2011 at 7:01 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote:
> > On Tue, 2011-09-20 at 18:19 +0530, mythripk@ti.com wrote:
> >> From: Mythri P K <mythripk@ti.com>
> >>
> >> Add support to dump the HDMI regm, regn, and other clock parameters.
> >
> > This patch doesn't work at all. It's checking for CONFIG_OMAP2_DSS_HDMI,
> > whereas the actual define is CONFIG_OMAP4_DSS_HDMI. And even after
> > fixing that, the output is:
> >
> > HDMI Clock Info
> > regm 104regmf 104
> > dcofreq 0regsd 1
> > DSS_FCK (DSS_FCLK) (off)
> > hdmi fclk source = 3
> >
> These are the reg m , mf , dcofreq , by default the HDMI clock input is sysclk ,
> These values are based on the pixel clock.I suppose all the other
> clock values are
> printed via dss / dispc clock dump , is there any other dump that is missing?
I don't know, as the output was so garbled that I didn't look any
further.
But just look at the outputs from other interfaces, mainly DSI. Make the
output format similar, and print relevant information in the same way.
Tomi
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2011-09-20 15:42 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-09-20 12:49 [PATCH 0/5] OMAPDSS: HDMI: Debug support and Register cleanup mythripk
2011-09-20 12:49 ` [PATCH 1/5] OMAPDSS: HDMI: Move the comments in avi infoframe mythripk
2011-09-20 12:49 ` [PATCH 2/5] OMAPDSS: HDMI: Replace hdmi_reg struct with u16 mythripk
2011-09-20 12:49 ` [PATCH 3/5] OMAPDSS: HDMI: Add missing register definitions mythripk
2011-09-20 12:49 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through mythripk
2011-09-20 12:49 ` [PATCH 5/5] OMAPDSS: HDMI: Add support to dump clocks through mythripk
2011-09-20 13:31 ` Tomi Valkeinen
2011-09-20 15:36 ` K, Mythri P
2011-09-20 15:42 ` Tomi Valkeinen
2011-09-20 13:29 ` [PATCH 4/5] OMAPDSS: HDMI: Add support to dump registers through Tomi Valkeinen
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