From mboxrd@z Thu Jan 1 00:00:00 1970 From: Grazvydas Ignotas Subject: [PATCH] ARM: OMAP: sram: fix BUG in dpll code for !PM case Date: Sat, 7 Apr 2012 00:53:21 +0300 Message-ID: <1333749201-23255-1-git-send-email-notasas@gmail.com> Return-path: Received: from mail-we0-f174.google.com ([74.125.82.174]:33607 "EHLO mail-we0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752650Ab2DFVx2 (ORCPT ); Fri, 6 Apr 2012 17:53:28 -0400 Received: by wejx9 with SMTP id x9so1663326wej.19 for ; Fri, 06 Apr 2012 14:53:27 -0700 (PDT) Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Tony Lindgren , Grazvydas Ignotas _omap3_sram_configure_core_dpll is called when SDRC is reprogrammed, which is done regardless of CONFIG_PM setting, so we always need it's setup code too. Without this, we hit a BUG() on OMAP3 when kernel is built without CONFIG_PM: Reprogramming SDRC clock to 332000000 Hz ------------[ cut here ]------------ kernel BUG at arch/arm/plat-omap/sram.c:342! Internal error: Oops - BUG: 0 [#1] ARM ... [] (omap3_configure_core_dpll+0x68/0x6c) from [] (omap3_core_dpll_m2_set_rate+0x1) [] (omap3_core_dpll_m2_set_rate+0x138/0x1b0) from [] (omap2_clk_set_rate+0x14/0x2) [] (omap2_clk_set_rate+0x14/0x20) from [] (clk_set_rate+0x54/0x74) [] (clk_set_rate+0x54/0x74) from [] (omap_sdrc_init+0x70/0x90) [] (omap_sdrc_init+0x70/0x90) from [] (omap3pandora_init+0x11c/0x164) [] (omap3pandora_init+0x11c/0x164) from [] (customize_machine+0x20/0x28) [] (customize_machine+0x20/0x28) from [] (do_one_initcall+0xa0/0x16c) [] (do_one_initcall+0xa0/0x16c) from [] (kernel_init+0x104/0x1ac) [] (kernel_init+0x104/0x1ac) from [] (kernel_thread_exit+0x0/0x8) Signed-off-by: Grazvydas Ignotas --- arch/arm/plat-omap/sram.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index eec98af..f9a8c53 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, sdrc_actim_ctrl_b_1, sdrc_mr_1); } -#ifdef CONFIG_PM void omap3_sram_restore_context(void) { omap_sram_ceil = omap_sram_base + omap_sram_size; @@ -358,17 +357,18 @@ void omap3_sram_restore_context(void) omap3_sram_configure_core_dpll_sz); omap_push_sram_idle(); } -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_OMAP3 */ static inline int omap34xx_sram_init(void) { -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) omap3_sram_restore_context(); -#endif return 0; } +#else +static inline int omap34xx_sram_init(void) +{ + return 0; +} +#endif /* CONFIG_ARCH_OMAP3 */ static inline int am33xx_sram_init(void) { -- 1.7.0.4