* [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.
@ 2013-05-30 19:54 Ruchika Kharwar
2013-06-21 7:42 ` George Cherian
0 siblings, 1 reply; 6+ messages in thread
From: Ruchika Kharwar @ 2013-05-30 19:54 UTC (permalink / raw)
To: linux-usb, linux-omap
Cc: Felipe Balbi, Kishon Vijay Abraham I, Greg Kroah-Hartman,
Ruchika Kharwar
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.
This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
---
drivers/usb/phy/phy-omap-usb3.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index a6e60b1..efe6e14 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
@@ -27,7 +27,7 @@
#include <linux/delay.h>
#include <linux/usb/omap_control_usb.h>
-#define NUM_SYS_CLKS 5
+#define NUM_SYS_CLKS 6
#define PLL_STATUS 0x00000004
#define PLL_GO 0x00000008
#define PLL_CONFIGURATION1 0x0000000C
@@ -62,6 +62,7 @@ enum sys_clk_rate {
CLK_RATE_12MHZ,
CLK_RATE_16MHZ,
CLK_RATE_19MHZ,
+ CLK_RATE_20MHZ,
CLK_RATE_26MHZ,
CLK_RATE_38MHZ
};
@@ -72,6 +73,8 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
{1250, 12, 4, 20, 0}, /* 26 MHz */
{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
+ {1000, 7, 4, 10, 0}, /* 20 MHz */
+
};
static int omap_usb3_suspend(struct usb_phy *x, int suspend)
@@ -122,6 +125,8 @@ static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
return CLK_RATE_16MHZ;
case 19200000:
return CLK_RATE_19MHZ;
+ case 20000000:
+ return CLK_RATE_20MHZ;
case 26000000:
return CLK_RATE_26MHZ;
case 38400000:
--
1.7.5.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.
2013-05-30 19:54 Ruchika Kharwar
@ 2013-06-21 7:42 ` George Cherian
0 siblings, 0 replies; 6+ messages in thread
From: George Cherian @ 2013-06-21 7:42 UTC (permalink / raw)
To: Ruchika Kharwar
Cc: linux-usb, linux-omap, Felipe Balbi, Kishon Vijay Abraham I,
Greg Kroah-Hartman
On 5/31/2013 1:24 AM, Ruchika Kharwar wrote:
> Addition of the M and N recommended values for the USB3 PHY DPLL.
> Sysclk for DRA7xx is 20MHz.
> This yields:
> Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
>
> Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
> ---
> drivers/usb/phy/phy-omap-usb3.c | 7 ++++++-
> 1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
> index a6e60b1..efe6e14 100644
> --- a/drivers/usb/phy/phy-omap-usb3.c
> +++ b/drivers/usb/phy/phy-omap-usb3.c
> @@ -27,7 +27,7 @@
> #include <linux/delay.h>
> #include <linux/usb/omap_control_usb.h>
>
> -#define NUM_SYS_CLKS 5
> +#define NUM_SYS_CLKS 6
> #define PLL_STATUS 0x00000004
> #define PLL_GO 0x00000008
> #define PLL_CONFIGURATION1 0x0000000C
> @@ -62,6 +62,7 @@ enum sys_clk_rate {
> CLK_RATE_12MHZ,
> CLK_RATE_16MHZ,
> CLK_RATE_19MHZ,
> + CLK_RATE_20MHZ,
> CLK_RATE_26MHZ,
> CLK_RATE_38MHZ
> };
> @@ -72,6 +73,8 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
> {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
> {1250, 12, 4, 20, 0}, /* 26 MHz */
> {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
> + {1000, 7, 4, 10, 0}, /* 20 MHz */
> +
> };
>
CLK_RATE_20MHZ is 3 but 20MHz value added in array at offset 5???
> static int omap_usb3_suspend(struct usb_phy *x, int suspend)
> @@ -122,6 +125,8 @@ static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
> return CLK_RATE_16MHZ;
> case 19200000:
> return CLK_RATE_19MHZ;
> + case 20000000:
> + return CLK_RATE_20MHZ;
> case 26000000:
> return CLK_RATE_26MHZ;
> case 38400000:
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.
@ 2013-06-21 15:46 Ruchika Kharwar
2013-07-08 7:28 ` Felipe Balbi
0 siblings, 1 reply; 6+ messages in thread
From: Ruchika Kharwar @ 2013-06-21 15:46 UTC (permalink / raw)
To: linux-usb, linux-doc, linux-omap
Cc: Felipe Balbi, Kishon Vijay Abraham I, Greg Kroah-Hartman,
Rob Landley, Ruchika Kharwar, Nikhil Devshatwar
Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.
This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
---
drivers/usb/phy/phy-omap-usb3.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index a6e60b1..a2fb30b 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
@@ -27,7 +27,7 @@
#include <linux/delay.h>
#include <linux/usb/omap_control_usb.h>
-#define NUM_SYS_CLKS 5
+#define NUM_SYS_CLKS 6
#define PLL_STATUS 0x00000004
#define PLL_GO 0x00000008
#define PLL_CONFIGURATION1 0x0000000C
@@ -62,6 +62,7 @@ enum sys_clk_rate {
CLK_RATE_12MHZ,
CLK_RATE_16MHZ,
CLK_RATE_19MHZ,
+ CLK_RATE_20MHZ,
CLK_RATE_26MHZ,
CLK_RATE_38MHZ
};
@@ -70,8 +71,10 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
{1250, 5, 4, 20, 0}, /* 12 MHz */
{3125, 20, 4, 20, 0}, /* 16.8 MHz */
{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
+ {1000, 7, 4, 10, 0}, /* 20 MHz */
{1250, 12, 4, 20, 0}, /* 26 MHz */
{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
+
};
static int omap_usb3_suspend(struct usb_phy *x, int suspend)
@@ -122,6 +125,8 @@ static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
return CLK_RATE_16MHZ;
case 19200000:
return CLK_RATE_19MHZ;
+ case 20000000:
+ return CLK_RATE_20MHZ;
case 26000000:
return CLK_RATE_26MHZ;
case 38400000:
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.
2013-06-21 15:46 [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values Ruchika Kharwar
@ 2013-07-08 7:28 ` Felipe Balbi
2013-07-08 14:33 ` Ruchika Kharwar
0 siblings, 1 reply; 6+ messages in thread
From: Felipe Balbi @ 2013-07-08 7:28 UTC (permalink / raw)
To: Ruchika Kharwar
Cc: linux-usb, linux-doc, linux-omap, Felipe Balbi,
Kishon Vijay Abraham I, Greg Kroah-Hartman, Rob Landley,
Nikhil Devshatwar
[-- Attachment #1: Type: text/plain, Size: 478 bytes --]
On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote:
> Addition of the M and N recommended values for the USB3 PHY DPLL.
> Sysclk for DRA7xx is 20MHz.
> This yields:
> Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
>
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
this won't apply since you had already sent me another version. Please
send in a fix up patch if that's wrong.
--
balbi
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.
2013-07-08 7:28 ` Felipe Balbi
@ 2013-07-08 14:33 ` Ruchika Kharwar
[not found] ` <51DACDA2.1060806-l0cyMroinI0@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Ruchika Kharwar @ 2013-07-08 14:33 UTC (permalink / raw)
To: balbi
Cc: linux-usb, linux-doc, linux-omap, Kishon Vijay Abraham I,
Greg Kroah-Hartman, Rob Landley, Nikhil Devshatwar
On 07/08/2013 02:28 AM, Felipe Balbi wrote:
> On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote:
>> Addition of the M and N recommended values for the USB3 PHY DPLL.
>> Sysclk for DRA7xx is 20MHz.
>> This yields:
>> Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
>>
>> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
>> Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
> this won't apply since you had already sent me another version. Please
> send in a fix up patch if that's wrong.
>
I already did .. :-)
Sent 07/04/2013
Correction of the omap_usb3_dpll_params array when the sys_clk_rate is
20MHz.
Signed-off-by: Nikhil Devshatwar<nikhil.nd@ti.com>
Signed-off-by: Ruchika Kharwar<ruchika@ti.com>
---
drivers/usb/phy/phy-omap-usb3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index efe6e14..a2fb30b 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
@@ -71,9 +71,9 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
{1250, 5, 4, 20, 0}, /* 12 MHz */
{3125, 20, 4, 20, 0}, /* 16.8 MHz */
{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
+ {1000, 7, 4, 10, 0}, /* 20 MHz */
{1250, 12, 4, 20, 0}, /* 26 MHz */
{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
- {1000, 7, 4, 10, 0}, /* 20 MHz */
};
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.
[not found] ` <51DACDA2.1060806-l0cyMroinI0@public.gmane.org>
@ 2013-07-09 11:43 ` Roger Quadros
0 siblings, 0 replies; 6+ messages in thread
From: Roger Quadros @ 2013-07-09 11:43 UTC (permalink / raw)
To: Ruchika Kharwar
Cc: balbi-l0cyMroinI0, linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA, Kishon Vijay Abraham I,
Greg Kroah-Hartman, Rob Landley, Nikhil Devshatwar
On 07/08/2013 05:33 PM, Ruchika Kharwar wrote:
>
> On 07/08/2013 02:28 AM, Felipe Balbi wrote:
>> On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote:
>>> Addition of the M and N recommended values for the USB3 PHY DPLL.
>>> Sysclk for DRA7xx is 20MHz.
>>> This yields:
>>> Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
>>>
>>> Signed-off-by: Nikhil Devshatwar <nikhil.nd-l0cyMroinI0@public.gmane.org>
>>> Signed-off-by: Ruchika Kharwar <ruchika-l0cyMroinI0@public.gmane.org>
>> this won't apply since you had already sent me another version. Please
>> send in a fix up patch if that's wrong.
>>
> I already did .. :-)
> Sent 07/04/2013
FYI, I've just sent a better version to fix the root of the problem,
i.e. use lookup table instead of index based lookup.
That should avoid such problems in the future.
cheers,
-roger
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2013-06-21 15:46 [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values Ruchika Kharwar
2013-07-08 7:28 ` Felipe Balbi
2013-07-08 14:33 ` Ruchika Kharwar
[not found] ` <51DACDA2.1060806-l0cyMroinI0@public.gmane.org>
2013-07-09 11:43 ` Roger Quadros
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2013-06-21 7:42 ` George Cherian
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