From mboxrd@z Thu Jan 1 00:00:00 1970 From: Felipe Balbi Subject: [RFT/RFC/PATCH 02/31] arm: omap: irq: define INTC_ILR0 register Date: Wed, 20 Nov 2013 12:08:49 -0600 Message-ID: <1384970958-4118-3-git-send-email-balbi@ti.com> References: <1384970958-4118-1-git-send-email-balbi@ti.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Received: from devils.ext.ti.com ([198.47.26.153]:52563 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754596Ab3KTSKL (ORCPT ); Wed, 20 Nov 2013 13:10:11 -0500 In-Reply-To: <1384970958-4118-1-git-send-email-balbi@ti.com> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Tony Lindgren Cc: Linux OMAP Mailing List , Linux ARM Kernel Mailing List , Felipe Balbi this is currently used as a hardcoded 0x100 offset. Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 748f86b..c9539b1 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -41,6 +41,7 @@ #define INTC_MIR_CLEAR0 0x0088 #define INTC_MIR_SET0 0x008c #define INTC_PENDING_IRQ0 0x0098 +#define INTC_ILR0 0x0100 /* Number of IRQ state bits in each MIR register */ #define IRQ_BITS_PER_REG 32 -- 1.8.4.GIT