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From: Tomasz Figa <t.figa@samsung.com>
To: linux-samsung-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
	Kukjin Kim <kgene.kim@samsung.com>,
	Laura Abbott <lauraa@codeaurora.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Robin Holt <holt@sgi.com>, Russell King <linux@arm.linux.org.uk>,
	Santosh Shilimkar <santosh.shilimkar@ti.com>,
	Tony Lindgren <tony@atomide.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Tomasz Figa <t.figa@samsung.com>
Subject: [PATCH 3/5] ARM: mm: cache-l2x0: Use l2c_write_sec() for LATENCY_CTRL registers
Date: Wed, 11 Jun 2014 17:30:10 +0200	[thread overview]
Message-ID: <1402500612-4778-4-git-send-email-t.figa@samsung.com> (raw)
In-Reply-To: <1402500612-4778-1-git-send-email-t.figa@samsung.com>

According to the documentation, TAG_LATENCY_CTRL and DATA_LATENCY_CTRL
registers of L2C-310 can be written only in secure mode, so
l2c_write_sec() should be used to change them, instead of plain
writel_relaxed().

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
 arch/arm/mm/cache-l2x0.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 1695eab..0180eb7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1024,20 +1024,20 @@ static void __init l2c310_of_parse(const struct device_node *np,
 
 	of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
 	if (tag[0] && tag[1] && tag[2])
-		writel_relaxed(
+		l2c_write_sec(
 			L310_LATENCY_CTRL_RD(tag[0] - 1) |
 			L310_LATENCY_CTRL_WR(tag[1] - 1) |
 			L310_LATENCY_CTRL_SETUP(tag[2] - 1),
-			l2x0_base + L310_TAG_LATENCY_CTRL);
+			l2x0_base, L310_TAG_LATENCY_CTRL);
 
 	of_property_read_u32_array(np, "arm,data-latency",
 				   data, ARRAY_SIZE(data));
 	if (data[0] && data[1] && data[2])
-		writel_relaxed(
+		l2c_write_sec(
 			L310_LATENCY_CTRL_RD(data[0] - 1) |
 			L310_LATENCY_CTRL_WR(data[1] - 1) |
 			L310_LATENCY_CTRL_SETUP(data[2] - 1),
-			l2x0_base + L310_DATA_LATENCY_CTRL);
+			l2x0_base, L310_DATA_LATENCY_CTRL);
 
 	of_property_read_u32_array(np, "arm,filter-ranges",
 				   filter, ARRAY_SIZE(filter));
-- 
1.9.3

  parent reply	other threads:[~2014-06-11 15:30 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-11 15:30 [PATCH 0/5] Handle non-secure L2C initialization on Exynos4 Tomasz Figa
2014-06-11 15:30 ` [PATCH 1/5] ARM: mm: cache-l2x0: Add base address argument to write_sec callback Tomasz Figa
2014-06-11 16:00   ` Jon Loeliger
2014-06-11 16:07     ` Tomasz Figa
2014-06-11 15:30 ` [PATCH 2/5] ARM: Get outer cache .write_sec callback from mach_desc only if not NULL Tomasz Figa
2014-06-11 15:30 ` Tomasz Figa [this message]
2014-06-11 15:30 ` [PATCH 4/5] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Tomasz Figa
2014-06-11 15:30 ` [PATCH 5/5] ARM: dts: exynos4: Add nodes for L2 cache controller Tomasz Figa

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